forked from Minki/linux
[PATCH] m68knommu: ColdFire 532x CPU startup code
Add kernel startup code for the new Freescale 532x CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Greg Ungerer
Linus Torvalds
parent
b671b653da
commit
3196cf83ad
486
arch/m68knommu/platform/532x/config.c
Normal file
486
arch/m68knommu/platform/532x/config.c
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@ -0,0 +1,486 @@
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/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/532x/config.c
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*
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* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2000, Lineo (www.lineo.com)
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* Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
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* Copyright Freescale Semiconductor, Inc 2006
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* Copyright (c) 2006, emlix, Sebastian Hess <sh@emlix.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/***************************************************************************/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/dma.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcftimer.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfdma.h>
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#include <asm/mcfwdebug.h>
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/***************************************************************************/
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void coldfire_tick(void);
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void coldfire_timer_init(irqreturn_t (*handler)(int, void *, struct pt_regs *));
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unsigned long coldfire_timer_offset(void);
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void coldfire_trap_init(void);
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void coldfire_reset(void);
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extern unsigned int mcf_timervector;
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extern unsigned int mcf_profilevector;
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extern unsigned int mcf_timerlevel;
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/***************************************************************************/
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/*
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* DMA channel base address table.
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*/
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unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = { };
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unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
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/***************************************************************************/
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void mcf_settimericr(unsigned int timer, unsigned int level)
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{
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volatile unsigned char *icrp;
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unsigned int icr;
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unsigned char irq;
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if (timer <= 2) {
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switch (timer) {
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case 2: irq = 33; icr = MCFSIM_ICR_TIMER2; break;
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default: irq = 32; icr = MCFSIM_ICR_TIMER1; break;
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}
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icrp = (volatile unsigned char *) (MCF_MBAR + icr);
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*icrp = level;
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mcf_enable_irq0(irq);
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}
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}
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/***************************************************************************/
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int mcf_timerirqpending(int timer)
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{
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unsigned int imr = 0;
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switch (timer) {
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case 1: imr = 0x1; break;
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case 2: imr = 0x2; break;
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default: break;
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}
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return (mcf_getiprh() & imr);
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}
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/***************************************************************************/
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void config_BSP(char *commandp, int size)
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{
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mcf_setimr(MCFSIM_IMR_MASKALL);
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#if defined(CONFIG_BOOTPARAM)
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strncpy(commandp, CONFIG_BOOTPARAM_STRING, size);
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commandp[size-1] = 0;
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#else
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/* Copy command line from FLASH to local buffer... */
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memcpy(commandp, (char *) 0x4000, 4);
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if(strncmp(commandp, "kcl ", 4) == 0){
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memcpy(commandp, (char *) 0x4004, size);
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commandp[size-1] = 0;
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} else {
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memset(commandp, 0, size);
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}
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#endif
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mcf_timervector = 64+32;
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mcf_profilevector = 64+33;
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mach_sched_init = coldfire_timer_init;
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mach_tick = coldfire_tick;
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mach_gettimeoffset = coldfire_timer_offset;
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mach_trap_init = coldfire_trap_init;
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mach_reset = coldfire_reset;
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#ifdef MCF_BDM_DISABLE
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/*
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* Disable the BDM clocking. This also turns off most of the rest of
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* the BDM device. This is good for EMC reasons. This option is not
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* incompatible with the memory protection option.
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*/
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wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
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#endif
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}
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/***************************************************************************/
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/* Board initialization */
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/********************************************************************/
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/*
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* PLL min/max specifications
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*/
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#define MAX_FVCO 500000 /* KHz */
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#define MAX_FSYS 80000 /* KHz */
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#define MIN_FSYS 58333 /* KHz */
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#define FREF 16000 /* KHz */
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#define MAX_MFD 135 /* Multiplier */
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#define MIN_MFD 88 /* Multiplier */
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#define BUSDIV 6 /* Divider */
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/*
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* Low Power Divider specifications
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*/
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#define MIN_LPD (1 << 0) /* Divider (not encoded) */
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#define MAX_LPD (1 << 15) /* Divider (not encoded) */
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#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
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#define SYS_CLK_KHZ 80000
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#define SYSTEM_PERIOD 12.5
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/*
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* SDRAM Timing Parameters
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*/
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#define SDRAM_BL 8 /* # of beats in a burst */
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#define SDRAM_TWR 2 /* in clocks */
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#define SDRAM_CASL 2.5 /* CASL in clocks */
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#define SDRAM_TRCD 2 /* in clocks */
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#define SDRAM_TRP 2 /* in clocks */
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#define SDRAM_TRFC 7 /* in clocks */
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#define SDRAM_TREFI 7800 /* in ns */
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#define EXT_SRAM_ADDRESS (0xC0000000)
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#define FLASH_ADDRESS (0x00000000)
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#define SDRAM_ADDRESS (0x40000000)
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#define NAND_FLASH_ADDRESS (0xD0000000)
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int sys_clk_khz = 0;
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int sys_clk_mhz = 0;
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void wtm_init(void);
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void scm_init(void);
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void gpio_init(void);
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void fbcs_init(void);
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void sdramc_init(void);
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int clock_pll (int fsys, int flags);
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int clock_limp (int);
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int clock_exit_limp (void);
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int get_sys_clock (void);
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asmlinkage void __init sysinit(void)
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{
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sys_clk_khz = clock_pll(0, 0);
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sys_clk_mhz = sys_clk_khz/1000;
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wtm_init();
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scm_init();
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gpio_init();
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fbcs_init();
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sdramc_init();
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}
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void wtm_init(void)
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{
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/* Disable watchdog timer */
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MCF_WTM_WCR = 0;
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}
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#define MCF_SCM_BCR_GBW (0x00000100)
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#define MCF_SCM_BCR_GBR (0x00000200)
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void scm_init(void)
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{
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/* All masters are trusted */
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MCF_SCM_MPR = 0x77777777;
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/* Allow supervisor/user, read/write, and trusted/untrusted
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access to all slaves */
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MCF_SCM_PACRA = 0;
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MCF_SCM_PACRB = 0;
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MCF_SCM_PACRC = 0;
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MCF_SCM_PACRD = 0;
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MCF_SCM_PACRE = 0;
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MCF_SCM_PACRF = 0;
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/* Enable bursts */
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MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
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}
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void fbcs_init(void)
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{
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MCF_GPIO_PAR_CS = 0x0000003E;
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/* Latch chip select */
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MCF_FBCS1_CSAR = 0x10080000;
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MCF_FBCS1_CSCR = 0x002A3780;
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MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
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/* Initialize latch to drive signals to inactive states */
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*((u16 *)(0x10080000)) = 0xFFFF;
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/* External SRAM */
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MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
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MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
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| MCF_FBCS_CSCR_AA
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| MCF_FBCS_CSCR_SBM
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| MCF_FBCS_CSCR_WS(1));
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MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
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| MCF_FBCS_CSMR_V);
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/* Boot Flash connected to FBCS0 */
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MCF_FBCS0_CSAR = FLASH_ADDRESS;
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MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
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| MCF_FBCS_CSCR_BEM
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| MCF_FBCS_CSCR_AA
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| MCF_FBCS_CSCR_SBM
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| MCF_FBCS_CSCR_WS(7));
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MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
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| MCF_FBCS_CSMR_V);
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}
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void sdramc_init(void)
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{
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/*
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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*/
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if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
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/* SDRAM chip select initialization */
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/* Initialize SDRAM chip select */
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MCF_SDRAMC_SDCS0 = (0
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| MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
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| MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
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/*
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* Basic configuration and initialization
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*/
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MCF_SDRAMC_SDCFG1 = (0
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| MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
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| MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
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| MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
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| MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
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| MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
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| MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
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| MCF_SDRAMC_SDCFG1_WTLAT(3));
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MCF_SDRAMC_SDCFG2 = (0
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| MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
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| MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
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| MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
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| MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
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/*
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* Precharge and enable write to SDMR
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*/
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MCF_SDRAMC_SDCR = (0
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| MCF_SDRAMC_SDCR_MODE_EN
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| MCF_SDRAMC_SDCR_CKE
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| MCF_SDRAMC_SDCR_DDR
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| MCF_SDRAMC_SDCR_MUX(1)
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| MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
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| MCF_SDRAMC_SDCR_PS_16
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| MCF_SDRAMC_SDCR_IPALL);
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/*
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* Write extended mode register
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*/
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MCF_SDRAMC_SDMR = (0
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| MCF_SDRAMC_SDMR_BNKAD_LEMR
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| MCF_SDRAMC_SDMR_AD(0x0)
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| MCF_SDRAMC_SDMR_CMD);
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/*
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* Write mode register and reset DLL
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*/
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MCF_SDRAMC_SDMR = (0
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| MCF_SDRAMC_SDMR_BNKAD_LMR
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| MCF_SDRAMC_SDMR_AD(0x163)
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| MCF_SDRAMC_SDMR_CMD);
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/*
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* Execute a PALL command
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*/
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MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
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/*
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* Perform two REF cycles
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*/
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MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
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MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
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/*
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* Write mode register and clear reset DLL
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*/
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MCF_SDRAMC_SDMR = (0
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| MCF_SDRAMC_SDMR_BNKAD_LMR
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| MCF_SDRAMC_SDMR_AD(0x063)
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| MCF_SDRAMC_SDMR_CMD);
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/*
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* Enable auto refresh and lock SDMR
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*/
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MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
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MCF_SDRAMC_SDCR |= (0
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| MCF_SDRAMC_SDCR_REF
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| MCF_SDRAMC_SDCR_DQS_OE(0xC));
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}
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}
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void gpio_init(void)
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{
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/* Enable UART0 pins */
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MCF_GPIO_PAR_UART = ( 0
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| MCF_GPIO_PAR_UART_PAR_URXD0
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| MCF_GPIO_PAR_UART_PAR_UTXD0);
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/* Initialize TIN3 as a GPIO output to enable the write
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half of the latch */
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MCF_GPIO_PAR_TIMER = 0x00;
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MCF_GPIO_PDDR_TIMER = 0x08;
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MCF_GPIO_PCLRR_TIMER = 0x0;
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}
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int clock_pll(int fsys, int flags)
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{
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int fref, temp, fout, mfd;
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u32 i;
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fref = FREF;
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if (fsys == 0) {
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/* Return current PLL output */
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mfd = MCF_PLL_PFDR;
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return (fref * mfd / (BUSDIV * 4));
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}
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/* Check bounds of requested system clock */
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if (fsys > MAX_FSYS)
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fsys = MAX_FSYS;
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if (fsys < MIN_FSYS)
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fsys = MIN_FSYS;
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/* Multiplying by 100 when calculating the temp value,
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and then dividing by 100 to calculate the mfd allows
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for exact values without needing to include floating
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point libraries. */
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temp = 100 * fsys / fref;
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mfd = 4 * BUSDIV * temp / 100;
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/* Determine the output frequency for selected values */
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fout = (fref * mfd / (BUSDIV * 4));
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/*
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* Check to see if the SDRAM has already been initialized.
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* If it has then the SDRAM needs to be put into self refresh
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* mode before reprogramming the PLL.
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*/
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if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
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/* Put SDRAM into self refresh mode */
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MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
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/*
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* Initialize the PLL to generate the new system clock frequency.
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* The device must be put into LIMP mode to reprogram the PLL.
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*/
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/* Enter LIMP mode */
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clock_limp(DEFAULT_LPD);
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/* Reprogram PLL for desired fsys */
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MCF_PLL_PODR = (0
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| MCF_PLL_PODR_CPUDIV(BUSDIV/3)
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| MCF_PLL_PODR_BUSDIV(BUSDIV));
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MCF_PLL_PFDR = mfd;
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/* Exit LIMP mode */
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clock_exit_limp();
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/*
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* Return the SDRAM to normal operation if it is in use.
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*/
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if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
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/* Exit self refresh mode */
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MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
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/* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
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MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
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/* wait for DQS logic to relock */
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for (i = 0; i < 0x200; i++)
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;
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return fout;
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}
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int clock_limp(int div)
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{
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u32 temp;
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/* Check bounds of divider */
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if (div < MIN_LPD)
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div = MIN_LPD;
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if (div > MAX_LPD)
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div = MAX_LPD;
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/* Save of the current value of the SSIDIV so we don't
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overwrite the value*/
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temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
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/* Apply the divider to the system clock */
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MCF_CCM_CDR = ( 0
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| MCF_CCM_CDR_LPDIV(div)
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| MCF_CCM_CDR_SSIDIV(temp));
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MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
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return (FREF/(3*(1 << div)));
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}
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int clock_exit_limp(void)
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{
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int fout;
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/* Exit LIMP mode */
|
||||
MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
|
||||
|
||||
/* Wait for PLL to lock */
|
||||
while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
|
||||
;
|
||||
|
||||
fout = get_sys_clock();
|
||||
|
||||
return fout;
|
||||
}
|
||||
|
||||
int get_sys_clock(void)
|
||||
{
|
||||
int divider;
|
||||
|
||||
/* Test to see if device is in LIMP mode */
|
||||
if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
|
||||
divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
|
||||
return (FREF/(2 << divider));
|
||||
}
|
||||
else
|
||||
return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user