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[PATCH] m32r: framebuffer device support

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This patch is for supporting Epson s1d13xxx framebuffer device for m32r.  #
Sorry, a little bigger.

The Epson s1d13806 is already supported by 2.6.12 kernel, and its driver is
placed as drivers/video/s1d13xxxfb.c.

For the m32r, a header file include/asm-m32r/s1d13806.h was prepared for
several m32r target platforms.  It was originally generated by an Epson
tool S1D13806CFG.EXE, and modified manually for the m32r platforms.

Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Hirokazu Takata 2005-07-07 17:59:32 -07:00 committed by Linus Torvalds
parent e34ac862ee
commit 316240f66a
12 changed files with 1716 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
arch/m32r/kernel/setup_m32700ut.c
View File

@ -3,7 +3,7 @@
*
* Setup routines for Renesas M32700UT Board
*
* Copyright (c) 2002 Hiroyuki Kondo, Hirokazu Takata,
* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
* Hitoshi Yamamoto, Takeo Takahashi
*
* This file is subject to the terms and conditions of the GNU General
@ -435,7 +435,7 @@ void __init init_IRQ(void)
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
enable_m32700ut_irq(M32R_IRQ_INT2);
//#if defined(CONFIG_VIDEO_M32R_AR)
#if defined(CONFIG_VIDEO_M32R_AR)
/*
* INT3# is used for AR
*/
@ -445,9 +445,11 @@ void __init init_IRQ(void)
irq_desc[M32R_IRQ_INT3].depth = 1;
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_m32700ut_irq(M32R_IRQ_INT3);
//#endif /* CONFIG_VIDEO_M32R_AR */
#endif /* CONFIG_VIDEO_M32R_AR */
}
#if defined(CONFIG_SMC91X)
#define LAN_IOSTART 0x300
#define LAN_IOEND 0x320
static struct resource smc91x_resources[] = {
@ -469,10 +471,55 @@ static struct platform_device smc91x_device = {
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
#endif
#if defined(CONFIG_FB_S1D13XXX)
#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
.initregs = s1d13xxxfb_initregs,
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
.platform_init_video = NULL,
#ifdef CONFIG_PM
.platform_suspend_video = NULL,
.platform_resume_video = NULL,
#endif
};
static struct resource s1d13xxxfb_resources[] = {
[0] = {
.start = 0x10600000UL,
.end = 0x1073FFFFUL,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x10400000UL,
.end = 0x104001FFUL,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device s1d13xxxfb_device = {
.name = S1D_DEVICENAME,
.id = 0,
.dev = {
.platform_data = &s1d13xxxfb_data,
},
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
.resource = s1d13xxxfb_resources,
};
#endif
static int __init platform_init(void)
{
#if defined(CONFIG_SMC91X)
platform_device_register(&smc91x_device);
#endif
#if defined(CONFIG_FB_S1D13XXX)
platform_device_register(&s1d13xxxfb_device);
#endif
return 0;
}
arch_initcall(platform_init);

49
arch/m32r/kernel/setup_mappi.c
View File

@ -3,7 +3,7 @@
*
* Setup routines for Renesas MAPPI Board
*
* Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
* Hitoshi Yamamoto
*/
@ -11,6 +11,7 @@
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/system.h>
#include <asm/m32r.h>
@ -158,3 +159,49 @@ void __init init_IRQ(void)
disable_mappi_irq(M32R_IRQ_INT2);
#endif /* CONFIG_M32RPCC */
}
#if defined(CONFIG_FB_S1D13XXX)
#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
.initregs = s1d13xxxfb_initregs,
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
.platform_init_video = NULL,
#ifdef CONFIG_PM
.platform_suspend_video = NULL,
.platform_resume_video = NULL,
#endif
};
static struct resource s1d13xxxfb_resources[] = {
[0] = {
.start = 0x10200000UL,
.end = 0x1033FFFFUL,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x10000000UL,
.end = 0x100001FFUL,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device s1d13xxxfb_device = {
.name = S1D_DEVICENAME,
.id = 0,
.dev = {
.platform_data = &s1d13xxxfb_data,
},
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
.resource = s1d13xxxfb_resources,
};
static int __init platform_init(void)
{
platform_device_register(&s1d13xxxfb_device);
return 0;
}
arch_initcall(platform_init);
#endif

2
arch/m32r/kernel/setup_mappi2.c
View File

@ -3,7 +3,7 @@
*
* Setup routines for Renesas MAPPI-II(M3A-ZA36) Board
*
* Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
* Hitoshi Yamamoto, Mamoru Sakugawa
*/

48
arch/m32r/kernel/setup_mappi3.c
View File

@ -178,6 +178,8 @@ void __init init_IRQ(void)
#endif /* CONFIG_M32R_CFC */
}
#if defined(CONFIG_SMC91X)
#define LAN_IOSTART 0x300
#define LAN_IOEND 0x320
static struct resource smc91x_resources[] = {
@ -200,9 +202,55 @@ static struct platform_device smc91x_device = {
.resource = smc91x_resources,
};
#endif
#if defined(CONFIG_FB_S1D13XXX)
#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
.initregs = s1d13xxxfb_initregs,
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
.platform_init_video = NULL,
#ifdef CONFIG_PM
.platform_suspend_video = NULL,
.platform_resume_video = NULL,
#endif
};
static struct resource s1d13xxxfb_resources[] = {
[0] = {
.start = 0x1d600000UL,
.end = 0x1d73FFFFUL,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x1d400000UL,
.end = 0x1d4001FFUL,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device s1d13xxxfb_device = {
.name = S1D_DEVICENAME,
.id = 0,
.dev = {
.platform_data = &s1d13xxxfb_data,
},
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
.resource = s1d13xxxfb_resources,
};
#endif
static int __init platform_init(void)
{
#if defined(CONFIG_SMC91X)
platform_device_register(&smc91x_device);
#endif
#if defined(CONFIG_FB_S1D13XXX)
platform_device_register(&s1d13xxxfb_device);
#endif
return 0;
}
arch_initcall(platform_init);

3
arch/m32r/kernel/setup_oaks32r.c
View File

@ -3,7 +3,7 @@
*
* Setup routines for OAKS32R Board
*
* Copyright (c) 2002-2004 Hiroyuki Kondo, Hirokazu Takata,
* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
* Hitoshi Yamamoto, Mamoru Sakugawa
*/
@ -139,5 +139,4 @@ void __init init_IRQ(void)
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_oaks32r_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_SERIAL_M32R_SIO */
}

53
arch/m32r/kernel/setup_opsput.c
View File

@ -3,7 +3,7 @@
*
* Setup routines for Renesas OPSPUT Board
*
* Copyright (c) 2002-2004
* Copyright (c) 2002-2005
* Hiroyuki Kondo, Hirokazu Takata,
* Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
*
@ -439,7 +439,7 @@ void __init init_IRQ(void)
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
enable_opsput_irq(M32R_IRQ_INT2);
//#if defined(CONFIG_VIDEO_M32R_AR)
#if defined(CONFIG_VIDEO_M32R_AR)
/*
* INT3# is used for AR
*/
@ -449,9 +449,11 @@ void __init init_IRQ(void)
irq_desc[M32R_IRQ_INT3].depth = 1;
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_opsput_irq(M32R_IRQ_INT3);
//#endif /* CONFIG_VIDEO_M32R_AR */
#endif /* CONFIG_VIDEO_M32R_AR */
}
#if defined(CONFIG_SMC91X)
#define LAN_IOSTART 0x300
#define LAN_IOEND 0x320
static struct resource smc91x_resources[] = {
@ -473,10 +475,55 @@ static struct platform_device smc91x_device = {
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
#endif
#if defined(CONFIG_FB_S1D13XXX)
#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
.initregs = s1d13xxxfb_initregs,
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
.platform_init_video = NULL,
#ifdef CONFIG_PM
.platform_suspend_video = NULL,
.platform_resume_video = NULL,
#endif
};
static struct resource s1d13xxxfb_resources[] = {
[0] = {
.start = 0x10600000UL,
.end = 0x1073FFFFUL,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x10400000UL,
.end = 0x104001FFUL,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device s1d13xxxfb_device = {
.name = S1D_DEVICENAME,
.id = 0,
.dev = {
.platform_data = &s1d13xxxfb_data,
},
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
.resource = s1d13xxxfb_resources,
};
#endif
static int __init platform_init(void)
{
#if defined(CONFIG_SMC91X)
platform_device_register(&smc91x_device);
#endif
#if defined(CONFIG_FB_S1D13XXX)
platform_device_register(&s1d13xxxfb_device);
#endif
return 0;
}
arch_initcall(platform_init);

5
drivers/video/logo/Kconfig
View File

@ -63,5 +63,10 @@ config LOGO_SUPERH_CLUT224
depends on LOGO && SUPERH
default y
config LOGO_M32R_CLUT224
bool "224-color M32R Linux logo"
depends on LOGO && M32R
default y
endmenu

1
drivers/video/logo/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_LOGO_SUN_CLUT224) += logo_sun_clut224.o
obj-$(CONFIG_LOGO_SUPERH_MONO) += logo_superh_mono.o
obj-$(CONFIG_LOGO_SUPERH_VGA16) += logo_superh_vga16.o
obj-$(CONFIG_LOGO_SUPERH_CLUT224) += logo_superh_clut224.o
obj-$(CONFIG_LOGO_M32R_CLUT224) += logo_m32r_clut224.o
# How to generate logo's

5
drivers/video/logo/logo.c
View File

@ -33,6 +33,7 @@ extern const struct linux_logo logo_sun_clut224;
extern const struct linux_logo logo_superh_mono;
extern const struct linux_logo logo_superh_vga16;
extern const struct linux_logo logo_superh_clut224;
extern const struct linux_logo logo_m32r_clut224;
const struct linux_logo *fb_find_logo(int depth)
@ -96,6 +97,10 @@ const struct linux_logo *fb_find_logo(int depth)
#ifdef CONFIG_LOGO_SUPERH_CLUT224
/* SuperH Linux logo */
logo = &logo_superh_clut224;
#endif
#ifdef CONFIG_LOGO_M32R_CLUT224
/* M32R Linux logo */
logo = &logo_m32r_clut224;
#endif
}
return logo;

1292
drivers/video/logo/logo_m32r_clut224.ppm Normal file
View File

File diff suppressed because it is too large Load Diff

10
drivers/video/s1d13xxxfb.c
View File

@ -67,12 +67,18 @@ static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix = {
static inline u8
s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno)
{
#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
#endif
return readb(par->regs + regno);
}
static inline void
s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value)
{
#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
#endif
writeb(value, par->regs + regno);
}
@ -259,7 +265,11 @@ s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
regno, pseudo_val);
#if defined(CONFIG_PLAT_MAPPI)
((u32 *)info->pseudo_palette)[regno] = cpu_to_le16(pseudo_val);
#else
((u32 *)info->pseudo_palette)[regno] = pseudo_val;
#endif
break;
case FB_VISUAL_PSEUDOCOLOR:

199
include/asm-m32r/s1d13806.h Normal file
View File

@ -0,0 +1,199 @@
//----------------------------------------------------------------------------
//
// File generated by S1D13806CFG.EXE
//
// Copyright (c) 2000,2001 Epson Research and Development, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Panel: (active) 640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)
#define SWIVEL_VIEW 0 /* 0:none, 1:90 not completed */
static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
{0x0001,0x00}, // Miscellaneous Register
{0x01FC,0x00}, // Display Mode Register
#if defined(CONFIG_PLAT_MAPPI)
{0x0004,0x00}, // General IO Pins Configuration Register 0
{0x0005,0x00}, // General IO Pins Configuration Register 1
{0x0008,0x00}, // General IO Pins Control Register 0
{0x0009,0x00}, // General IO Pins Control Register 1
{0x0010,0x00}, // Memory Clock Configuration Register
{0x0014,0x00}, // LCD Pixel Clock Configuration Register
{0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
{0x001C,0x00}, // MediaPlug Clock Configuration Register
/*
* .. 10MHz: 0x00
* .. 30MHz: 0x01
* 30MHz ..: 0x02
*/
{0x001E,0x02}, // CPU To Memory Wait State Select Register
{0x0021,0x02}, // DRAM Refresh Rate Register
{0x002A,0x11}, // DRAM Timings Control Register 0
{0x002B,0x13}, // DRAM Timings Control Register 1
{0x0020,0x80}, // Memory Configuration Register
{0x0030,0x25}, // Panel Type Register
{0x0031,0x00}, // MOD Rate Register
{0x0032,0x4F}, // LCD Horizontal Display Width Register
{0x0034,0x12}, // LCD Horizontal Non-Display Period Register
{0x0035,0x01}, // TFT FPLINE Start Position Register
{0x0036,0x0B}, // TFT FPLINE Pulse Width Register
{0x0038,0xDF}, // LCD Vertical Display Height Register 0
{0x0039,0x01}, // LCD Vertical Display Height Register 1
{0x003A,0x2C}, // LCD Vertical Non-Display Period Register
{0x003B,0x0A}, // TFT FPFRAME Start Position Register
{0x003C,0x01}, // TFT FPFRAME Pulse Width Register
{0x0041,0x00}, // LCD Miscellaneous Register
{0x0042,0x00}, // LCD Display Start Address Register 0
{0x0043,0x00}, // LCD Display Start Address Register 1
{0x0044,0x00}, // LCD Display Start Address Register 2
#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
{0x0004,0x07}, // GPIO[0:7] direction
{0x0005,0x00}, // GPIO[8:12] direction
{0x0008,0x00}, // GPIO[0:7] data
{0x0009,0x00}, // GPIO[8:12] data
{0x0008,0x04}, // LCD panel Vcc on
{0x0008,0x05}, // LCD panel reset
{0x0010,0x01}, // Memory Clock Configuration Register
{0x0014,0x30}, // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
{0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
{0x001C,0x00}, // MediaPlug Clock Configuration Register(10MHz)
{0x001E,0x00}, // CPU To Memory Wait State Select Register
{0x0020,0x80}, // Memory Configuration Register
{0x0021,0x03}, // DRAM Refresh Rate Register
{0x002A,0x00}, // DRAM Timings Control Register 0
{0x002B,0x01}, // DRAM Timings Control Register 1
{0x0030,0x25}, // Panel Type Register
{0x0031,0x00}, // MOD Rate Register
{0x0032,0x1d}, // LCD Horizontal Display Width Register
{0x0034,0x05}, // LCD Horizontal Non-Display Period Register
{0x0035,0x01}, // TFT FPLINE Start Position Register
{0x0036,0x01}, // TFT FPLINE Pulse Width Register
{0x0038,0x3F}, // LCD Vertical Display Height Register 0
{0x0039,0x01}, // LCD Vertical Display Height Register 1
{0x003A,0x0b}, // LCD Vertical Non-Display Period Register
{0x003B,0x07}, // TFT FPFRAME Start Position Register
{0x003C,0x02}, // TFT FPFRAME Pulse Width Register
{0x0041,0x00}, // LCD Miscellaneous Register
#if (SWIVEL_VIEW == 0)
{0x0042,0x00}, // LCD Display Start Address Register 0
{0x0043,0x00}, // LCD Display Start Address Register 1
{0x0044,0x00}, // LCD Display Start Address Register 2
#elif (SWIVEL_VIEW == 1)
// 1024 - W(320) = 0x2C0
{0x0042,0xC0}, // LCD Display Start Address Register 0
{0x0043,0x02}, // LCD Display Start Address Register 1
{0x0044,0x00}, // LCD Display Start Address Register 2
// 1024
{0x0046,0x00}, // LCD Memory Address Offset Register 0
{0x0047,0x02}, // LCD Memory Address Offset Register 1
#else
#error unsupported SWIVEL_VIEW mode
#endif
#else
#error no platform configuration
#endif /* CONFIG_PLAT_XXX */
{0x0048,0x00}, // LCD Pixel Panning Register
{0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
{0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
{0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
{0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
{0x0053,0x01}, // CRT/TV HRTC Start Position Register
{0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
{0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
{0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
{0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
{0x0059,0x09}, // CRT/TV VRTC Start Position Register
{0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
{0x005B,0x10}, // TV Output Control Register
{0x0062,0x00}, // CRT/TV Display Start Address Register 0
{0x0063,0x00}, // CRT/TV Display Start Address Register 1
{0x0064,0x00}, // CRT/TV Display Start Address Register 2
{0x0068,0x00}, // CRT/TV Pixel Panning Register
{0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
{0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
{0x0070,0x00}, // LCD Ink/Cursor Control Register
{0x0071,0x01}, // LCD Ink/Cursor Start Address Register
{0x0072,0x00}, // LCD Cursor X Position Register 0
{0x0073,0x00}, // LCD Cursor X Position Register 1
{0x0074,0x00}, // LCD Cursor Y Position Register 0
{0x0075,0x00}, // LCD Cursor Y Position Register 1
{0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
{0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
{0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
{0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
{0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
{0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
{0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
{0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
{0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
{0x0082,0x00}, // CRT/TV Cursor X Position Register 0
{0x0083,0x00}, // CRT/TV Cursor X Position Register 1
{0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
{0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
{0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
{0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
{0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
{0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
{0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
{0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
{0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
{0x0100,0x00}, // BitBlt Control Register 0
{0x0101,0x00}, // BitBlt Control Register 1
{0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
{0x0103,0x00}, // BitBlt Operation Register
{0x0104,0x00}, // BitBlt Source Start Address Register 0
{0x0105,0x00}, // BitBlt Source Start Address Register 1
{0x0106,0x00}, // BitBlt Source Start Address Register 2
{0x0108,0x00}, // BitBlt Destination Start Address Register 0
{0x0109,0x00}, // BitBlt Destination Start Address Register 1
{0x010A,0x00}, // BitBlt Destination Start Address Register 2
{0x010C,0x00}, // BitBlt Memory Address Offset Register 0
{0x010D,0x00}, // BitBlt Memory Address Offset Register 1
{0x0110,0x00}, // BitBlt Width Register 0
{0x0111,0x00}, // BitBlt Width Register 1
{0x0112,0x00}, // BitBlt Height Register 0
{0x0113,0x00}, // BitBlt Height Register 1
{0x0114,0x00}, // BitBlt Background Color Register 0
{0x0115,0x00}, // BitBlt Background Color Register 1
{0x0118,0x00}, // BitBlt Foreground Color Register 0
{0x0119,0x00}, // BitBlt Foreground Color Register 1
{0x01E0,0x00}, // Look-Up Table Mode Register
{0x01E2,0x00}, // Look-Up Table Address Register
{0x01F0,0x10}, // Power Save Configuration Register
{0x01F1,0x00}, // Power Save Status Register
{0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
#if (SWIVEL_VIEW == 0)
{0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
#elif (SWIVEL_VIEW == 1)
{0x01FC,0x41}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
#else
#error unsupported SWIVEL_VIEW mode
#endif /* SWIVEL_VIEW */
#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
{0x0008,0x07}, // LCD panel Vdd & Vg on
#endif
{0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
#if defined(CONFIG_PLAT_MAPPI)
{0x0046,0x80}, // LCD Memory Address Offset Register 0
{0x0047,0x02}, // LCD Memory Address Offset Register 1
#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
{0x0046,0xf0}, // LCD Memory Address Offset Register 0
{0x0047,0x00}, // LCD Memory Address Offset Register 1
#endif
{0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
{0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 // takeo
{0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
};