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powerpc/smp: Merge Power9 topology with Power topology

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A new sched_domain_topology_level was added just for Power9. However the
same can be achieved by merging powerpc_topology with power9_topology
and makes the code more simpler especially when adding a new sched
domain.

Signed-off-by: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200810071834.92514-3-srikar@linux.vnet.ibm.com
This commit is contained in:
Srikar Dronamraju
2020-08-10 12:48:26 +05:30
committed by Michael Ellerman
parent d0fd24bbd2
commit 2ef0ca54d9
1 changed files with 3 additions and 22 deletions
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25
arch/powerpc/kernel/smp.c
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@@ -1314,7 +1314,7 @@ int setup_profiling_timer(unsigned int multiplier)
} }
#ifdef CONFIG_SCHED_SMT #ifdef CONFIG_SCHED_SMT
/* cpumask of CPUs with asymetric SMT dependancy */ /* cpumask of CPUs with asymmetric SMT dependency */
static int powerpc_smt_flags(void) static int powerpc_smt_flags(void)
{ {
int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES;
@@ -1327,14 +1327,6 @@ static int powerpc_smt_flags(void)
} }
#endif #endif
static struct sched_domain_topology_level powerpc_topology[] = {
#ifdef CONFIG_SCHED_SMT
{ cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
#endif
{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
{ NULL, },
};
/* /*
* P9 has a slightly odd architecture where pairs of cores share an L2 cache. * P9 has a slightly odd architecture where pairs of cores share an L2 cache.
* This topology makes it *much* cheaper to migrate tasks between adjacent cores * This topology makes it *much* cheaper to migrate tasks between adjacent cores
@@ -1362,7 +1354,7 @@ static const struct cpumask *smallcore_smt_mask(int cpu)
} }
#endif #endif
static struct sched_domain_topology_level power9_topology[] = { static struct sched_domain_topology_level powerpc_topology[] = {
#ifdef CONFIG_SCHED_SMT #ifdef CONFIG_SCHED_SMT
{ cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
#endif #endif
@@ -1387,21 +1379,10 @@ void __init smp_cpus_done(unsigned int max_cpus)
#ifdef CONFIG_SCHED_SMT #ifdef CONFIG_SCHED_SMT
if (has_big_cores) { if (has_big_cores) {
pr_info("Big cores detected but using small core scheduling\n"); pr_info("Big cores detected but using small core scheduling\n");
power9_topology[0].mask = smallcore_smt_mask;
powerpc_topology[0].mask = smallcore_smt_mask; powerpc_topology[0].mask = smallcore_smt_mask;
} }
#endif #endif
/* set_sched_topology(powerpc_topology);
* If any CPU detects that it's sharing a cache with another CPU then
* use the deeper topology that is aware of this sharing.
*/
if (shared_caches) {
pr_info("Using shared cache scheduler topology\n");
set_sched_topology(power9_topology);
} else {
pr_info("Using standard scheduler topology\n");
set_sched_topology(powerpc_topology);
}
} }
#ifdef CONFIG_HOTPLUG_CPU #ifdef CONFIG_HOTPLUG_CPU