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OMAP2/3: hwmod: L3 and L4 CORE/PER/WKUP hwmods don't have IDLEST

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Since these hwmods do not have IDLEST, set the HWMOD_NO_IDLEST flag,
otherwise _enable() will fail due to failing _wait_target_ready().

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Kevin Hilman 2010-07-26 16:34:28 -06:00 committed by Paul Walmsley
parent 6405616754
commit 2eb1875d2b
3 changed files with 20 additions and 10 deletions
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9
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -65,7 +65,8 @@ static struct omap_hwmod omap2420_l3_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2420_l3_masters), .masters_cnt = ARRAY_SIZE(omap2420_l3_masters),
.slaves = omap2420_l3_slaves, .slaves = omap2420_l3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l3_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_l3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
}; };
static struct omap_hwmod omap2420_l4_wkup_hwmod; static struct omap_hwmod omap2420_l4_wkup_hwmod;
@ -95,7 +96,8 @@ static struct omap_hwmod omap2420_l4_core_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
.slaves = omap2420_l4_core_slaves, .slaves = omap2420_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
}; };
/* Slave interfaces on the L4_WKUP interconnect */ /* Slave interfaces on the L4_WKUP interconnect */
@ -115,7 +117,8 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
.slaves = omap2420_l4_wkup_slaves, .slaves = omap2420_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
}; };
/* Master interfaces on the MPU device */ /* Master interfaces on the MPU device */

9
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -65,7 +65,8 @@ static struct omap_hwmod omap2430_l3_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2430_l3_masters), .masters_cnt = ARRAY_SIZE(omap2430_l3_masters),
.slaves = omap2430_l3_slaves, .slaves = omap2430_l3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l3_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_l3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
}; };
static struct omap_hwmod omap2430_l4_wkup_hwmod; static struct omap_hwmod omap2430_l4_wkup_hwmod;
@ -97,7 +98,8 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
.slaves = omap2430_l4_core_slaves, .slaves = omap2430_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
}; };
/* Slave interfaces on the L4_WKUP interconnect */ /* Slave interfaces on the L4_WKUP interconnect */
@ -117,7 +119,8 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
.slaves = omap2430_l4_wkup_slaves, .slaves = omap2430_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
}; };
/* Master interfaces on the MPU device */ /* Master interfaces on the MPU device */

12
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -76,7 +76,8 @@ static struct omap_hwmod omap3xxx_l3_hwmod = {
.masters_cnt = ARRAY_SIZE(omap3xxx_l3_masters), .masters_cnt = ARRAY_SIZE(omap3xxx_l3_masters),
.slaves = omap3xxx_l3_slaves, .slaves = omap3xxx_l3_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_l3_slaves), .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
}; };
static struct omap_hwmod omap3xxx_l4_wkup_hwmod; static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
@ -106,7 +107,8 @@ static struct omap_hwmod omap3xxx_l4_core_hwmod = {
.masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
.slaves = omap3xxx_l4_core_slaves, .slaves = omap3xxx_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
}; };
/* Slave interfaces on the L4_PER interconnect */ /* Slave interfaces on the L4_PER interconnect */
@ -126,7 +128,8 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = {
.masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
.slaves = omap3xxx_l4_per_slaves, .slaves = omap3xxx_l4_per_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
}; };
/* Slave interfaces on the L4_WKUP interconnect */ /* Slave interfaces on the L4_WKUP interconnect */
@ -146,7 +149,8 @@ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
.masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
.slaves = omap3xxx_l4_wkup_slaves, .slaves = omap3xxx_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
}; };
/* Master interfaces on the MPU device */ /* Master interfaces on the MPU device */