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[IA64] SGI Altix : fix pcibr_dmamap_ate32() bug

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On a SGI Altix TIOCP based PCI bus we need to include the ATE_PIO attribute
bit if we're mapping a 32bit MSI address.

Signed-off-by: Mike Habeck <habeck@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Mike Habeck 2007-04-06 12:04:39 -05:00 committed by Tony Luck
parent 8a3a78d149
commit 2e0d232bff
2 changed files with 9 additions and 4 deletions
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8
arch/ia64/sn/pci/pcibr/pcibr_dma.c
View File

@ -96,10 +96,14 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
} }
/* /*
* If we're mapping for MSI, set the MSI bit in the ATE * If we're mapping for MSI, set the MSI bit in the ATE. If it's a
* TIOCP based pci bus, we also need to set the PIO bit in the ATE.
*/ */
if (dma_flags & SN_DMA_MSI) if (dma_flags & SN_DMA_MSI) {
ate |= PCI32_ATE_MSI; ate |= PCI32_ATE_MSI;
if (IS_TIOCP_SOFT(pcibus_info))
ate |= PCI32_ATE_PIO;
}
ate_write(pcibus_info, ate_index, ate_count, ate); ate_write(pcibus_info, ate_index, ate_count, ate);

5
include/asm-ia64/sn/pcibr_provider.h
View File

@ -21,6 +21,7 @@
#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \ #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
asic == PCIIO_ASIC_TYPE_TIOCP) asic == PCIIO_ASIC_TYPE_TIOCP)
#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) #define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
/* /*
@ -53,8 +54,8 @@
* Bridge PMU Address Transaltion Entry Attibutes * Bridge PMU Address Transaltion Entry Attibutes
*/ */
#define PCI32_ATE_V (0x1 << 0) #define PCI32_ATE_V (0x1 << 0)
#define PCI32_ATE_CO (0x1 << 1) #define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
#define PCI32_ATE_PREC (0x1 << 2) #define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
#define PCI32_ATE_MSI (0x1 << 2) #define PCI32_ATE_MSI (0x1 << 2)
#define PCI32_ATE_PREF (0x1 << 3) #define PCI32_ATE_PREF (0x1 << 3)
#define PCI32_ATE_BAR (0x1 << 4) #define PCI32_ATE_BAR (0x1 << 4)