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ASoC: rt5645: multiple JD mode support

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There are 3 JD modes in RT5645. This patch configure register
values according to platform data.

Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Bard Liao 2014-11-18 16:50:18 +08:00 committed by Mark Brown
parent 471f208af9
commit 2d4e2d0205
3 changed files with 42 additions and 1 deletions
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1
include/sound/rt5645.h
View File

@ -26,6 +26,7 @@ struct rt5645_platform_data {
/* true if codec's jd function is used */ /* true if codec's jd function is used */
bool en_jd_func; bool en_jd_func;
unsigned int jd_mode;
}; };
#endif #endif

35
sound/soc/codecs/rt5645.c
View File

@ -2239,7 +2239,8 @@ static int rt5645_jack_detect(struct snd_soc_codec *codec)
snd_soc_dapm_disable_pin(&codec->dapm, "micbias1"); snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
snd_soc_dapm_disable_pin(&codec->dapm, "micbias2"); snd_soc_dapm_disable_pin(&codec->dapm, "micbias2");
snd_soc_dapm_disable_pin(&codec->dapm, "LDO2"); if (rt5645->pdata.jd_mode == 0)
snd_soc_dapm_disable_pin(&codec->dapm, "LDO2");
snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power"); snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
snd_soc_dapm_sync(&codec->dapm); snd_soc_dapm_sync(&codec->dapm);
} }
@ -2543,6 +2544,38 @@ static int rt5645_i2c_probe(struct i2c_client *i2c,
RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
} }
if (rt5645->pdata.jd_mode) {
regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
switch (rt5645->pdata.jd_mode) {
case 1:
regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
RT5645_JD1_MODE_MASK,
RT5645_JD1_MODE_0);
break;
case 2:
regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
RT5645_JD1_MODE_MASK,
RT5645_JD1_MODE_1);
break;
case 3:
regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
RT5645_JD1_MODE_MASK,
RT5645_JD1_MODE_2);
break;
default:
break;
}
}
if (rt5645->i2c->irq) { if (rt5645->i2c->irq) {
ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING

7
sound/soc/codecs/rt5645.h
View File

@ -594,6 +594,7 @@
#define RT5645_M_DAC1_HM_SFT 14 #define RT5645_M_DAC1_HM_SFT 14
#define RT5645_M_HPVOL_HM (0x1 << 13) #define RT5645_M_HPVOL_HM (0x1 << 13)
#define RT5645_M_HPVOL_HM_SFT 13 #define RT5645_M_HPVOL_HM_SFT 13
#define RT5645_IRQ_PSV_MODE (0x1 << 12)
/* SPK Left Mixer Control (0x46) */ /* SPK Left Mixer Control (0x46) */
#define RT5645_G_RM_L_SM_L_MASK (0x3 << 14) #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
@ -1350,6 +1351,10 @@
#define RT5645_PWR_CLK25M_PU (0x1 << 4) #define RT5645_PWR_CLK25M_PU (0x1 << 4)
#define RT5645_IRQ_CLK_MCLK (0x0 << 3) #define RT5645_IRQ_CLK_MCLK (0x0 << 3)
#define RT5645_IRQ_CLK_INT (0x1 << 3) #define RT5645_IRQ_CLK_INT (0x1 << 3)
#define RT5645_JD1_MODE_MASK (0x3 << 0)
#define RT5645_JD1_MODE_0 (0x0 << 0)
#define RT5645_JD1_MODE_1 (0x1 << 0)
#define RT5645_JD1_MODE_2 (0x2 << 0)
/* VAD Control 4 (0x9d) */ /* VAD Control 4 (0x9d) */
#define RT5645_VAD_SEL_MASK (0x3 << 8) #define RT5645_VAD_SEL_MASK (0x3 << 8)
@ -1638,6 +1643,7 @@
#define RT5645_OT_P_SFT 10 #define RT5645_OT_P_SFT 10
#define RT5645_OT_P_NOR (0x0 << 10) #define RT5645_OT_P_NOR (0x0 << 10)
#define RT5645_OT_P_INV (0x1 << 10) #define RT5645_OT_P_INV (0x1 << 10)
#define RT5645_IRQ_JD_1_1_EN (0x1 << 9)
/* IRQ Control 2 (0xbe) */ /* IRQ Control 2 (0xbe) */
#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15) #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
@ -2120,6 +2126,7 @@ enum {
#define RT5645_RXDP2_SEL_SFT (3) #define RT5645_RXDP2_SEL_SFT (3)
/* General Control3 (0xfc) */ /* General Control3 (0xfc) */
#define RT5645_JD_PSV_MODE (0x1 << 12)
#define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11) #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)
#define RT5645_MICINDET_MANU (0x1 << 7) #define RT5645_MICINDET_MANU (0x1 << 7)