forked from Minki/linux
Merge branch 'lantiq-GSWIP-fixes'
Martin Blumenstingl says:
====================
lantiq: GSWIP: two more fixes
after my last patch got accepted and is now in net as commit
3e6fdeb28f ("net: dsa: lantiq_gswip: Let GSWIP automatically set
the xMII clock") [0] some more people from the OpenWrt community
(many thanks to everyone involved) helped test the GSWIP driver: [1]
It turns out that the previous fix does not work for all boards.
There's no regression, but it doesn't fix as many problems as I
thought. This is why two more fixes are needed:
- the first one solves many (four known but probably there are
a few extra hidden ones) reported bugs with the GSWIP where no
traffic would flow. Not all circumstances are fully understood
but testing shows that switching away from PHY auto polling
solves all of them
- while investigating the different problems which are addressed
by the first patch some small issues with the existing code were
found. These are addressed by the second patch
Changes since v1 at [0]:
- Don't configure the link parameters in gswip_phylink_mac_config
(as we're using the "modern" way in gswip_phylink_mac_link_up).
Thanks to Andrew for the hint with the phylink documentation.
- Clarify that GSWIP_MII_CFG_RMII_CLK is ignored by the hardware in
the description of the second patch as suggested by Hauke
- Don't set GSWIP_MII_CFG_RGMII_IBS in the second patch as we don't
have any hardware available for testing this. The patch
description now also reflects this.
- Added Andrew's Reviewed-by to the first patch (thank you!)
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
2d1b50abf8
@ -93,8 +93,12 @@
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/* GSWIP MII Registers */
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#define GSWIP_MII_CFGp(p) (0x2 * (p))
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#define GSWIP_MII_CFG_RESET BIT(15)
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#define GSWIP_MII_CFG_EN BIT(14)
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#define GSWIP_MII_CFG_ISOLATE BIT(13)
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#define GSWIP_MII_CFG_LDCLKDIS BIT(12)
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#define GSWIP_MII_CFG_RGMII_IBS BIT(8)
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#define GSWIP_MII_CFG_RMII_CLK BIT(7)
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#define GSWIP_MII_CFG_MODE_MIIP 0x0
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#define GSWIP_MII_CFG_MODE_MIIM 0x1
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#define GSWIP_MII_CFG_MODE_RMIIP 0x2
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@ -190,6 +194,23 @@
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#define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
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#define GSWIP_MAC_FLEN 0x8C5
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#define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
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#define GSWIP_MAC_CTRL_0_PADEN BIT(8)
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#define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
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#define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
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#define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
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#define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
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#define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
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#define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
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#define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
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#define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
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#define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
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#define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
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#define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
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#define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
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#define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
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#define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
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#define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
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#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
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#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
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@ -653,16 +674,13 @@ static int gswip_port_enable(struct dsa_switch *ds, int port,
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GSWIP_SDMA_PCTRLp(port));
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if (!dsa_is_cpu_port(ds, port)) {
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u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO |
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GSWIP_MDIO_PHY_SPEED_AUTO |
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GSWIP_MDIO_PHY_FDUP_AUTO |
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GSWIP_MDIO_PHY_FCONTX_AUTO |
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GSWIP_MDIO_PHY_FCONRX_AUTO |
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(phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK);
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u32 mdio_phy = 0;
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gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port));
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/* Activate MDIO auto polling */
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gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0);
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if (phydev)
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mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
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GSWIP_MDIO_PHYp(port));
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}
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return 0;
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@ -675,14 +693,6 @@ static void gswip_port_disable(struct dsa_switch *ds, int port)
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if (!dsa_is_user_port(ds, port))
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return;
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if (!dsa_is_cpu_port(ds, port)) {
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN,
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GSWIP_MDIO_PHY_LINK_MASK,
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GSWIP_MDIO_PHYp(port));
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/* Deactivate MDIO auto polling */
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gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0);
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}
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gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
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GSWIP_FDMA_PCTRLp(port));
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gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
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@ -794,19 +804,32 @@ static int gswip_setup(struct dsa_switch *ds)
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gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
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gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
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/* disable PHY auto polling */
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/* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
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* interoperability problem with this auto polling mechanism because
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* their status registers think that the link is in a different state
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* than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
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* as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
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* auto polling state machine consider the link being negotiated with
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* 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
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* to the switch port being completely dead (RX and TX are both not
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* working).
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* Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
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* GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
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* it would work fine for a few minutes to hours and then stop, on
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* other device it would no traffic could be sent or received at all.
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* Testing shows that when PHY auto polling is disabled these problems
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* go away.
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*/
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gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
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/* Configure the MDIO Clock 2.5 MHz */
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gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
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for (i = 0; i < priv->hw_info->max_ports; i++) {
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/* Disable the xMII link */
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gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i);
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/* Automatically select the xMII interface clock */
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gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK,
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GSWIP_MII_CFG_RATE_AUTO, i);
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}
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/* Disable the xMII interface and clear it's isolation bit */
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for (i = 0; i < priv->hw_info->max_ports; i++)
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gswip_mii_mask_cfg(priv,
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GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
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0, i);
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/* enable special tag insertion on cpu port */
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gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
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@ -1455,6 +1478,112 @@ unsupported:
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return;
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}
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static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
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{
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u32 mdio_phy;
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if (link)
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mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
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else
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mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,
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GSWIP_MDIO_PHYp(port));
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}
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static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
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phy_interface_t interface)
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{
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u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
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switch (speed) {
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case SPEED_10:
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mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
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if (interface == PHY_INTERFACE_MODE_RMII)
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mii_cfg = GSWIP_MII_CFG_RATE_M50;
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else
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mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
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break;
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case SPEED_100:
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mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
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if (interface == PHY_INTERFACE_MODE_RMII)
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mii_cfg = GSWIP_MII_CFG_RATE_M50;
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else
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mii_cfg = GSWIP_MII_CFG_RATE_M25;
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
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break;
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case SPEED_1000:
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mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
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mii_cfg = GSWIP_MII_CFG_RATE_M125;
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
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break;
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}
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,
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GSWIP_MDIO_PHYp(port));
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gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
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gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,
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GSWIP_MAC_CTRL_0p(port));
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}
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static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
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{
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u32 mac_ctrl_0, mdio_phy;
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if (duplex == DUPLEX_FULL) {
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
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mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
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} else {
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
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mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
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}
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gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,
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GSWIP_MAC_CTRL_0p(port));
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,
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GSWIP_MDIO_PHYp(port));
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}
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static void gswip_port_set_pause(struct gswip_priv *priv, int port,
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bool tx_pause, bool rx_pause)
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{
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u32 mac_ctrl_0, mdio_phy;
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if (tx_pause && rx_pause) {
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
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mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
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GSWIP_MDIO_PHY_FCONRX_EN;
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} else if (tx_pause) {
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
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mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
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GSWIP_MDIO_PHY_FCONRX_DIS;
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} else if (rx_pause) {
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
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mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
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GSWIP_MDIO_PHY_FCONRX_EN;
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} else {
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mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
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mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
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GSWIP_MDIO_PHY_FCONRX_DIS;
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}
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gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,
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mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));
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gswip_mdio_mask(priv,
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GSWIP_MDIO_PHY_FCONTX_MASK |
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GSWIP_MDIO_PHY_FCONRX_MASK,
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mdio_phy, GSWIP_MDIO_PHYp(port));
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}
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static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
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unsigned int mode,
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const struct phylink_link_state *state)
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@ -1474,6 +1603,9 @@ static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
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break;
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case PHY_INTERFACE_MODE_RMII:
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miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
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/* Configure the RMII clock as output: */
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miicfg |= GSWIP_MII_CFG_RMII_CLK;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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@ -1486,7 +1618,11 @@ static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
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"Unsupported interface: %d\n", state->interface);
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return;
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}
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gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port);
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gswip_mii_mask_cfg(priv,
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GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
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GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
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miicfg, port);
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switch (state->interface) {
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case PHY_INTERFACE_MODE_RGMII_ID:
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@ -1511,6 +1647,9 @@ static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
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struct gswip_priv *priv = ds->priv;
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gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
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if (!dsa_is_cpu_port(ds, port))
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gswip_port_set_link(priv, port, false);
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}
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static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
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@ -1522,6 +1661,13 @@ static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
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{
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struct gswip_priv *priv = ds->priv;
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if (!dsa_is_cpu_port(ds, port)) {
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gswip_port_set_link(priv, port, true);
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gswip_port_set_speed(priv, port, speed, interface);
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gswip_port_set_duplex(priv, port, duplex);
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gswip_port_set_pause(priv, port, tx_pause, rx_pause);
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}
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gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
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}
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