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drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading

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The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-08-07 17:01:47 +08:00 committed by Alex Deucher
parent 266d81d9ee
commit 2c5b8080d8
1 changed files with 0 additions and 6 deletions
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6
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
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@ -1640,12 +1640,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
data->uvd_power_gated = true;
data->vce_power_gated = true;
if (data->smu_features[GNLD_DPM_UVD].enabled)
data->uvd_power_gated = false;
if (data->smu_features[GNLD_DPM_VCE].enabled)
data->vce_power_gated = false;
}
static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)