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drm/nve0/ibus: handle PIBUS interrupts to prevent storm

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-08-22 23:55:42 -04:00
parent 757833cc9f
commit 2c1a425e7d
6 changed files with 162 additions and 0 deletions
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1
drivers/gpu/drm/nouveau/Makefile
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@ -73,6 +73,7 @@ nouveau-y += core/subdev/gpio/nvd0.o
nouveau-y += core/subdev/i2c/base.o
nouveau-y += core/subdev/i2c/aux.o
nouveau-y += core/subdev/i2c/bit.o
nouveau-y += core/subdev/ibus/nve0.o
nouveau-y += core/subdev/instmem/base.o
nouveau-y += core/subdev/instmem/nv04.o
nouveau-y += core/subdev/instmem/nv40.o

1
drivers/gpu/drm/nouveau/core/include/core/device.h
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@ -17,6 +17,7 @@ enum nv_subdev_type {
NVDEV_SUBDEV_TIMER,
NVDEV_SUBDEV_FB,
NVDEV_SUBDEV_LTCG,
NVDEV_SUBDEV_IBUS,
NVDEV_SUBDEV_INSTMEM,
NVDEV_SUBDEV_VM,
NVDEV_SUBDEV_BAR,

33
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h Normal file
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@ -0,0 +1,33 @@
#ifndef __NOUVEAU_IBUS_H__
#define __NOUVEAU_IBUS_H__
#include <core/subdev.h>
#include <core/device.h>
struct nouveau_ibus {
struct nouveau_subdev base;
};
static inline struct nouveau_ibus *
nouveau_ibus(void *obj)
{
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_IBUS];
}
#define nouveau_ibus_create(p,e,o,d) \
nouveau_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \
sizeof(**d), (void **)d)
#define nouveau_ibus_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_ibus_init(p) \
nouveau_subdev_init(&(p)->base)
#define nouveau_ibus_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s))
#define _nouveau_ibus_dtor _nouveau_subdev_dtor
#define _nouveau_ibus_init _nouveau_subdev_init
#define _nouveau_ibus_fini _nouveau_subdev_fini
extern struct nouveau_oclass nve0_ibus_oclass;
#endif

3
drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
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@ -33,6 +33,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltcg.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
@ -60,6 +61,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
@ -83,6 +85,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;

123
drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c Normal file
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@ -0,0 +1,123 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/ibus.h>
struct nve0_ibus_priv {
struct nouveau_ibus base;
};
static void
nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800));
u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0800));
nv_error(priv, "HUB%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
nv_mask(priv, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000);
}
static void
nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800));
u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0800));
nv_error(priv, "ROP%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
nv_mask(priv, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000);
}
static void
nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800));
u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0800));
nv_error(priv, "GPC%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
nv_mask(priv, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000);
}
static void
nve0_ibus_intr(struct nouveau_subdev *subdev)
{
struct nve0_ibus_priv *priv = (void *)subdev;
u32 intr0 = nv_rd32(priv, 0x120058);
u32 intr1 = nv_rd32(priv, 0x12005c);
u32 hubnr = nv_rd32(priv, 0x120070);
u32 ropnr = nv_rd32(priv, 0x120074);
u32 gpcnr = nv_rd32(priv, 0x120078);
u32 i;
for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
u32 stat = 0x00000100 << i;
if (intr0 & stat) {
nve0_ibus_intr_hub(priv, i);
intr0 &= ~stat;
}
}
for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
u32 stat = 0x00010000 << i;
if (intr0 & stat) {
nve0_ibus_intr_rop(priv, i);
intr0 &= ~stat;
}
}
for (i = 0; intr1 && i < gpcnr; i++) {
u32 stat = 0x00000001 << i;
if (intr1 & stat) {
nve0_ibus_intr_gpc(priv, i);
intr1 &= ~stat;
}
}
}
static int
nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nve0_ibus_priv *priv;
int ret;
ret = nouveau_ibus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->intr = nve0_ibus_intr;
return 0;
}
struct nouveau_oclass
nve0_ibus_oclass = {
.handle = NV_SUBDEV(IBUS, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_ibus_ctor,
.dtor = _nouveau_ibus_dtor,
.init = _nouveau_ibus_init,
.fini = _nouveau_ibus_fini,
},
};

1
drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
View File

@ -40,6 +40,7 @@ nvc0_mc_intr[] = {
{ 0x00200000, NVDEV_SUBDEV_GPIO },
{ 0x02000000, NVDEV_SUBDEV_LTCG },
{ 0x04000000, NVDEV_ENGINE_DISP },
{ 0x40000000, NVDEV_SUBDEV_IBUS },
{ 0x80000000, NVDEV_ENGINE_SW },
{},
};