ARM: exynos: Set MCPM as mandatory for Exynos542x/5800 SoCs
Support for Exynos5420/5422/5800 SoCs requires MCPM to properly boot all CPU cores on all currectly supported platforms: Peach Pit (Exynos5420), Odroid XU3/XU3lite/XU4/HC1 (Exynos5422) and Peach Pi (Exynos5800). Without it some CPU cores fail to come online. Remove then the ability to disable MCPM and make it mandatory when Exynos542x/5800 support is enabled. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -9,7 +9,6 @@ CONFIG_MODULE_UNLOAD=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_ARCH_EXYNOS=y
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CONFIG_ARCH_EXYNOS=y
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CONFIG_ARCH_EXYNOS3=y
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CONFIG_ARCH_EXYNOS3=y
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CONFIG_EXYNOS5420_MCPM=y
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CONFIG_SMP=y
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CONFIG_SMP=y
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CONFIG_BIG_LITTLE=y
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CONFIG_BIG_LITTLE=y
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CONFIG_NR_CPUS=8
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CONFIG_NR_CPUS=8
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@ -33,7 +33,6 @@ CONFIG_MACH_BERLIN_BG2CD=y
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CONFIG_MACH_BERLIN_BG2Q=y
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CONFIG_MACH_BERLIN_BG2Q=y
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CONFIG_ARCH_DIGICOLOR=y
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CONFIG_ARCH_DIGICOLOR=y
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CONFIG_ARCH_EXYNOS=y
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CONFIG_ARCH_EXYNOS=y
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CONFIG_EXYNOS5420_MCPM=y
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CONFIG_ARCH_HIGHBANK=y
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CONFIG_ARCH_HIGHBANK=y
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CONFIG_ARCH_HISI=y
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CONFIG_ARCH_HISI=y
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CONFIG_ARCH_HI3xxx=y
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CONFIG_ARCH_HI3xxx=y
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@ -106,21 +106,15 @@ config SOC_EXYNOS5420
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bool "SAMSUNG EXYNOS5420"
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bool "SAMSUNG EXYNOS5420"
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default y
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default y
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depends on ARCH_EXYNOS5
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depends on ARCH_EXYNOS5
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select MCPM if SMP
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select ARM_CCI400_PORT_CTRL
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select ARM_CPU_SUSPEND
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config SOC_EXYNOS5800
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config SOC_EXYNOS5800
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bool "SAMSUNG EXYNOS5800"
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bool "SAMSUNG EXYNOS5800"
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default y
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default y
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depends on SOC_EXYNOS5420
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depends on SOC_EXYNOS5420
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config EXYNOS5420_MCPM
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bool "Exynos5420 Multi-Cluster PM support"
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depends on MCPM && SOC_EXYNOS5420
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select ARM_CCI400_PORT_CTRL
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select ARM_CPU_SUSPEND
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help
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This is needed to provide CPU and cluster power management
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on Exynos5420 implementing big.LITTLE.
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config EXYNOS_CPU_SUSPEND
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config EXYNOS_CPU_SUSPEND
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bool
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bool
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select ARM_CPU_SUSPEND
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select ARM_CPU_SUSPEND
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@ -18,5 +18,5 @@ plus_sec := $(call as-instr,.arch_extension sec,+sec)
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AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
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AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
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AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec)
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AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec)
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obj-$(CONFIG_EXYNOS5420_MCPM) += mcpm-exynos.o
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obj-$(CONFIG_MCPM) += mcpm-exynos.o
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CFLAGS_mcpm-exynos.o += -march=armv7-a
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CFLAGS_mcpm-exynos.o += -march=armv7-a
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@ -268,7 +268,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
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if (IS_ENABLED(CONFIG_MCPM)) {
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mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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mcpm_cpu_suspend();
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mcpm_cpu_suspend();
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}
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}
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@ -351,7 +351,7 @@ static void exynos5420_pm_prepare(void)
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exynos_pm_enter_sleep_mode();
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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/* ensure at least INFORM0 has the resume address */
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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if (IS_ENABLED(CONFIG_MCPM))
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pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
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pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
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tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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@ -455,7 +455,7 @@ static void exynos5420_prepare_pm_resume(void)
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mpidr = read_cpuid_mpidr();
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mpidr = read_cpuid_mpidr();
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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if (IS_ENABLED(CONFIG_MCPM))
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WARN_ON(mcpm_cpu_powered_up());
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WARN_ON(mcpm_cpu_powered_up());
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if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
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if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
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