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MIPS: Alchemy: Fix db1200 PSC clock enablement

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Enable PSC0 (I2C/SPI) clock and leave PSC1 (Audio) alone.  This patch
restores functionality to both Audio and I2C/SPI.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7544/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss 2014-08-18 17:10:32 +02:00 committed by Ralf Baechle
parent 2727cab25a
commit 293076f300
1 changed files with 1 additions and 5 deletions
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6
arch/mips/alchemy/devboards/db1200.c
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@ -847,6 +847,7 @@ int __init db1200_dev_setup(void)
pr_warn("DB1200: cant get I2C close to 50MHz\n"); pr_warn("DB1200: cant get I2C close to 50MHz\n");
else else
clk_set_rate(c, pfc); clk_set_rate(c, pfc);
clk_prepare_enable(c);
clk_put(c); clk_put(c);
} }
@ -922,11 +923,6 @@ int __init db1200_dev_setup(void)
} }
/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
c = clk_get(NULL, "psc1_intclk");
if (!IS_ERR(c)) {
clk_prepare_enable(c);
clk_put(c);
}
__raw_writel(PSC_SEL_CLK_SERCLK, __raw_writel(PSC_SEL_CLK_SERCLK,
(void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
wmb(); wmb();