x86/pci: Enable pci root res read out for 32bit too
Should be good for 32bit too. -v3: cast res->start -v4: according to Linus, to use %pR instead of cast Signed-off-by: Yinghai Lu <yinghai@kernel.org> LKML-Reference: <1265793639-15071-9-git-send-email-yinghai@kernel.org> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -14,8 +14,7 @@ obj-$(CONFIG_X86_VISWS) += visws.o
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obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
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obj-y += common.o early.o
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obj-y += amd_bus.o
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obj-$(CONFIG_X86_64) += bus_numa.o
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obj-y += amd_bus.o bus_numa.o
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ifeq ($(CONFIG_PCI_DEBUG),y)
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EXTRA_CFLAGS += -DDEBUG
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@ -6,9 +6,7 @@
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#include <asm/pci_x86.h>
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#ifdef CONFIG_X86_64
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#include <asm/pci-direct.h>
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#endif
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#include "bus_numa.h"
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@ -17,8 +15,6 @@
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* also get peer root bus resource for io,mmio
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*/
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#ifdef CONFIG_X86_64
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struct pci_hostbridge_probe {
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u32 bus;
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u32 slot;
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@ -339,24 +335,14 @@ static int __init early_fill_mp_bus_info(void)
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info->bus_min, info->bus_max, info->node, info->link);
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for (j = 0; j < res_num; j++) {
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res = &info->res[j];
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printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
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busnum, j,
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(res->flags & IORESOURCE_IO)?"io port":"mmio",
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res->start, res->end);
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printk(KERN_DEBUG "bus: %02x index %x %pR\n",
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busnum, j, res);
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}
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}
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return 0;
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}
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#else /* !CONFIG_X86_64 */
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static int __init early_fill_mp_bus_info(void) { return 0; }
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#endif /* !CONFIG_X86_64 */
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/* common 32/64 bit code */
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#define ENABLE_CF8_EXT_CFG (1ULL << 46)
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static void enable_pci_io_ecs(void *unused)
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@ -1,5 +1,5 @@
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#ifdef CONFIG_X86_64
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#ifndef __BUS_NUMA_H
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#define __BUS_NUMA_H
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/*
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* sub bus (transparent) will use entres from 3 to store extra from
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* root, so need to make sure we have enough slot there, Should we
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@ -257,10 +257,6 @@ void __init pcibios_resource_survey(void)
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*/
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fs_initcall(pcibios_assign_resources);
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void __weak x86_pci_root_bus_res_quirks(struct pci_bus *b)
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{
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}
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/*
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* If we set up a device for bus mastering, we need to check the latency
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* timer as certain crappy BIOSes forget to set it properly.
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