forked from Minki/linux
[8139too]: tab-align enums and structs; remove dead code
* (main change) tab-align hardware register value enums, and hw struct * MMIO_FLUSH_AUDIT_COMPLETE has been defined to 1 for a while. Remove the code activated when it is set to zero. Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jeff Garzik
David S. Miller
parent
6cc92cddb1
commit
28006c65a7
@ -291,198 +291,197 @@ static struct {
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/* Symbolic offsets to registers. */
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enum RTL8139_registers {
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MAC0 = 0, /* Ethernet hardware address. */
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MAR0 = 8, /* Multicast filter. */
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TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
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TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
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RxBuf = 0x30,
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ChipCmd = 0x37,
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RxBufPtr = 0x38,
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RxBufAddr = 0x3A,
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IntrMask = 0x3C,
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IntrStatus = 0x3E,
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TxConfig = 0x40,
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RxConfig = 0x44,
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Timer = 0x48, /* A general-purpose counter. */
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RxMissed = 0x4C, /* 24 bits valid, write clears. */
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Cfg9346 = 0x50,
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Config0 = 0x51,
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Config1 = 0x52,
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FlashReg = 0x54,
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MediaStatus = 0x58,
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Config3 = 0x59,
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Config4 = 0x5A, /* absent on RTL-8139A */
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HltClk = 0x5B,
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MultiIntr = 0x5C,
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TxSummary = 0x60,
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BasicModeCtrl = 0x62,
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BasicModeStatus = 0x64,
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NWayAdvert = 0x66,
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NWayLPAR = 0x68,
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NWayExpansion = 0x6A,
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MAC0 = 0, /* Ethernet hardware address. */
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MAR0 = 8, /* Multicast filter. */
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TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
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TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
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RxBuf = 0x30,
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ChipCmd = 0x37,
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RxBufPtr = 0x38,
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RxBufAddr = 0x3A,
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IntrMask = 0x3C,
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IntrStatus = 0x3E,
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TxConfig = 0x40,
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RxConfig = 0x44,
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Timer = 0x48, /* A general-purpose counter. */
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RxMissed = 0x4C, /* 24 bits valid, write clears. */
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Cfg9346 = 0x50,
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Config0 = 0x51,
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Config1 = 0x52,
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FlashReg = 0x54,
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MediaStatus = 0x58,
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Config3 = 0x59,
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Config4 = 0x5A, /* absent on RTL-8139A */
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HltClk = 0x5B,
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MultiIntr = 0x5C,
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TxSummary = 0x60,
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BasicModeCtrl = 0x62,
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BasicModeStatus = 0x64,
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NWayAdvert = 0x66,
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NWayLPAR = 0x68,
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NWayExpansion = 0x6A,
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/* Undocumented registers, but required for proper operation. */
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FIFOTMS = 0x70, /* FIFO Control and test. */
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CSCR = 0x74, /* Chip Status and Configuration Register. */
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PARA78 = 0x78,
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PARA7c = 0x7c, /* Magic transceiver parameter register. */
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Config5 = 0xD8, /* absent on RTL-8139A */
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FIFOTMS = 0x70, /* FIFO Control and test. */
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CSCR = 0x74, /* Chip Status and Configuration Register. */
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PARA78 = 0x78,
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PARA7c = 0x7c, /* Magic transceiver parameter register. */
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Config5 = 0xD8, /* absent on RTL-8139A */
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};
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enum ClearBitMasks {
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MultiIntrClear = 0xF000,
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ChipCmdClear = 0xE2,
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Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
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MultiIntrClear = 0xF000,
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ChipCmdClear = 0xE2,
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Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
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};
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enum ChipCmdBits {
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CmdReset = 0x10,
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CmdRxEnb = 0x08,
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CmdTxEnb = 0x04,
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RxBufEmpty = 0x01,
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CmdReset = 0x10,
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CmdRxEnb = 0x08,
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CmdTxEnb = 0x04,
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RxBufEmpty = 0x01,
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};
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/* Interrupt register bits, using my own meaningful names. */
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enum IntrStatusBits {
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PCIErr = 0x8000,
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PCSTimeout = 0x4000,
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RxFIFOOver = 0x40,
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RxUnderrun = 0x20,
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RxOverflow = 0x10,
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TxErr = 0x08,
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TxOK = 0x04,
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RxErr = 0x02,
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RxOK = 0x01,
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PCIErr = 0x8000,
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PCSTimeout = 0x4000,
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RxFIFOOver = 0x40,
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RxUnderrun = 0x20,
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RxOverflow = 0x10,
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TxErr = 0x08,
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TxOK = 0x04,
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RxErr = 0x02,
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RxOK = 0x01,
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RxAckBits = RxFIFOOver | RxOverflow | RxOK,
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RxAckBits = RxFIFOOver | RxOverflow | RxOK,
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};
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enum TxStatusBits {
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TxHostOwns = 0x2000,
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TxUnderrun = 0x4000,
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TxStatOK = 0x8000,
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TxOutOfWindow = 0x20000000,
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TxAborted = 0x40000000,
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TxCarrierLost = 0x80000000,
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TxHostOwns = 0x2000,
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TxUnderrun = 0x4000,
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TxStatOK = 0x8000,
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TxOutOfWindow = 0x20000000,
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TxAborted = 0x40000000,
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TxCarrierLost = 0x80000000,
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};
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enum RxStatusBits {
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RxMulticast = 0x8000,
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RxPhysical = 0x4000,
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RxBroadcast = 0x2000,
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RxBadSymbol = 0x0020,
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RxRunt = 0x0010,
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RxTooLong = 0x0008,
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RxCRCErr = 0x0004,
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RxBadAlign = 0x0002,
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RxStatusOK = 0x0001,
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RxMulticast = 0x8000,
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RxPhysical = 0x4000,
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RxBroadcast = 0x2000,
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RxBadSymbol = 0x0020,
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RxRunt = 0x0010,
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RxTooLong = 0x0008,
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RxCRCErr = 0x0004,
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RxBadAlign = 0x0002,
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RxStatusOK = 0x0001,
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};
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/* Bits in RxConfig. */
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enum rx_mode_bits {
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0x08,
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AcceptMulticast = 0x04,
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AcceptMyPhys = 0x02,
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AcceptAllPhys = 0x01,
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0x08,
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AcceptMulticast = 0x04,
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AcceptMyPhys = 0x02,
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AcceptAllPhys = 0x01,
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};
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/* Bits in TxConfig. */
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enum tx_config_bits {
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/* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
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TxIFGShift = 24,
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TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
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TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
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TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
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TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
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TxIFGShift = 24,
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TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
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TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
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TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
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TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
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TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
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TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
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TxClearAbt = (1 << 0), /* Clear abort (WO) */
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TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
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TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
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TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
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TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
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TxClearAbt = (1 << 0), /* Clear abort (WO) */
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TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
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TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
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TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
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TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
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};
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/* Bits in Config1 */
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enum Config1Bits {
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Cfg1_PM_Enable = 0x01,
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Cfg1_VPD_Enable = 0x02,
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Cfg1_PIO = 0x04,
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Cfg1_MMIO = 0x08,
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LWAKE = 0x10, /* not on 8139, 8139A */
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Cfg1_PM_Enable = 0x01,
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Cfg1_VPD_Enable = 0x02,
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Cfg1_PIO = 0x04,
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Cfg1_MMIO = 0x08,
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LWAKE = 0x10, /* not on 8139, 8139A */
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Cfg1_Driver_Load = 0x20,
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Cfg1_LED0 = 0x40,
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Cfg1_LED1 = 0x80,
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SLEEP = (1 << 1), /* only on 8139, 8139A */
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PWRDN = (1 << 0), /* only on 8139, 8139A */
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Cfg1_LED0 = 0x40,
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Cfg1_LED1 = 0x80,
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SLEEP = (1 << 1), /* only on 8139, 8139A */
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PWRDN = (1 << 0), /* only on 8139, 8139A */
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};
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/* Bits in Config3 */
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enum Config3Bits {
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Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
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Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
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Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
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Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
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Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
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Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
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Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
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Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
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Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
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Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
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Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
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Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
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Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
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Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
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Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
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Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
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};
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/* Bits in Config4 */
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enum Config4Bits {
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LWPTN = (1 << 2), /* not on 8139, 8139A */
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LWPTN = (1 << 2), /* not on 8139, 8139A */
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};
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/* Bits in Config5 */
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enum Config5Bits {
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Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
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Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
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Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
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Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
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Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
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Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
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Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
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Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
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Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
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Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
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Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
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Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
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Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
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Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
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};
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enum RxConfigBits {
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/* rx fifo threshold */
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RxCfgFIFOShift = 13,
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RxCfgFIFONone = (7 << RxCfgFIFOShift),
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RxCfgFIFOShift = 13,
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RxCfgFIFONone = (7 << RxCfgFIFOShift),
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/* Max DMA burst */
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RxCfgDMAShift = 8,
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RxCfgDMAShift = 8,
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RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
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/* rx ring buffer length */
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RxCfgRcv8K = 0,
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RxCfgRcv16K = (1 << 11),
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RxCfgRcv32K = (1 << 12),
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RxCfgRcv64K = (1 << 11) | (1 << 12),
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RxCfgRcv8K = 0,
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RxCfgRcv16K = (1 << 11),
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RxCfgRcv32K = (1 << 12),
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RxCfgRcv64K = (1 << 11) | (1 << 12),
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/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
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RxNoWrap = (1 << 7),
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RxNoWrap = (1 << 7),
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};
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/* Twister tuning parameters from RealTek.
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Completely undocumented, but required to tune bad links on some boards. */
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enum CSCRBits {
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CSCR_LinkOKBit = 0x0400,
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CSCR_LinkChangeBit = 0x0800,
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CSCR_LinkStatusBits = 0x0f000,
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CSCR_LinkDownOffCmd = 0x003c0,
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CSCR_LinkDownCmd = 0x0f3c0,
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CSCR_LinkOKBit = 0x0400,
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CSCR_LinkChangeBit = 0x0800,
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CSCR_LinkStatusBits = 0x0f000,
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CSCR_LinkDownOffCmd = 0x003c0,
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CSCR_LinkDownCmd = 0x0f3c0,
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};
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enum Cfg9346Bits {
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Cfg9346_Lock = 0x00,
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Cfg9346_Unlock = 0xC0,
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Cfg9346_Lock = 0x00,
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Cfg9346_Unlock = 0xC0,
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};
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typedef enum {
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CH_8139 = 0,
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CH_8139 = 0,
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CH_8139_K,
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CH_8139A,
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CH_8139A_G,
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@ -495,8 +494,8 @@ typedef enum {
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} chip_t;
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enum chip_flags {
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HasHltClk = (1 << 0),
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HasLWake = (1 << 1),
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HasHltClk = (1 << 0),
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HasLWake = (1 << 1),
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};
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#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
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@ -569,38 +568,46 @@ struct rtl_extra_stats {
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};
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struct rtl8139_private {
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void __iomem *mmio_addr;
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int drv_flags;
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struct pci_dev *pci_dev;
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u32 msg_enable;
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struct napi_struct napi;
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struct net_device *dev;
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struct net_device_stats stats;
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unsigned char *rx_ring;
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unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
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unsigned int tx_flag;
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unsigned long cur_tx;
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unsigned long dirty_tx;
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unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
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unsigned char *tx_bufs; /* Tx bounce buffer region. */
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dma_addr_t rx_ring_dma;
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dma_addr_t tx_bufs_dma;
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signed char phys[4]; /* MII device addresses. */
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char twistie, twist_row, twist_col; /* Twister tune state. */
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unsigned int watchdog_fired : 1;
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unsigned int default_port : 4; /* Last dev->if_port value. */
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unsigned int have_thread : 1;
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spinlock_t lock;
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spinlock_t rx_lock;
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chip_t chipset;
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u32 rx_config;
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struct rtl_extra_stats xstats;
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void __iomem *mmio_addr;
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int drv_flags;
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struct pci_dev *pci_dev;
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u32 msg_enable;
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struct napi_struct napi;
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struct net_device *dev;
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struct net_device_stats stats;
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struct delayed_work thread;
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unsigned char *rx_ring;
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unsigned int cur_rx; /* RX buf index of next pkt */
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dma_addr_t rx_ring_dma;
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struct mii_if_info mii;
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unsigned int regs_len;
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unsigned long fifo_copy_timeout;
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unsigned int tx_flag;
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unsigned long cur_tx;
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unsigned long dirty_tx;
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unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
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unsigned char *tx_bufs; /* Tx bounce buffer region. */
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dma_addr_t tx_bufs_dma;
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signed char phys[4]; /* MII device addresses. */
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/* Twister tune state. */
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char twistie, twist_row, twist_col;
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unsigned int watchdog_fired : 1;
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unsigned int default_port : 4; /* Last dev->if_port value. */
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unsigned int have_thread : 1;
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spinlock_t lock;
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spinlock_t rx_lock;
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chip_t chipset;
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u32 rx_config;
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struct rtl_extra_stats xstats;
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struct delayed_work thread;
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struct mii_if_info mii;
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unsigned int regs_len;
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unsigned long fifo_copy_timeout;
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};
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MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
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@ -648,24 +655,11 @@ static const struct ethtool_ops rtl8139_ethtool_ops;
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#define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
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#define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
|
||||
|
||||
|
||||
#define MMIO_FLUSH_AUDIT_COMPLETE 1
|
||||
#if MMIO_FLUSH_AUDIT_COMPLETE
|
||||
|
||||
/* write MMIO register */
|
||||
#define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
|
||||
#define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
|
||||
#define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
|
||||
|
||||
#else
|
||||
|
||||
/* write MMIO register, then flush */
|
||||
#define RTL_W8 RTL_W8_F
|
||||
#define RTL_W16 RTL_W16_F
|
||||
#define RTL_W32 RTL_W32_F
|
||||
|
||||
#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
|
||||
|
||||
/* read MMIO register */
|
||||
#define RTL_R8(reg) ioread8 (ioaddr + (reg))
|
||||
#define RTL_R16(reg) ioread16 (ioaddr + (reg))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user