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Merge branch 'cleanup/__iomem' into next/cleanup

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__iomem annotation cleanup branch from Arnd.

* cleanup/__iomem: (21 commits)
  net: seeq: use __iomem pointers for MMIO
  video: da8xx-fb: use __iomem pointers for MMIO
  scsi: eesox: use __iomem pointers for MMIO
  serial: ks8695: use __iomem pointers for MMIO
  input: rpcmouse: use __iomem pointers for MMIO
  ARM: samsung: use __iomem pointers for MMIO
  ARM: spear13xx: use __iomem pointers for MMIO
  ARM: sa1100: use __iomem pointers for MMIO
  ARM: prima2: use __iomem pointers for MMIO
  ARM: nomadik: use __iomem pointers for MMIO
  ARM: msm: use __iomem pointers for MMIO
  ARM: lpc32xx: use __iomem pointers for MMIO
  ARM: ks8695: use __iomem pointers for MMIO
  ARM: ixp4xx: use __iomem pointers for MMIO
  ARM: iop32x: use __iomem pointers for MMIO
  ARM: iop13xx: use __iomem pointers for MMIO
  ARM: integrator: use __iomem pointers for MMIO
  ARM: imx: use __iomem pointers for MMIO
  ARM: ebsa110: use __iomem pointers for MMIO
  ARM: at91: use __iomem pointers for MMIO
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2012-09-22 10:24:06 -07:00
commit 268aebe4d0
66 changed files with 399 additions and 395 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-at91/at91x40.c
View File

@ -47,7 +47,7 @@ static void at91x40_idle(void)
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
__raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
__raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
cpu_do_idle();
}

4
arch/arm/mach-at91/at91x40_time.c
View File

@ -29,10 +29,10 @@
#include <mach/at91_tc.h>
#define at91_tc_read(field) \
__raw_readl(AT91_TC + field)
__raw_readl(AT91_IO_P2V(AT91_TC) + field)
#define at91_tc_write(field, value) \
__raw_writel(value, AT91_TC + field);
__raw_writel(value, AT91_IO_P2V(AT91_TC) + field);
/*
* 3 counter/timer units present.

4
arch/arm/mach-at91/include/mach/hardware.h
View File

@ -67,13 +67,13 @@
* to 0xFEF78000 .. 0xFF000000. (544Kb)
*/
#define AT91_IO_PHYS_BASE 0xFFF78000
#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE)
#else
/*
* Identity mapping for the non MMU case.
*/
#define AT91_IO_PHYS_BASE AT91_BASE_SYS
#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE
#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE)
#endif
#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)

6
arch/arm/mach-at91/include/mach/uncompress.h
View File

@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
0,
};
static inline const u32* decomp_soc_detect(u32 dbgu_base)
static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
{
u32 cidr, socid;
@ -142,10 +142,10 @@ static inline void arch_decomp_setup(void)
int i = 0;
const u32* usarts;
usarts = decomp_soc_detect(AT91_BASE_DBGU0);
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
if (!usarts)
usarts = decomp_soc_detect(AT91_BASE_DBGU1);
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
if (!usarts) {
at91_uart = NULL;
return;

4
arch/arm/mach-at91/setup.c
View File

@ -73,7 +73,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
{
struct map_desc *desc = &sram_desc[bank];
desc->virtual = AT91_IO_VIRT_BASE - length;
desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
if (bank > 0)
desc->virtual -= sram_desc[bank - 1].length;
@ -88,7 +88,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
}
static struct map_desc at91_io_desc __initdata = {
.virtual = AT91_VA_BASE_SYS,
.virtual = (unsigned long)AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,

8
arch/arm/mach-ebsa110/core.c
View File

@ -74,22 +74,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = {
* sparse external-decode ISAIO space
*/
{ /* IRQ_STAT/IRQ_MCLR */
.virtual = IRQ_STAT,
.virtual = (unsigned long)IRQ_STAT,
.pfn = __phys_to_pfn(TRICK4_PHYS),
.length = TRICK4_SIZE,
.type = MT_DEVICE
}, { /* IRQ_MASK/IRQ_MSET */
.virtual = IRQ_MASK,
.virtual = (unsigned long)IRQ_MASK,
.pfn = __phys_to_pfn(TRICK3_PHYS),
.length = TRICK3_SIZE,
.type = MT_DEVICE
}, { /* SOFT_BASE */
.virtual = SOFT_BASE,
.virtual = (unsigned long)SOFT_BASE,
.pfn = __phys_to_pfn(TRICK1_PHYS),
.length = TRICK1_SIZE,
.type = MT_DEVICE
}, { /* PIT_BASE */
.virtual = PIT_BASE,
.virtual = (unsigned long)PIT_BASE,
.pfn = __phys_to_pfn(TRICK0_PHYS),
.length = TRICK0_SIZE,
.type = MT_DEVICE

12
arch/arm/mach-ebsa110/core.h
View File

@ -31,11 +31,11 @@
#define TRICK7_PHYS 0xf3c00000
/* Virtual addresses */
#define PIT_BASE 0xfc000000 /* trick 0 */
#define SOFT_BASE 0xfd000000 /* trick 1 */
#define IRQ_MASK 0xfe000000 /* trick 3 - read */
#define IRQ_MSET 0xfe000000 /* trick 3 - write */
#define IRQ_STAT 0xff000000 /* trick 4 - read */
#define IRQ_MCLR 0xff000000 /* trick 4 - write */
#define PIT_BASE IOMEM(0xfc000000) /* trick 0 */
#define SOFT_BASE IOMEM(0xfd000000) /* trick 1 */
#define IRQ_MASK IOMEM(0xfe000000) /* trick 3 - read */
#define IRQ_MSET IOMEM(0xfe000000) /* trick 3 - write */
#define IRQ_STAT IOMEM(0xff000000) /* trick 4 - read */
#define IRQ_MCLR IOMEM(0xff000000) /* trick 4 - write */
#endif

4
arch/arm/mach-imx/mach-kzm_arm11_01.c
View File

@ -258,13 +258,13 @@ static void __init kzm_board_init(void)
*/
static struct map_desc kzm_io_desc[] __initdata = {
{
.virtual = MX31_CS4_BASE_ADDR_VIRT,
.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
.length = MX31_CS4_SIZE,
.type = MT_DEVICE
},
{
.virtual = MX31_CS5_BASE_ADDR_VIRT,
.virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
.length = MX31_CS5_SIZE,
.type = MT_DEVICE

2
arch/arm/mach-imx/mach-mx31ads.c
View File

@ -540,7 +540,7 @@ static void __init mxc_init_audio(void)
*/
static struct map_desc mx31ads_io_desc[] __initdata = {
{
.virtual = MX31_CS4_BASE_ADDR_VIRT,
.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
.length = CS4_CS8900_MMIO_START,
.type = MT_DEVICE

2
arch/arm/mach-imx/mach-mx31lite.c
View File

@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = {
*/
static struct map_desc mx31lite_io_desc[] __initdata = {
{
.virtual = MX31_CS4_BASE_ADDR_VIRT,
.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
.length = MX31_CS4_SIZE,
.type = MT_DEVICE

4
arch/arm/mach-integrator/core.c
View File

@ -95,8 +95,8 @@ arch_initcall(integrator_init);
* UART0 7 6
* UART1 5 4
*/
#define SC_CTRLC IO_ADDRESS(INTEGRATOR_SC_CTRLC)
#define SC_CTRLS IO_ADDRESS(INTEGRATOR_SC_CTRLS)
#define SC_CTRLC __io_address(INTEGRATOR_SC_CTRLC)
#define SC_CTRLS __io_address(INTEGRATOR_SC_CTRLS)
static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
{

8
arch/arm/mach-integrator/cpu.c
View File

@ -25,10 +25,10 @@
static struct cpufreq_driver integrator_driver;
#define CM_ID IO_ADDRESS(INTEGRATOR_HDR_ID)
#define CM_OSC IO_ADDRESS(INTEGRATOR_HDR_OSC)
#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT)
#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
#define CM_ID __io_address(INTEGRATOR_HDR_ID)
#define CM_OSC __io_address(INTEGRATOR_HDR_OSC)
#define CM_STAT __io_address(INTEGRATOR_HDR_STAT)
#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK)
static const struct icst_params lclk_params = {
.ref = 24000000,

12
arch/arm/mach-integrator/integrator_ap.c
View File

@ -134,17 +134,17 @@ static struct map_desc ap_io_desc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE
}, {
.virtual = PCI_MEMORY_VADDR,
.virtual = (unsigned long)PCI_MEMORY_VADDR,
.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
.length = SZ_16M,
.type = MT_DEVICE
}, {
.virtual = PCI_CONFIG_VADDR,
.virtual = (unsigned long)PCI_CONFIG_VADDR,
.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
.length = SZ_16M,
.type = MT_DEVICE
}, {
.virtual = PCI_V3_VADDR,
.virtual = (unsigned long)PCI_V3_VADDR,
.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
.length = SZ_64K,
.type = MT_DEVICE
@ -314,9 +314,9 @@ static void __init ap_init(void)
/*
* Where is the timer (VA)?
*/
#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
static unsigned long timer_reload;

6
arch/arm/mach-integrator/integrator_cp.c
View File

@ -59,7 +59,7 @@
#define INTCP_ETH_SIZE 0x10
#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
#define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE)
#define INTCP_FLASHPROG 0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
@ -265,8 +265,8 @@ static struct platform_device *intcp_devs[] __initdata = {
*/
static unsigned int mmc_status(struct device *dev)
{
unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
unsigned int status = readl(__io_address(0xca000000 + 4));
writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));
return status & 8;
}

12
arch/arm/mach-integrator/pci_v3.c
View File

@ -181,7 +181,7 @@ static DEFINE_RAW_SPINLOCK(v3_lock);
#undef V3_LB_BASE_PREFETCH
#define V3_LB_BASE_PREFETCH 0
static unsigned long v3_open_config_window(struct pci_bus *bus,
static void __iomem *v3_open_config_window(struct pci_bus *bus,
unsigned int devfn, int offset)
{
unsigned int address, mapaddress, busnr;
@ -280,7 +280,7 @@ static void v3_close_config_window(void)
static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *val)
{
unsigned long addr;
void __iomem *addr;
unsigned long flags;
u32 v;
@ -311,7 +311,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
unsigned long addr;
void __iomem *addr;
unsigned long flags;
raw_spin_lock_irqsave(&v3_lock, flags);
@ -388,9 +388,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
* means I can't get additional information on the reason for the pm2fb
* problems. I suppose I'll just have to mind-meld with the machine. ;)
*/
#define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)
#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20)
#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24)
#define SC_PCI __io_address(INTEGRATOR_SC_PCIENABLE)
#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20)
#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24)
static int
v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)

20
arch/arm/mach-iop13xx/include/mach/iop13xx.h
View File

@ -126,18 +126,16 @@ extern unsigned long get_iop_tick_rate(void);
* IOP13XX chipset registers
*/
#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */
#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
(IOP13XX_PMMR_PHYS_MEM_BASE\
- IOP13XX_PMMR_VIRT_MEM_BASE))
#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
(IOP13XX_PMMR_PHYS_MEM_BASE\
- IOP13XX_PMMR_VIRT_MEM_BASE))
#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
+ IOP13XX_PMMR_PHYS_MEM_BASE)
#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
+ IOP13XX_PMMR_VIRT_MEM_BASE)
#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
@ -147,10 +145,10 @@ extern unsigned long get_iop_tick_rate(void);
#define IOP13XX_PMMR_SIZE 0x00080000
/*=================== Defines for Platform Devices =====================*/
#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)

14
arch/arm/mach-iop13xx/include/mach/memory.h
View File

@ -16,12 +16,12 @@
#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
static inline dma_addr_t __virt_to_lbus(unsigned long x)
static inline dma_addr_t __virt_to_lbus(void __iomem *x)
{
return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
}
static inline unsigned long __lbus_to_virt(dma_addr_t x)
static inline void __iomem *__lbus_to_virt(dma_addr_t x)
{
return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
}
@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
#define __arch_dma_to_virt(dev, addr) \
({ \
unsigned long __virt; \
void * __virt; \
dma_addr_t __dma = addr; \
if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \
__virt = __lbus_to_virt(__dma); \
else \
__virt = __phys_to_virt(__dma); \
(void *)__virt; \
__virt = (void *)__phys_to_virt(__dma); \
__virt; \
})
#define __arch_virt_to_dma(dev, addr) \
({ \
unsigned long __virt = (unsigned long)addr; \
void * __virt = addr; \
dma_addr_t __dma; \
if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \
__dma = __virt_to_lbus(__virt); \
else \
__dma = __virt_to_phys(__virt); \
__dma = __virt_to_phys((unsigned long)__virt); \
__dma; \
})

8
arch/arm/mach-iop13xx/io.c
View File

@ -33,14 +33,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
if (unlikely(!iop13xx_atux_mem_base))
retval = NULL;
else
retval = (void *)(iop13xx_atux_mem_base +
retval = (iop13xx_atux_mem_base +
(cookie - IOP13XX_PCIX_LOWER_MEM_RA));
break;
case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
if (unlikely(!iop13xx_atue_mem_base))
retval = NULL;
else
retval = (void *)(iop13xx_atue_mem_base +
retval = (iop13xx_atue_mem_base +
(cookie - IOP13XX_PCIE_LOWER_MEM_RA));
break;
case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
@ -49,7 +49,7 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
size, mtype, __builtin_return_address(0));
break;
case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
break;
default:
retval = __arm_ioremap_caller(cookie, size, mtype,
@ -74,7 +74,7 @@ static void __iop13xx_iounmap(volatile void __iomem *addr)
goto skip;
switch ((u32) addr) {
case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
goto skip;
}
__iounmap(addr);

16
arch/arm/mach-iop13xx/pci.c
View File

@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
static struct pci_bus *pci_bus_atux = 0;
static struct pci_bus *pci_bus_atue = 0;
u32 iop13xx_atue_mem_base;
u32 iop13xx_atux_mem_base;
void __iomem *iop13xx_atue_mem_base;
void __iomem *iop13xx_atux_mem_base;
size_t iop13xx_atue_mem_size;
size_t iop13xx_atux_mem_size;
@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void)
}
if (end) {
iop13xx_atux_mem_base =
(u32) __arm_ioremap_pfn(
iop13xx_atux_mem_base = __arm_ioremap_pfn(
__phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
, 0, iop13xx_atux_mem_size, MT_DEVICE);
if (!iop13xx_atux_mem_base) {
@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void)
}
} else
iop13xx_atux_mem_size = 0;
PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
__func__, atu, iop13xx_atux_mem_size,
iop13xx_atux_mem_base);
break;
@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void)
}
if (end) {
iop13xx_atue_mem_base =
(u32) __arm_ioremap_pfn(
iop13xx_atue_mem_base = __arm_ioremap_pfn(
__phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
, 0, iop13xx_atue_mem_size, MT_DEVICE);
if (!iop13xx_atue_mem_base) {
@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void)
}
} else
iop13xx_atue_mem_size = 0;
PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
__func__, atu, iop13xx_atue_mem_size,
iop13xx_atue_mem_base);
break;
}
printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
atu ? "ATUE" : "ATUX",
(atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
SZ_1M,

4
arch/arm/mach-iop13xx/pci.h
View File

@ -1,6 +1,6 @@
#include <linux/types.h>
extern u32 iop13xx_atue_mem_base;
extern u32 iop13xx_atux_mem_base;
extern void __iomem *iop13xx_atue_mem_base;
extern void __iomem *iop13xx_atux_mem_base;
extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size;

10
arch/arm/mach-iop13xx/setup.c
View File

@ -36,7 +36,7 @@
*/
static struct map_desc iop13xx_std_desc[] __initdata = {
{ /* mem mapped registers */
.virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
.virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
.length = IOP13XX_PMMR_SIZE,
.type = MT_DEVICE,
@ -71,8 +71,8 @@ static struct resource iop13xx_uart1_resources[] = {
static struct plat_serial8250_port iop13xx_uart0_data[] = {
{
.membase = (char*)(IOP13XX_UART0_VIRT),
.mapbase = (IOP13XX_UART0_PHYS),
.membase = IOP13XX_UART0_VIRT,
.mapbase = IOP13XX_UART0_PHYS,
.irq = IRQ_IOP13XX_UART0,
.uartclk = IOP13XX_UART_XTAL,
.regshift = 2,
@ -84,8 +84,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = {
static struct plat_serial8250_port iop13xx_uart1_data[] = {
{
.membase = (char*)(IOP13XX_UART1_VIRT),
.mapbase = (IOP13XX_UART1_PHYS),
.membase = IOP13XX_UART1_VIRT,
.mapbase = IOP13XX_UART1_PHYS,
.irq = IRQ_IOP13XX_UART1,
.uartclk = IOP13XX_UART_XTAL,
.regshift = 2,

2
arch/arm/mach-iop32x/glantank.c
View File

@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = {
static void glantank_power_off(void)
{
__raw_writeb(0x01, 0xfe8d0004);
__raw_writeb(0x01, IOMEM(0xfe8d0004));
while (1)
;

8
arch/arm/mach-ixp4xx/common.c
View File

@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx;
*************************************************************************/
static struct map_desc ixp4xx_io_desc[] __initdata = {
{ /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
.virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
.virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
.pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
.length = IXP4XX_PERIPHERAL_REGION_SIZE,
.type = MT_DEVICE
}, { /* Expansion Bus Config Registers */
.virtual = IXP4XX_EXP_CFG_BASE_VIRT,
.virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
.pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
.length = IXP4XX_EXP_CFG_REGION_SIZE,
.type = MT_DEVICE
}, { /* PCI Registers */
.virtual = IXP4XX_PCI_CFG_BASE_VIRT,
.virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
.length = IXP4XX_PCI_CFG_REGION_SIZE,
.type = MT_DEVICE
},
#ifdef CONFIG_DEBUG_LL
{ /* Debug UART mapping */
.virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
.virtual = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
.pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
.length = IXP4XX_DEBUG_UART_REGION_SIZE,
.type = MT_DEVICE

5
arch/arm/mach-ixp4xx/include/mach/cpu.h
View File

@ -14,6 +14,7 @@
#ifndef __ASM_ARCH_CPU_H__
#define __ASM_ARCH_CPU_H__
#include <linux/io.h>
#include <asm/cputype.h>
/* Processor id value in CP15 Register 0 */
@ -37,7 +38,7 @@
static inline u32 ixp4xx_read_feature_bits(void)
{
u32 val = ~*IXP4XX_EXP_CFG2;
u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
if (cpu_is_ixp42x_rev_a0())
return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
static inline void ixp4xx_write_feature_bits(u32 value)
{
*IXP4XX_EXP_CFG2 = ~value;
__raw_writel(~value, IXP4XX_EXP_CFG2);
}
#endif /* _ASM_ARCH_CPU_H */

10
arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
View File

@ -49,21 +49,21 @@
* Expansion BUS Configuration registers
*/
#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000)
#define IXP4XX_EXP_CFG_BASE_VIRT IOMEM(0xFFBFE000)
#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
/*
* PCI Config registers
*/
#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000)
#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFFBFF000)
#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
/*
* Peripheral space
*/
#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000)
#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFFBEB000)
#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
/*
@ -73,7 +73,7 @@
* aligned so that it * can be used with the low-level debug code.
*/
#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000)
#define IXP4XX_DEBUG_UART_BASE_VIRT IOMEM(0xffb00000)
#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
#define IXP4XX_EXP_CS0_OFFSET 0x00
@ -92,7 +92,7 @@
/*
* Expansion Bus Controller registers.
*/
#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)

2
arch/arm/mach-ks8695/cpu.c
View File

@ -36,7 +36,7 @@
static struct __initdata map_desc ks8695_io_desc[] = {
{
.virtual = KS8695_IO_VA,
.virtual = (unsigned long)KS8695_IO_VA,
.pfn = __phys_to_pfn(KS8695_IO_PA),
.length = KS8695_IO_SIZE,
.type = MT_DEVICE,

2
arch/arm/mach-ks8695/include/mach/hardware.h
View File

@ -33,7 +33,7 @@
* head debug code as the initial MMU setup only deals in L1 sections.
*/
#define KS8695_IO_PA 0x03F00000
#define KS8695_IO_VA 0xF0000000
#define KS8695_IO_VA IOMEM(0xF0000000)
#define KS8695_IO_SIZE SZ_1M
#define KS8695_PCIMEM_PA 0x60000000

6
arch/arm/mach-ks8695/include/mach/uncompress.h
View File

@ -19,15 +19,15 @@
static void putc(char c)
{
while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
barrier();
__raw_writel(c, KS8695_UART_PA + KS8695_URTH);
__raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH);
}
static inline void flush(void)
{
while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
barrier();
}

8
arch/arm/mach-lpc32xx/common.c
View File

@ -177,25 +177,25 @@ u32 clk_get_pclk_div(void)
static struct map_desc lpc32xx_io_desc[] __initdata = {
{
.virtual = IO_ADDRESS(LPC32XX_AHB0_START),
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
.pfn = __phys_to_pfn(LPC32XX_AHB0_START),
.length = LPC32XX_AHB0_SIZE,
.type = MT_DEVICE
},
{
.virtual = IO_ADDRESS(LPC32XX_AHB1_START),
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
.pfn = __phys_to_pfn(LPC32XX_AHB1_START),
.length = LPC32XX_AHB1_SIZE,
.type = MT_DEVICE
},
{
.virtual = IO_ADDRESS(LPC32XX_FABAPB_START),
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
.pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
.length = LPC32XX_FABAPB_SIZE,
.type = MT_DEVICE
},
{
.virtual = IO_ADDRESS(LPC32XX_IRAM_BASE),
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
.pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
.length = (LPC32XX_IRAM_BANK_SIZE * 2),
.type = MT_DEVICE

2
arch/arm/mach-lpc32xx/include/mach/hardware.h
View File

@ -25,7 +25,7 @@
/*
* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
*/
#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
IO_BASE)
#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))

19
arch/arm/mach-msm/smd.c
View File

@ -49,13 +49,14 @@ static int msm_smd_debug_mask;
struct shared_info {
int ready;
unsigned state;
void __iomem *state;
};
static unsigned dummy_state[SMSM_STATE_COUNT];
static struct shared_info smd_info = {
.state = (unsigned) &dummy_state,
/* FIXME: not a real __iomem pointer */
.state = &dummy_state,
};
module_param_named(debug_mask, msm_smd_debug_mask,
@ -789,22 +790,22 @@ void *smem_alloc(unsigned id, unsigned size)
return smem_find(id, size);
}
void *smem_item(unsigned id, unsigned *size)
void __iomem *smem_item(unsigned id, unsigned *size)
{
struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
struct smem_heap_entry *toc = shared->heap_toc;
if (id >= SMEM_NUM_ITEMS)
return 0;
return NULL;
if (toc[id].allocated) {
*size = toc[id].size;
return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset);
return (MSM_SHARED_RAM_BASE + toc[id].offset);
} else {
*size = 0;
}
return 0;
return NULL;
}
void *smem_find(unsigned id, unsigned size_in)
@ -850,7 +851,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data)
int smsm_change_state(enum smsm_state_item item,
uint32_t clear_mask, uint32_t set_mask)
{
unsigned long addr = smd_info.state + item * 4;
void __iomem *addr = smd_info.state + item * 4;
unsigned long flags;
unsigned state;
@ -936,10 +937,10 @@ int smd_core_init(void)
/* wait for essential items to be initialized */
for (;;) {
unsigned size;
void *state;
void __iomem *state;
state = smem_item(SMEM_SMSM_SHARED_STATE, &size);
if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) {
smd_info.state = (unsigned)state;
smd_info.state = state;
break;
}
}

2
arch/arm/mach-nomadik/include/mach/hardware.h
View File

@ -30,7 +30,7 @@
- NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
/* used in asm code, so no casts */
#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
/*
* Base address defination for Nomadik Onchip Logic Block

8
arch/arm/mach-nomadik/include/mach/uncompress.h
View File

@ -27,10 +27,10 @@
struct amba_device;
#include <linux/amba/serial.h>
#define NOMADIK_UART_DR 0x101FB000
#define NOMADIK_UART_LCRH 0x101FB02c
#define NOMADIK_UART_CR 0x101FB030
#define NOMADIK_UART_FR 0x101FB018
#define NOMADIK_UART_DR (void __iomem *)0x101FB000
#define NOMADIK_UART_LCRH (void __iomem *)0x101FB02c
#define NOMADIK_UART_CR (void __iomem *)0x101FB030
#define NOMADIK_UART_FR (void __iomem *)0x101FB018
static void putc(const char c)
{

4
arch/arm/mach-prima2/include/mach/uncompress.h
View File

@ -25,11 +25,11 @@ static __inline__ void putc(char c)
* during kernel decompression, all mappings are flat:
* virt_addr == phys_addr
*/
while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
& SIRFSOC_UART1_TXFIFO_FULL)
barrier();
__raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
__raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
}
static inline void flush(void)

2
arch/arm/mach-sa1100/include/mach/simpad.h
View File

@ -87,7 +87,7 @@
#define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22)
#define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23)
#define CS3_BASE 0xf1000000
#define CS3_BASE IOMEM(0xf1000000)
long simpad_get_cs3_ro(void);
long simpad_get_cs3_shadow(void);

2
arch/arm/mach-sa1100/simpad.c
View File

@ -124,7 +124,7 @@ static struct map_desc simpad_io_desc[] __initdata = {
.length = 0x00800000,
.type = MT_DEVICE
}, { /* Simpad CS3 */
.virtual = CS3_BASE,
.virtual = (unsigned long)CS3_BASE,
.pfn = __phys_to_pfn(SA1100_CS3_PHYS),
.length = 0x00100000,
.type = MT_DEVICE

12
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -432,7 +432,7 @@ static void usb1_host_port_power(int port, int power)
return;
/* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
__raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
__raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
}
static struct r8a66597_platdata usb1_host_data = {
@ -1224,9 +1224,9 @@ static struct i2c_board_info i2c1_devices[] = {
};
#define GPIO_PORT9CR 0xE6051009
#define GPIO_PORT10CR 0xE605100A
#define USCCR1 0xE6058144
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define USCCR1 IOMEM(0xE6058144)
static void __init ap4evb_init(void)
{
u32 srcr4;
@ -1304,7 +1304,7 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_OVCN2_1, NULL);
/* setup USB phy */
__raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
__raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */
/* enable FSI2 port A (ak4643) */
gpio_request(GPIO_FN_FSIAIBT, NULL);
@ -1453,7 +1453,7 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_HDMI_CEC, NULL);
/* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
#define SRCR4 0xe61580bc
#define SRCR4 IOMEM(0xe61580bc)
srcr4 = __raw_readl(SRCR4);
__raw_writel(srcr4 | (1 << 13), SRCR4);
udelay(50);

6
arch/arm/mach-shmobile/board-armadillo800eva.c
View File

@ -135,7 +135,7 @@
* usbhsf_power_ctrl()
*/
#define IRQ7 evt2irq(0x02e0)
#define USBCR1 0xe605810a
#define USBCR1 IOMEM(0xe605810a)
#define USBH 0xC6700000
#define USBH_USBCTR 0x10834
@ -950,8 +950,8 @@ clock_error:
/*
* board init
*/
#define GPIO_PORT7CR 0xe6050007
#define GPIO_PORT8CR 0xe6050008
#define GPIO_PORT7CR IOMEM(0xe6050007)
#define GPIO_PORT8CR IOMEM(0xe6050008)
static void __init eva_init(void)
{
struct platform_device *usb = NULL;

8
arch/arm/mach-shmobile/board-bonito.c
View File

@ -108,12 +108,12 @@ static struct regulator_consumer_supply dummy_supplies[] = {
#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
static u16 bonito_fpga_read(u32 offset)
{
return __raw_readw(0xf0003000 + offset);
return __raw_readw(IOMEM(0xf0003000) + offset);
}
static void bonito_fpga_write(u32 offset, u16 val)
{
__raw_writew(val, 0xf0003000 + offset);
__raw_writew(val, IOMEM(0xf0003000) + offset);
}
static void bonito_fpga_irq_disable(struct irq_data *data)
@ -361,8 +361,8 @@ static void __init bonito_map_io(void)
#define BIT_ON(sw, bit) (sw & (1 << bit))
#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
#define VCCQ1CR 0xE6058140
#define VCCQ1LCDCR 0xE6058186
#define VCCQ1CR IOMEM(0xE6058140)
#define VCCQ1LCDCR IOMEM(0xE6058186)
static void __init bonito_init(void)
{

12
arch/arm/mach-shmobile/board-g3evm.c
View File

@ -106,7 +106,7 @@ static void usb_host_port_power(int port, int power)
return;
/* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
__raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
__raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
}
static struct r8a66597_platdata usb_host_data = {
@ -279,10 +279,10 @@ static void __init g3evm_init(void)
gpio_request(GPIO_FN_IDIN, NULL);
/* setup USB phy */
__raw_writew(0x0300, 0xe605810a); /* USBCR1 */
__raw_writew(0x00e0, 0xe60581c0); /* CPFCH */
__raw_writew(0x6010, 0xe60581c6); /* CGPOSR */
__raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */
__raw_writew(0x0300, IOMEM(0xe605810a)); /* USBCR1 */
__raw_writew(0x00e0, IOMEM(0xe60581c0)); /* CPFCH */
__raw_writew(0x6010, IOMEM(0xe60581c6)); /* CGPOSR */
__raw_writew(0x8a0a, IOMEM(0xe605810c)); /* USBCR2 */
/* KEYSC @ CN7 */
gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL);
@ -320,7 +320,7 @@ static void __init g3evm_init(void)
gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL);
gpio_request(GPIO_FN_FRB, NULL);
/* FOE, FCDE, FSC on dedicated pins */
__raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
__raw_writel(__raw_readl(IOMEM(0xe6158048)) & ~(1 << 15), IOMEM(0xe6158048));
/* IrDA */
gpio_request(GPIO_FN_IRDA_OUT, NULL);

30
arch/arm/mach-shmobile/board-g4evm.c
View File

@ -126,7 +126,7 @@ static void usb_host_port_power(int port, int power)
return;
/* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
__raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
__raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
}
static struct r8a66597_platdata usb_host_data = {
@ -270,17 +270,17 @@ static struct platform_device *g4evm_devices[] __initdata = {
&sdhi1_device,
};
#define GPIO_SDHID0_D0 0xe60520fc
#define GPIO_SDHID0_D1 0xe60520fd
#define GPIO_SDHID0_D2 0xe60520fe
#define GPIO_SDHID0_D3 0xe60520ff
#define GPIO_SDHICMD0 0xe6052100
#define GPIO_SDHID0_D0 IOMEM(0xe60520fc)
#define GPIO_SDHID0_D1 IOMEM(0xe60520fd)
#define GPIO_SDHID0_D2 IOMEM(0xe60520fe)
#define GPIO_SDHID0_D3 IOMEM(0xe60520ff)
#define GPIO_SDHICMD0 IOMEM(0xe6052100)
#define GPIO_SDHID1_D0 0xe6052103
#define GPIO_SDHID1_D1 0xe6052104
#define GPIO_SDHID1_D2 0xe6052105
#define GPIO_SDHID1_D3 0xe6052106
#define GPIO_SDHICMD1 0xe6052107
#define GPIO_SDHID1_D0 IOMEM(0xe6052103)
#define GPIO_SDHID1_D1 IOMEM(0xe6052104)
#define GPIO_SDHID1_D2 IOMEM(0xe6052105)
#define GPIO_SDHID1_D3 IOMEM(0xe6052106)
#define GPIO_SDHICMD1 IOMEM(0xe6052107)
static void __init g4evm_init(void)
{
@ -318,10 +318,10 @@ static void __init g4evm_init(void)
gpio_request(GPIO_FN_IDIN, NULL);
/* setup USB phy */
__raw_writew(0x0200, 0xe605810a); /* USBCR1 */
__raw_writew(0x00e0, 0xe60581c0); /* CPFCH */
__raw_writew(0x6010, 0xe60581c6); /* CGPOSR */
__raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */
__raw_writew(0x0200, IOMEM(0xe605810a)); /* USBCR1 */
__raw_writew(0x00e0, IOMEM(0xe60581c0)); /* CPFCH */
__raw_writew(0x6010, IOMEM(0xe60581c6)); /* CGPOSR */
__raw_writew(0x8a0a, IOMEM(0xe605810c)); /* USBCR2 */
/* KEYSC @ CN31 */
gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL);

8
arch/arm/mach-shmobile/board-kzm9g.c
View File

@ -133,8 +133,8 @@ static struct platform_device usb_host_device = {
/* USB Func CN17 */
struct usbhs_private {
unsigned int phy;
unsigned int cr2;
void __iomem *phy;
void __iomem *cr2;
struct renesas_usbhs_platform_info info;
};
@ -232,8 +232,8 @@ static u32 usbhs_pipe_cfg[] = {
};
static struct usbhs_private usbhs_private = {
.phy = 0xe60781e0, /* USBPHYINT */
.cr2 = 0xe605810c, /* USBCR2 */
.phy = IOMEM(0xe60781e0), /* USBPHYINT */
.cr2 = IOMEM(0xe605810c), /* USBCR2 */
.info = {
.platform_callback = {
.hardware_init = usbhs_hardware_init,

22
arch/arm/mach-shmobile/board-mackerel.c
View File

@ -583,8 +583,8 @@ out:
#define USBHS0_POLL_INTERVAL (HZ * 5)
struct usbhs_private {
unsigned int usbphyaddr;
unsigned int usbcrcaddr;
void __iomem *usbphyaddr;
void __iomem *usbcrcaddr;
struct renesas_usbhs_platform_info info;
struct delayed_work work;
struct platform_device *pdev;
@ -642,7 +642,7 @@ static void usbhs0_hardware_exit(struct platform_device *pdev)
}
static struct usbhs_private usbhs0_private = {
.usbcrcaddr = 0xe605810c, /* USBCR2 */
.usbcrcaddr = IOMEM(0xe605810c), /* USBCR2 */
.info = {
.platform_callback = {
.hardware_init = usbhs0_hardware_init,
@ -776,8 +776,8 @@ static u32 usbhs1_pipe_cfg[] = {
};
static struct usbhs_private usbhs1_private = {
.usbphyaddr = 0xe60581e2, /* USBPHY1INTAP */
.usbcrcaddr = 0xe6058130, /* USBCR4 */
.usbphyaddr = IOMEM(0xe60581e2), /* USBPHY1INTAP */
.usbcrcaddr = IOMEM(0xe6058130), /* USBCR4 */
.info = {
.platform_callback = {
.hardware_init = usbhs1_hardware_init,
@ -1402,12 +1402,12 @@ static struct i2c_board_info i2c1_devices[] = {
},
};
#define GPIO_PORT9CR 0xE6051009
#define GPIO_PORT10CR 0xE605100A
#define GPIO_PORT167CR 0xE60520A7
#define GPIO_PORT168CR 0xE60520A8
#define SRCR4 0xe61580bc
#define USCCR1 0xE6058144
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define GPIO_PORT167CR IOMEM(0xE60520A7)
#define GPIO_PORT168CR IOMEM(0xE60520A8)
#define SRCR4 IOMEM(0xe61580bc)
#define USCCR1 IOMEM(0xE6058144)
static void __init mackerel_init(void)
{
u32 srcr4;

42
arch/arm/mach-shmobile/clock-r8a7740.c
View File

@ -41,29 +41,29 @@
*/
/* CPG registers */
#define FRQCRA 0xe6150000
#define FRQCRB 0xe6150004
#define VCLKCR1 0xE6150008
#define VCLKCR2 0xE615000c
#define FRQCRC 0xe61500e0
#define FSIACKCR 0xe6150018
#define PLLC01CR 0xe6150028
#define FRQCRA IOMEM(0xe6150000)
#define FRQCRB IOMEM(0xe6150004)
#define VCLKCR1 IOMEM(0xE6150008)
#define VCLKCR2 IOMEM(0xE615000c)
#define FRQCRC IOMEM(0xe61500e0)
#define FSIACKCR IOMEM(0xe6150018)
#define PLLC01CR IOMEM(0xe6150028)
#define SUBCKCR 0xe6150080
#define USBCKCR 0xe615008c
#define SUBCKCR IOMEM(0xe6150080)
#define USBCKCR IOMEM(0xe615008c)
#define MSTPSR0 0xe6150030
#define MSTPSR1 0xe6150038
#define MSTPSR2 0xe6150040
#define MSTPSR3 0xe6150048
#define MSTPSR4 0xe615004c
#define FSIBCKCR 0xe6150090
#define HDMICKCR 0xe6150094
#define SMSTPCR0 0xe6150130
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
#define SMSTPCR3 0xe615013c
#define SMSTPCR4 0xe6150140
#define MSTPSR0 IOMEM(0xe6150030)
#define MSTPSR1 IOMEM(0xe6150038)
#define MSTPSR2 IOMEM(0xe6150040)
#define MSTPSR3 IOMEM(0xe6150048)
#define MSTPSR4 IOMEM(0xe615004c)
#define FSIBCKCR IOMEM(0xe6150090)
#define HDMICKCR IOMEM(0xe6150094)
#define SMSTPCR0 IOMEM(0xe6150130)
#define SMSTPCR1 IOMEM(0xe6150134)
#define SMSTPCR2 IOMEM(0xe6150138)
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR4 IOMEM(0xe6150140)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk extalr_clk = {

44
arch/arm/mach-shmobile/clock-sh7367.c
View File

@ -24,28 +24,28 @@
#include <mach/common.h>
/* SH7367 registers */
#define RTFRQCR 0xe6150000
#define SYFRQCR 0xe6150004
#define CMFRQCR 0xe61500E0
#define VCLKCR1 0xe6150008
#define VCLKCR2 0xe615000C
#define VCLKCR3 0xe615001C
#define SCLKACR 0xe6150010
#define SCLKBCR 0xe6150014
#define SUBUSBCKCR 0xe6158080
#define SPUCKCR 0xe6150084
#define MSUCKCR 0xe6150088
#define MVI3CKCR 0xe6150090
#define VOUCKCR 0xe6150094
#define MFCK1CR 0xe6150098
#define MFCK2CR 0xe615009C
#define PLLC1CR 0xe6150028
#define PLLC2CR 0xe615002C
#define RTMSTPCR0 0xe6158030
#define RTMSTPCR2 0xe6158038
#define SYMSTPCR0 0xe6158040
#define SYMSTPCR2 0xe6158048
#define CMMSTPCR0 0xe615804c
#define RTFRQCR IOMEM(0xe6150000)
#define SYFRQCR IOMEM(0xe6150004)
#define CMFRQCR IOMEM(0xe61500E0)
#define VCLKCR1 IOMEM(0xe6150008)
#define VCLKCR2 IOMEM(0xe615000C)
#define VCLKCR3 IOMEM(0xe615001C)
#define SCLKACR IOMEM(0xe6150010)
#define SCLKBCR IOMEM(0xe6150014)
#define SUBUSBCKCR IOMEM(0xe6158080)
#define SPUCKCR IOMEM(0xe6150084)
#define MSUCKCR IOMEM(0xe6150088)
#define MVI3CKCR IOMEM(0xe6150090)
#define VOUCKCR IOMEM(0xe6150094)
#define MFCK1CR IOMEM(0xe6150098)
#define MFCK2CR IOMEM(0xe615009C)
#define PLLC1CR IOMEM(0xe6150028)
#define PLLC2CR IOMEM(0xe615002C)
#define RTMSTPCR0 IOMEM(0xe6158030)
#define RTMSTPCR2 IOMEM(0xe6158038)
#define SYMSTPCR0 IOMEM(0xe6158040)
#define SYMSTPCR2 IOMEM(0xe6158048)
#define CMMSTPCR0 IOMEM(0xe615804c)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {

60
arch/arm/mach-shmobile/clock-sh7372.c
View File

@ -24,36 +24,36 @@
#include <mach/common.h>
/* SH7372 registers */
#define FRQCRA 0xe6150000
#define FRQCRB 0xe6150004
#define FRQCRC 0xe61500e0
#define FRQCRD 0xe61500e4
#define VCLKCR1 0xe6150008
#define VCLKCR2 0xe615000c
#define VCLKCR3 0xe615001c
#define FMSICKCR 0xe6150010
#define FMSOCKCR 0xe6150014
#define FSIACKCR 0xe6150018
#define FSIBCKCR 0xe6150090
#define SUBCKCR 0xe6150080
#define SPUCKCR 0xe6150084
#define VOUCKCR 0xe6150088
#define HDMICKCR 0xe6150094
#define DSITCKCR 0xe6150060
#define DSI0PCKCR 0xe6150064
#define DSI1PCKCR 0xe6150098
#define PLLC01CR 0xe6150028
#define PLLC2CR 0xe615002c
#define RMSTPCR0 0xe6150110
#define RMSTPCR1 0xe6150114
#define RMSTPCR2 0xe6150118
#define RMSTPCR3 0xe615011c
#define RMSTPCR4 0xe6150120
#define SMSTPCR0 0xe6150130
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
#define SMSTPCR3 0xe615013c
#define SMSTPCR4 0xe6150140
#define FRQCRA IOMEM(0xe6150000)
#define FRQCRB IOMEM(0xe6150004)
#define FRQCRC IOMEM(0xe61500e0)
#define FRQCRD IOMEM(0xe61500e4)
#define VCLKCR1 IOMEM(0xe6150008)
#define VCLKCR2 IOMEM(0xe615000c)
#define VCLKCR3 IOMEM(0xe615001c)
#define FMSICKCR IOMEM(0xe6150010)
#define FMSOCKCR IOMEM(0xe6150014)
#define FSIACKCR IOMEM(0xe6150018)
#define FSIBCKCR IOMEM(0xe6150090)
#define SUBCKCR IOMEM(0xe6150080)
#define SPUCKCR IOMEM(0xe6150084)
#define VOUCKCR IOMEM(0xe6150088)
#define HDMICKCR IOMEM(0xe6150094)
#define DSITCKCR IOMEM(0xe6150060)
#define DSI0PCKCR IOMEM(0xe6150064)
#define DSI1PCKCR IOMEM(0xe6150098)
#define PLLC01CR IOMEM(0xe6150028)
#define PLLC2CR IOMEM(0xe615002c)
#define RMSTPCR0 IOMEM(0xe6150110)
#define RMSTPCR1 IOMEM(0xe6150114)
#define RMSTPCR2 IOMEM(0xe6150118)
#define RMSTPCR3 IOMEM(0xe615011c)
#define RMSTPCR4 IOMEM(0xe6150120)
#define SMSTPCR0 IOMEM(0xe6150130)
#define SMSTPCR1 IOMEM(0xe6150134)
#define SMSTPCR2 IOMEM(0xe6150138)
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR4 IOMEM(0xe6150140)
#define FSIDIVA 0xFE1F8000
#define FSIDIVB 0xFE1F8008

50
arch/arm/mach-shmobile/clock-sh7377.c
View File

@ -24,31 +24,31 @@
#include <mach/common.h>
/* SH7377 registers */
#define RTFRQCR 0xe6150000
#define SYFRQCR 0xe6150004
#define CMFRQCR 0xe61500E0
#define VCLKCR1 0xe6150008
#define VCLKCR2 0xe615000C
#define VCLKCR3 0xe615001C
#define FMSICKCR 0xe6150010
#define FMSOCKCR 0xe6150014
#define FSICKCR 0xe6150018
#define PLLC1CR 0xe6150028
#define PLLC2CR 0xe615002C
#define SUBUSBCKCR 0xe6150080
#define SPUCKCR 0xe6150084
#define MSUCKCR 0xe6150088
#define MVI3CKCR 0xe6150090
#define HDMICKCR 0xe6150094
#define MFCK1CR 0xe6150098
#define MFCK2CR 0xe615009C
#define DSITCKCR 0xe6150060
#define DSIPCKCR 0xe6150064
#define SMSTPCR0 0xe6150130
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
#define SMSTPCR3 0xe615013C
#define SMSTPCR4 0xe6150140
#define RTFRQCR IOMEM(0xe6150000)
#define SYFRQCR IOMEM(0xe6150004)
#define CMFRQCR IOMEM(0xe61500E0)
#define VCLKCR1 IOMEM(0xe6150008)
#define VCLKCR2 IOMEM(0xe615000C)
#define VCLKCR3 IOMEM(0xe615001C)
#define FMSICKCR IOMEM(0xe6150010)
#define FMSOCKCR IOMEM(0xe6150014)
#define FSICKCR IOMEM(0xe6150018)
#define PLLC1CR IOMEM(0xe6150028)
#define PLLC2CR IOMEM(0xe615002C)
#define SUBUSBCKCR IOMEM(0xe6150080)
#define SPUCKCR IOMEM(0xe6150084)
#define MSUCKCR IOMEM(0xe6150088)
#define MVI3CKCR IOMEM(0xe6150090)
#define HDMICKCR IOMEM(0xe6150094)
#define MFCK1CR IOMEM(0xe6150098)
#define MFCK2CR IOMEM(0xe615009C)
#define DSITCKCR IOMEM(0xe6150060)
#define DSIPCKCR IOMEM(0xe6150064)
#define SMSTPCR0 IOMEM(0xe6150130)
#define SMSTPCR1 IOMEM(0xe6150134)
#define SMSTPCR2 IOMEM(0xe6150138)
#define SMSTPCR3 IOMEM(0xe615013C)
#define SMSTPCR4 IOMEM(0xe6150140)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {

70
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -23,43 +23,43 @@
#include <linux/clkdev.h>
#include <mach/common.h>
#define FRQCRA 0xe6150000
#define FRQCRB 0xe6150004
#define FRQCRD 0xe61500e4
#define VCLKCR1 0xe6150008
#define VCLKCR2 0xe615000C
#define VCLKCR3 0xe615001C
#define ZBCKCR 0xe6150010
#define FLCKCR 0xe6150014
#define SD0CKCR 0xe6150074
#define SD1CKCR 0xe6150078
#define SD2CKCR 0xe615007C
#define FSIACKCR 0xe6150018
#define FSIBCKCR 0xe6150090
#define SUBCKCR 0xe6150080
#define SPUACKCR 0xe6150084
#define SPUVCKCR 0xe6150094
#define MSUCKCR 0xe6150088
#define HSICKCR 0xe615008C
#define MFCK1CR 0xe6150098
#define MFCK2CR 0xe615009C
#define DSITCKCR 0xe6150060
#define DSI0PCKCR 0xe6150064
#define DSI1PCKCR 0xe6150068
#define FRQCRA IOMEM(0xe6150000)
#define FRQCRB IOMEM(0xe6150004)
#define FRQCRD IOMEM(0xe61500e4)
#define VCLKCR1 IOMEM(0xe6150008)
#define VCLKCR2 IOMEM(0xe615000C)
#define VCLKCR3 IOMEM(0xe615001C)
#define ZBCKCR IOMEM(0xe6150010)
#define FLCKCR IOMEM(0xe6150014)
#define SD0CKCR IOMEM(0xe6150074)
#define SD1CKCR IOMEM(0xe6150078)
#define SD2CKCR IOMEM(0xe615007C)
#define FSIACKCR IOMEM(0xe6150018)
#define FSIBCKCR IOMEM(0xe6150090)
#define SUBCKCR IOMEM(0xe6150080)
#define SPUACKCR IOMEM(0xe6150084)
#define SPUVCKCR IOMEM(0xe6150094)
#define MSUCKCR IOMEM(0xe6150088)
#define HSICKCR IOMEM(0xe615008C)
#define MFCK1CR IOMEM(0xe6150098)
#define MFCK2CR IOMEM(0xe615009C)
#define DSITCKCR IOMEM(0xe6150060)
#define DSI0PCKCR IOMEM(0xe6150064)
#define DSI1PCKCR IOMEM(0xe6150068)
#define DSI0PHYCR 0xe615006C
#define DSI1PHYCR 0xe6150070
#define PLLECR 0xe61500d0
#define PLL0CR 0xe61500d8
#define PLL1CR 0xe6150028
#define PLL2CR 0xe615002c
#define PLL3CR 0xe61500dc
#define SMSTPCR0 0xe6150130
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
#define SMSTPCR3 0xe615013c
#define SMSTPCR4 0xe6150140
#define SMSTPCR5 0xe6150144
#define CKSCR 0xe61500c0
#define PLLECR IOMEM(0xe61500d0)
#define PLL0CR IOMEM(0xe61500d8)
#define PLL1CR IOMEM(0xe6150028)
#define PLL2CR IOMEM(0xe615002c)
#define PLL3CR IOMEM(0xe61500dc)
#define SMSTPCR0 IOMEM(0xe6150130)
#define SMSTPCR1 IOMEM(0xe6150134)
#define SMSTPCR2 IOMEM(0xe6150138)
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR4 IOMEM(0xe6150140)
#define SMSTPCR5 IOMEM(0xe6150144)
#define CKSCR IOMEM(0xe61500c0)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {

6
arch/arm/mach-shmobile/include/mach/gpio.h
View File

@ -35,12 +35,12 @@ static inline int irq_to_gpio(unsigned int irq)
* the method to control only pull up/down/free.
* this function should be replaced by correct gpio function
*/
static inline void __init gpio_direction_none(u32 addr)
static inline void __init gpio_direction_none(void __iomem * addr)
{
__raw_writeb(0x00, addr);
}
static inline void __init gpio_request_pullup(u32 addr)
static inline void __init gpio_request_pullup(void __iomem * addr)
{
u8 data = __raw_readb(addr);
@ -49,7 +49,7 @@ static inline void __init gpio_request_pullup(u32 addr)
__raw_writeb(data, addr);
}
static inline void __init gpio_request_pulldown(u32 addr)
static inline void __init gpio_request_pulldown(void __iomem * addr)
{
u8 data = __raw_readb(addr);

14
arch/arm/mach-shmobile/intc-r8a7779.c
View File

@ -29,14 +29,14 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#define INT2SMSKCR0 0xfe7822a0
#define INT2SMSKCR1 0xfe7822a4
#define INT2SMSKCR2 0xfe7822a8
#define INT2SMSKCR3 0xfe7822ac
#define INT2SMSKCR4 0xfe7822b0
#define INT2SMSKCR0 IOMEM(0xfe7822a0)
#define INT2SMSKCR1 IOMEM(0xfe7822a4)
#define INT2SMSKCR2 IOMEM(0xfe7822a8)
#define INT2SMSKCR3 IOMEM(0xfe7822ac)
#define INT2SMSKCR4 IOMEM(0xfe7822b0)
#define INT2NTSR0 0xfe700060
#define INT2NTSR1 0xfe700064
#define INT2NTSR0 IOMEM(0xfe700060)
#define INT2NTSR1 IOMEM(0xfe700064)
static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
{

27
arch/arm/mach-shmobile/intc-sh7372.c
View File

@ -624,6 +624,9 @@ void sh7372_intcs_resume(void)
__raw_writeb(ffd5[k], intcs_ffd5 + k);
}
#define E694_BASE IOMEM(0xe6940000)
#define E695_BASE IOMEM(0xe6950000)
static unsigned short e694[0x200];
static unsigned short e695[0x200];
@ -632,22 +635,22 @@ void sh7372_intca_suspend(void)
int k;
for (k = 0x00; k <= 0x38; k += 4)
e694[k] = __raw_readw(0xe6940000 + k);
e694[k] = __raw_readw(E694_BASE + k);
for (k = 0x80; k <= 0xb4; k += 4)
e694[k] = __raw_readb(0xe6940000 + k);
e694[k] = __raw_readb(E694_BASE + k);
for (k = 0x180; k <= 0x1b4; k += 4)
e694[k] = __raw_readb(0xe6940000 + k);
e694[k] = __raw_readb(E694_BASE + k);
for (k = 0x00; k <= 0x50; k += 4)
e695[k] = __raw_readw(0xe6950000 + k);
e695[k] = __raw_readw(E695_BASE + k);
for (k = 0x80; k <= 0xa8; k += 4)
e695[k] = __raw_readb(0xe6950000 + k);
e695[k] = __raw_readb(E695_BASE + k);
for (k = 0x180; k <= 0x1a8; k += 4)
e695[k] = __raw_readb(0xe6950000 + k);
e695[k] = __raw_readb(E695_BASE + k);
}
void sh7372_intca_resume(void)
@ -655,20 +658,20 @@ void sh7372_intca_resume(void)
int k;
for (k = 0x00; k <= 0x38; k += 4)
__raw_writew(e694[k], 0xe6940000 + k);
__raw_writew(e694[k], E694_BASE + k);
for (k = 0x80; k <= 0xb4; k += 4)
__raw_writeb(e694[k], 0xe6940000 + k);
__raw_writeb(e694[k], E694_BASE + k);
for (k = 0x180; k <= 0x1b4; k += 4)
__raw_writeb(e694[k], 0xe6940000 + k);
__raw_writeb(e694[k], E694_BASE + k);
for (k = 0x00; k <= 0x50; k += 4)
__raw_writew(e695[k], 0xe6950000 + k);
__raw_writew(e695[k], E695_BASE + k);
for (k = 0x80; k <= 0xa8; k += 4)
__raw_writeb(e695[k], 0xe6950000 + k);
__raw_writeb(e695[k], E695_BASE + k);
for (k = 0x180; k <= 0x1a8; k += 4)
__raw_writeb(e695[k], 0xe6950000 + k);
__raw_writeb(e695[k], E695_BASE + k);
}

20
arch/arm/mach-shmobile/intc-sh73a0.c
View File

@ -366,10 +366,12 @@ static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
static struct irqaction sh73a0_irq_pin_cascade[32];
#define PINTER0 0xe69000a0
#define PINTER1 0xe69000a4
#define PINTRR0 0xe69000d0
#define PINTRR1 0xe69000d4
#define PINTER0_PHYS 0xe69000a0
#define PINTER1_PHYS 0xe69000a4
#define PINTER0_VIRT IOMEM(0xe69000a0)
#define PINTER1_VIRT IOMEM(0xe69000a4)
#define PINTRR0 IOMEM(0xe69000d0)
#define PINTRR1 IOMEM(0xe69000d4)
#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
@ -377,14 +379,14 @@ static struct irqaction sh73a0_irq_pin_cascade[32];
#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0", \
INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0", \
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \
INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \
INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1", \
INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \
INTC_PINT_V_NONE, INTC_PINT_V_NONE, \
@ -394,7 +396,7 @@ INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \
static struct irqaction sh73a0_pint0_cascade;
static struct irqaction sh73a0_pint1_cascade;
static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq)
{
unsigned long value = ioread32(rr) & ioread32(er);
int k;
@ -409,13 +411,13 @@ static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
{
pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0));
return IRQ_HANDLED;
}
static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
{
pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0));
return IRQ_HANDLED;
}

6
arch/arm/mach-shmobile/pm-rmobile.c
View File

@ -20,9 +20,9 @@
#include <mach/pm-rmobile.h>
/* SYSC */
#define SPDCR 0xe6180008
#define SWUCR 0xe6180014
#define PSTR 0xe6180080
#define SPDCR IOMEM(0xe6180008)
#define SWUCR IOMEM(0xe6180014)
#define PSTR IOMEM(0xe6180080)
#define PSTR_RETRIES 100
#define PSTR_DELAY_US 10

57
arch/arm/mach-shmobile/pm-sh7372.c
View File

@ -29,45 +29,46 @@
#include <mach/pm-rmobile.h>
/* DBG */
#define DBGREG1 0xe6100020
#define DBGREG9 0xe6100040
#define DBGREG1 IOMEM(0xe6100020)
#define DBGREG9 IOMEM(0xe6100040)
/* CPGA */
#define SYSTBCR 0xe6150024
#define MSTPSR0 0xe6150030
#define MSTPSR1 0xe6150038
#define MSTPSR2 0xe6150040
#define MSTPSR3 0xe6150048
#define MSTPSR4 0xe615004c
#define PLLC01STPCR 0xe61500c8
#define SYSTBCR IOMEM(0xe6150024)
#define MSTPSR0 IOMEM(0xe6150030)
#define MSTPSR1 IOMEM(0xe6150038)
#define MSTPSR2 IOMEM(0xe6150040)
#define MSTPSR3 IOMEM(0xe6150048)
#define MSTPSR4 IOMEM(0xe615004c)
#define PLLC01STPCR IOMEM(0xe61500c8)
/* SYSC */
#define SBAR 0xe6180020
#define WUPRMSK 0xe6180028
#define WUPSMSK 0xe618002c
#define WUPSMSK2 0xe6180048
#define WUPSFAC 0xe6180098
#define IRQCR 0xe618022c
#define IRQCR2 0xe6180238
#define IRQCR3 0xe6180244
#define IRQCR4 0xe6180248
#define PDNSEL 0xe6180254
#define SBAR IOMEM(0xe6180020)
#define WUPRMSK IOMEM(0xe6180028)
#define WUPSMSK IOMEM(0xe618002c)
#define WUPSMSK2 IOMEM(0xe6180048)
#define WUPSFAC IOMEM(0xe6180098)
#define IRQCR IOMEM(0xe618022c)
#define IRQCR2 IOMEM(0xe6180238)
#define IRQCR3 IOMEM(0xe6180244)
#define IRQCR4 IOMEM(0xe6180248)
#define PDNSEL IOMEM(0xe6180254)
/* INTC */
#define ICR1A 0xe6900000
#define ICR2A 0xe6900004
#define ICR3A 0xe6900008
#define ICR4A 0xe690000c
#define INTMSK00A 0xe6900040
#define INTMSK10A 0xe6900044
#define INTMSK20A 0xe6900048
#define INTMSK30A 0xe690004c
#define ICR1A IOMEM(0xe6900000)
#define ICR2A IOMEM(0xe6900004)
#define ICR3A IOMEM(0xe6900008)
#define ICR4A IOMEM(0xe690000c)
#define INTMSK00A IOMEM(0xe6900040)
#define INTMSK10A IOMEM(0xe6900044)
#define INTMSK20A IOMEM(0xe6900048)
#define INTMSK30A IOMEM(0xe690004c)
/* MFIS */
/* FIXME: pointing where? */
#define SMFRAM 0xe6a70000
/* AP-System Core */
#define APARMBAREA 0xe6f10020
#define APARMBAREA IOMEM(0xe6f10020)
#ifdef CONFIG_PM

2
arch/arm/mach-shmobile/setup-sh7367.c
View File

@ -462,7 +462,7 @@ static void __init sh7367_earlytimer_init(void)
shmobile_earlytimer_init();
}
#define SYMSTPCR2 0xe6158048
#define SYMSTPCR2 IOMEM(0xe6158048)
#define SYMSTPCR2_CMT1 (1 << 29)
void __init sh7367_add_early_devices(void)

2
arch/arm/mach-shmobile/setup-sh7377.c
View File

@ -484,7 +484,7 @@ static void __init sh7377_earlytimer_init(void)
shmobile_earlytimer_init();
}
#define SMSTPCR3 0xe615013c
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR3_CMT1 (1 << 29)
void __init sh7377_add_early_devices(void)

2
arch/arm/mach-shmobile/setup-sh73a0.c
View File

@ -759,7 +759,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
&mpdma0_device,
};
#define SRCR2 0xe61580b0
#define SRCR2 IOMEM(0xe61580b0)
void __init sh73a0_add_standard_devices(void)
{

14
arch/arm/mach-spear13xx/include/mach/spear.h
View File

@ -17,26 +17,26 @@
#include <asm/memory.h>
#define PERIP_GRP2_BASE UL(0xB3000000)
#define VA_PERIP_GRP2_BASE UL(0xFE000000)
#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
#define MCIF_SDHCI_BASE UL(0xB3000000)
#define SYSRAM0_BASE UL(0xB3800000)
#define VA_SYSRAM0_BASE UL(0xFE800000)
#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
#define PERIP_GRP1_BASE UL(0xE0000000)
#define VA_PERIP_GRP1_BASE UL(0xFD000000)
#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000)
#define UART_BASE UL(0xE0000000)
#define VA_UART_BASE UL(0xFD000000)
#define VA_UART_BASE IOMEM(0xFD000000)
#define SSP_BASE UL(0xE0100000)
#define MISC_BASE UL(0xE0700000)
#define VA_MISC_BASE IOMEM(UL(0xFD700000))
#define VA_MISC_BASE IOMEM(0xFD700000)
#define A9SM_AND_MPMC_BASE UL(0xEC000000)
#define VA_A9SM_AND_MPMC_BASE UL(0xFC000000)
#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000)
/* A9SM peripheral offsets */
#define A9SM_PERIP_BASE UL(0xEC800000)
#define VA_A9SM_PERIP_BASE UL(0xFC800000)
#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000)
#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00)
#define L2CC_BASE UL(0xED000000)

6
arch/arm/mach-spear13xx/spear13xx.c
View File

@ -114,17 +114,17 @@ void __init spear13xx_l2x0_init(void)
*/
struct map_desc spear13xx_io_desc[] __initdata = {
{
.virtual = VA_PERIP_GRP2_BASE,
.virtual = (unsigned long)VA_PERIP_GRP2_BASE,
.pfn = __phys_to_pfn(PERIP_GRP2_BASE),
.length = SZ_16M,
.type = MT_DEVICE
}, {
.virtual = VA_PERIP_GRP1_BASE,
.virtual = (unsigned long)VA_PERIP_GRP1_BASE,
.pfn = __phys_to_pfn(PERIP_GRP1_BASE),
.length = SZ_16M,
.type = MT_DEVICE
}, {
.virtual = VA_A9SM_AND_MPMC_BASE,
.virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE,
.pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
.length = SZ_16M,
.type = MT_DEVICE

6
arch/arm/plat-mxc/include/mach/mx31.h
View File

@ -76,7 +76,7 @@
#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
#define MX31_ROMP_BASE_ADDR 0x60000000
#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
#define MX31_ROMP_SIZE SZ_1M
#define MX31_AVIC_BASE_ADDR 0x68000000
@ -92,11 +92,11 @@
#define MX31_CS3_BASE_ADDR 0xb2000000
#define MX31_CS4_BASE_ADDR 0xb4000000
#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000
#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
#define MX31_CS4_SIZE SZ_32M
#define MX31_CS5_BASE_ADDR 0xb6000000
#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000
#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
#define MX31_CS5_SIZE SZ_32M
#define MX31_X_MEMC_BASE_ADDR 0xb8000000

4
arch/arm/plat-samsung/s5p-irq-gpioint.c
View File

@ -24,7 +24,7 @@
#include <asm/mach/irq.h>
#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
#define CON_OFFSET 0x700
#define MASK_OFFSET 0x900
@ -153,7 +153,7 @@ static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
bank->chips[group - bank->start] = chip;
gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
(void __iomem *)GPIO_BASE(chip),
GPIO_BASE(chip),
handle_level_irq);
if (!gc)
return -ENOMEM;

2
drivers/input/mouse/rpcmouse.c
View File

@ -42,7 +42,7 @@ static irqreturn_t rpcmouse_irq(int irq, void *dev_id)
x = (short) iomd_readl(IOMD_MOUSEX);
y = (short) iomd_readl(IOMD_MOUSEY);
b = (short) (__raw_readl(0xe0310000) ^ 0x70);
b = (short) (__raw_readl(IOMEM(0xe0310000)) ^ 0x70);
dx = x - rpcmouse_lastx;
dy = y - rpcmouse_lasty;

4
drivers/net/ethernet/seeq/ether3.c
View File

@ -99,13 +99,13 @@ typedef enum {
* The SEEQ8005 doesn't like us writing to its registers
* too quickly.
*/
static inline void ether3_outb(int v, const void __iomem *r)
static inline void ether3_outb(int v, void __iomem *r)
{
writeb(v, r);
udelay(1);
}
static inline void ether3_outw(int v, const void __iomem *r)
static inline void ether3_outw(int v, void __iomem *r)
{
writew(v, r);
udelay(1);

2
drivers/scsi/arm/eesox.c
View File

@ -273,7 +273,7 @@ static void eesoxscsi_buffer_out(void *buf, int length, void __iomem *base)
{
const void __iomem *reg_fas = base + EESOX_FAS216_OFFSET;
const void __iomem *reg_dmastat = base + EESOX_DMASTAT;
const void __iomem *reg_dmadata = base + EESOX_DMADATA;
void __iomem *reg_dmadata = base + EESOX_DMADATA;
do {
unsigned int status;

4
drivers/tty/serial/serial_ks8695.c
View File

@ -548,8 +548,8 @@ static struct uart_ops ks8695uart_pops = {
static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
{
.membase = (void *) KS8695_UART_VA,
.mapbase = KS8695_UART_VA,
.membase = KS8695_UART_VA,
.mapbase = KS8695_UART_PA,
.iotype = SERIAL_IO_MEM,
.irq = KS8695_IRQ_UART_TX,
.uartclk = KS8695_CLOCK_RATE * 16,

8
drivers/video/da8xx-fb.c
View File

@ -131,7 +131,7 @@
#define UPPER_MARGIN 32
#define LOWER_MARGIN 32
static resource_size_t da8xx_fb_reg_base;
static void __iomem *da8xx_fb_reg_base;
static struct resource *lcdc_regs;
static unsigned int lcd_revision;
static irq_handler_t lcdc_irq_handler;
@ -951,7 +951,7 @@ static int __devexit fb_remove(struct platform_device *dev)
clk_disable(par->lcdc_clk);
clk_put(par->lcdc_clk);
framebuffer_release(info);
iounmap((void __iomem *)da8xx_fb_reg_base);
iounmap(da8xx_fb_reg_base);
release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
}
@ -1171,7 +1171,7 @@ static int __devinit fb_probe(struct platform_device *device)
if (!lcdc_regs)
return -EBUSY;
da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
da8xx_fb_reg_base = ioremap(lcdc_regs->start, len);
if (!da8xx_fb_reg_base) {
ret = -EBUSY;
goto err_request_mem;
@ -1392,7 +1392,7 @@ err_clk_put:
clk_put(fb_clk);
err_ioremap:
iounmap((void __iomem *)da8xx_fb_reg_base);
iounmap(da8xx_fb_reg_base);
err_request_mem:
release_mem_region(lcdc_regs->start, len);