forked from Minki/linux
This pull request brings in VEC (TV-out) support for vc4, along with a
pageflipping race fix. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE/JuuFDWp9/ZkuCBXtdYpNtH8nugFAlhLP/4ACgkQtdYpNtH8 nug5xA//T7E/tpDkKVsd/sP7OTVgxktUpBERNDr0oJi4f7i2zUswfH+3VzqO+a8J 5aQ2i2hdP0cST9c5/TJN95uL3nzyNhmbDV1J8ZAVMDxTYwuf1Nbx6+EYtSVtQqb9 pGLP5KkfoBMZpQGX8TbaXynoFPutff+SgE2O31ptZxqq80g/jERWBLal+6OWAi/O lLRorWyxF4Fqrfs/lt0q637FLOCKRSHdvlIl9njD47aBlLQBUxVR+Q7/cu/ZLgCo 0TlqzMlFROl+AR1G+hAys60H+qBJM7NB64earzMu0AfPw9nWV+y7lvr1PTv2JvKM fXTqn1vzyFEwREo7nKdmtJzVDffP2NHyvvdUE7NOiY8yffKT/xBfR0THGvIQs+MY U3rOrsuws+PWUDFEsJjuHZXynwOUULs1VkOt3kovndaJsjGLK6Zd1Y6vaVsEA1wF 1217c7j2rK2OS354coG7srUf8CU9QkwOS60l1RRdMRJuQ5K39gYHT/UuTeEq57Q5 R4XcV9CkJMeuq04waxsqZaAydSMq6El0S4oftynK/7IIZwQNAcc29i6zdFuq4XuW +XPrkUW9Fp1PchnfTD1uohSq0+h4vEO0iseK47sHnkYEY696fpxnTzwV66omIYzm aLTPLv6JuL4bzA3hn9AHRhN7y8Mh+Sn8bbx+Z9nKqNlT8M/acwY= =Sh9P -----END PGP SIGNATURE----- Merge tag 'drm-vc4-next-2016-12-09' of https://github.com/anholt/linux into drm-next This pull request brings in VEC (TV-out) support for vc4, along with a pageflipping race fix. * tag 'drm-vc4-next-2016-12-09' of https://github.com/anholt/linux: drm/vc4: Don't use drm_put_dev drm/vc4: Document VEC DT binding drm/vc4: Add support for the VEC (Video Encoder) IP drm: Add TV connector states to drm_connector_state drm: Turn DRM_MODE_SUBCONNECTOR_xx definitions into an enum drm/vc4: Fix ->clock_select setting for the VEC encoder drm/vc4: Fix race between page flip completion event and clean-up
This commit is contained in:
Dave Airlie
commit
2601a15d5d
@ -43,6 +43,13 @@ Required properties for DPI:
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- port: Port node with a single endpoint connecting to the panel
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device, as defined in [1]
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Required properties for VEC:
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- compatible: Should be "brcm,bcm2835-vec"
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- reg: Physical base address and length of the registers
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- clocks: The core clock the unit runs on
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- interrupts: The interrupt number
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See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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Required properties for V3D:
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- compatible: Should be "brcm,bcm2835-v3d"
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- reg: Physical base address and length of the V3D's registers
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@ -92,6 +99,13 @@ dpi: dpi@7e208000 {
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};
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};
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vec: vec@7e806000 {
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compatible = "brcm,bcm2835-vec";
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reg = <0x7e806000 0x1000>;
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clocks = <&clocks BCM2835_CLOCK_VEC>;
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interrupts = <2 27>;
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};
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v3d: v3d@7ec00000 {
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compatible = "brcm,bcm2835-v3d";
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reg = <0x7ec00000 0x1000>;
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@ -1087,12 +1087,38 @@ int drm_atomic_connector_set_property(struct drm_connector *connector,
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* now?) atomic writes to DPMS property:
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*/
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return -EINVAL;
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} else if (property == config->tv_select_subconnector_property) {
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state->tv.subconnector = val;
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} else if (property == config->tv_left_margin_property) {
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state->tv.margins.left = val;
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} else if (property == config->tv_right_margin_property) {
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state->tv.margins.right = val;
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} else if (property == config->tv_top_margin_property) {
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state->tv.margins.top = val;
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} else if (property == config->tv_bottom_margin_property) {
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state->tv.margins.bottom = val;
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} else if (property == config->tv_mode_property) {
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state->tv.mode = val;
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} else if (property == config->tv_brightness_property) {
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state->tv.brightness = val;
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} else if (property == config->tv_contrast_property) {
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state->tv.contrast = val;
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} else if (property == config->tv_flicker_reduction_property) {
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state->tv.flicker_reduction = val;
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} else if (property == config->tv_overscan_property) {
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state->tv.overscan = val;
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} else if (property == config->tv_saturation_property) {
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state->tv.saturation = val;
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} else if (property == config->tv_hue_property) {
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state->tv.hue = val;
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} else if (connector->funcs->atomic_set_property) {
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return connector->funcs->atomic_set_property(connector,
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state, property, val);
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} else {
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return -EINVAL;
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}
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return 0;
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}
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EXPORT_SYMBOL(drm_atomic_connector_set_property);
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@ -1135,6 +1161,30 @@ drm_atomic_connector_get_property(struct drm_connector *connector,
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*val = (state->crtc) ? state->crtc->base.id : 0;
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} else if (property == config->dpms_property) {
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*val = connector->dpms;
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} else if (property == config->tv_select_subconnector_property) {
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*val = state->tv.subconnector;
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} else if (property == config->tv_left_margin_property) {
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*val = state->tv.margins.left;
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} else if (property == config->tv_right_margin_property) {
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*val = state->tv.margins.right;
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} else if (property == config->tv_top_margin_property) {
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*val = state->tv.margins.top;
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} else if (property == config->tv_bottom_margin_property) {
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*val = state->tv.margins.bottom;
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} else if (property == config->tv_mode_property) {
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*val = state->tv.mode;
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} else if (property == config->tv_brightness_property) {
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*val = state->tv.brightness;
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} else if (property == config->tv_contrast_property) {
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*val = state->tv.contrast;
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} else if (property == config->tv_flicker_reduction_property) {
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*val = state->tv.flicker_reduction;
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} else if (property == config->tv_overscan_property) {
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*val = state->tv.overscan;
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} else if (property == config->tv_saturation_property) {
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*val = state->tv.saturation;
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} else if (property == config->tv_hue_property) {
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*val = state->tv.hue;
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} else if (connector->funcs->atomic_get_property) {
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return connector->funcs->atomic_get_property(connector,
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state, property, val);
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@ -11,6 +11,7 @@ vc4-y := \
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vc4_kms.o \
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vc4_gem.o \
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vc4_hdmi.o \
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vc4_vec.o \
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vc4_hvs.o \
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vc4_irq.o \
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vc4_plane.o \
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@ -83,8 +83,7 @@ struct vc4_crtc_data {
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/* Which channel of the HVS this pixelvalve sources from. */
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int hvs_channel;
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enum vc4_encoder_type encoder0_type;
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enum vc4_encoder_type encoder1_type;
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enum vc4_encoder_type encoder_types[4];
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};
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#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
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@ -669,6 +668,14 @@ void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
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CRTC_WRITE(PV_INTEN, 0);
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}
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/* Must be called with the event lock held */
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bool vc4_event_pending(struct drm_crtc *crtc)
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{
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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return !!vc4_crtc->event;
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}
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static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
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{
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struct drm_crtc *crtc = &vc4_crtc->base;
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@ -859,20 +866,26 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
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static const struct vc4_crtc_data pv0_data = {
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.hvs_channel = 0,
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.encoder0_type = VC4_ENCODER_TYPE_DSI0,
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.encoder1_type = VC4_ENCODER_TYPE_DPI,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
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},
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};
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static const struct vc4_crtc_data pv1_data = {
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.hvs_channel = 2,
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.encoder0_type = VC4_ENCODER_TYPE_DSI1,
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.encoder1_type = VC4_ENCODER_TYPE_SMI,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
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},
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};
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static const struct vc4_crtc_data pv2_data = {
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.hvs_channel = 1,
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.encoder0_type = VC4_ENCODER_TYPE_VEC,
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.encoder1_type = VC4_ENCODER_TYPE_HDMI,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
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[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
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},
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};
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static const struct of_device_id vc4_crtc_dt_match[] = {
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@ -886,17 +899,20 @@ static void vc4_set_crtc_possible_masks(struct drm_device *drm,
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struct drm_crtc *crtc)
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{
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
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const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
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struct drm_encoder *encoder;
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drm_for_each_encoder(encoder, drm) {
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struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
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int i;
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if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
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vc4_encoder->clock_select = 0;
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encoder->possible_crtcs |= drm_crtc_mask(crtc);
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} else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
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vc4_encoder->clock_select = 1;
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for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
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if (vc4_encoder->type == encoder_types[i]) {
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vc4_encoder->clock_select = i;
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encoder->possible_crtcs |= drm_crtc_mask(crtc);
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break;
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}
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}
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}
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}
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@ -19,6 +19,7 @@ static const struct drm_info_list vc4_debugfs_list[] = {
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{"bo_stats", vc4_bo_stats_debugfs, 0},
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{"dpi_regs", vc4_dpi_debugfs_regs, 0},
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{"hdmi_regs", vc4_hdmi_debugfs_regs, 0},
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{"vec_regs", vc4_vec_debugfs_regs, 0},
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{"hvs_regs", vc4_hvs_debugfs_regs, 0},
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{"crtc0_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)0},
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{"crtc1_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)1},
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@ -277,12 +277,14 @@ static void vc4_drm_unbind(struct device *dev)
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struct drm_device *drm = platform_get_drvdata(pdev);
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struct vc4_dev *vc4 = to_vc4_dev(drm);
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drm_dev_unregister(drm);
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if (vc4->fbdev)
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drm_fbdev_cma_fini(vc4->fbdev);
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drm_mode_config_cleanup(drm);
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drm_put_dev(drm);
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drm_dev_unref(drm);
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}
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static const struct component_master_ops vc4_drm_ops = {
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@ -292,6 +294,7 @@ static const struct component_master_ops vc4_drm_ops = {
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static struct platform_driver *const component_drivers[] = {
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&vc4_hdmi_driver,
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&vc4_vec_driver,
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&vc4_dpi_driver,
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&vc4_hvs_driver,
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&vc4_crtc_driver,
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@ -17,6 +17,7 @@ struct vc4_dev {
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struct vc4_crtc *crtc[3];
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struct vc4_v3d *v3d;
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struct vc4_dpi *dpi;
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struct vc4_vec *vec;
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struct drm_fbdev_cma *fbdev;
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@ -194,6 +195,7 @@ to_vc4_plane(struct drm_plane *plane)
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}
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enum vc4_encoder_type {
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VC4_ENCODER_TYPE_NONE,
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VC4_ENCODER_TYPE_HDMI,
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VC4_ENCODER_TYPE_VEC,
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VC4_ENCODER_TYPE_DSI0,
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@ -442,6 +444,7 @@ int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
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extern struct platform_driver vc4_crtc_driver;
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int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
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void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
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bool vc4_event_pending(struct drm_crtc *crtc);
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int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
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int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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unsigned int flags, int *vpos, int *hpos,
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@ -485,6 +488,10 @@ int vc4_queue_seqno_cb(struct drm_device *dev,
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extern struct platform_driver vc4_hdmi_driver;
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int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
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/* vc4_hdmi.c */
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extern struct platform_driver vc4_vec_driver;
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int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
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/* vc4_irq.c */
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irqreturn_t vc4_irq(int irq, void *arg);
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void vc4_irq_preinstall(struct drm_device *dev);
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@ -119,18 +119,35 @@ static int vc4_atomic_commit(struct drm_device *dev,
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/* Make sure that any outstanding modesets have finished. */
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if (nonblock) {
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ret = down_trylock(&vc4->async_modeset);
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if (ret) {
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struct drm_crtc *crtc;
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struct drm_crtc_state *crtc_state;
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unsigned long flags;
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bool busy = false;
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/*
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* If there's an undispatched event to send then we're
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* obviously still busy. If there isn't, then we can
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* unconditionally wait for the semaphore because it
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* shouldn't be contended (for long).
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*
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* This is to prevent a race where queuing a new flip
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* from userspace immediately on receipt of an event
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* beats our clean-up and returns EBUSY.
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*/
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spin_lock_irqsave(&dev->event_lock, flags);
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for_each_crtc_in_state(state, crtc, crtc_state, i)
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busy |= vc4_event_pending(crtc);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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if (busy) {
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kfree(c);
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return -EBUSY;
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}
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} else {
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}
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ret = down_interruptible(&vc4->async_modeset);
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if (ret) {
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kfree(c);
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return ret;
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}
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}
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ret = drm_atomic_helper_prepare_planes(dev, state);
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if (ret) {
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@ -177,8 +177,9 @@
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# define PV_CONTROL_WAIT_HSTART BIT(12)
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# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
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# define PV_CONTROL_PIXEL_REP_SHIFT 4
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# define PV_CONTROL_CLK_SELECT_DSI_VEC 0
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# define PV_CONTROL_CLK_SELECT_DSI 0
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# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
|
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# define PV_CONTROL_CLK_SELECT_VEC 2
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# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
|
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# define PV_CONTROL_CLK_SELECT_SHIFT 2
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# define PV_CONTROL_FIFO_CLR BIT(1)
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657
drivers/gpu/drm/vc4/vc4_vec.c
Normal file
657
drivers/gpu/drm/vc4/vc4_vec.c
Normal file
@ -0,0 +1,657 @@
|
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/*
|
||||
* Copyright (C) 2016 Broadcom
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* DOC: VC4 SDTV module
|
||||
*/
|
||||
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
#include <drm/drm_edid.h>
|
||||
#include <drm/drm_panel.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/component.h>
|
||||
#include <linux/of_graph.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include "vc4_drv.h"
|
||||
#include "vc4_regs.h"
|
||||
|
||||
/* WSE Registers */
|
||||
#define VEC_WSE_RESET 0xc0
|
||||
|
||||
#define VEC_WSE_CONTROL 0xc4
|
||||
#define VEC_WSE_WSS_ENABLE BIT(7)
|
||||
|
||||
#define VEC_WSE_WSS_DATA 0xc8
|
||||
#define VEC_WSE_VPS_DATA1 0xcc
|
||||
#define VEC_WSE_VPS_CONTROL 0xd0
|
||||
|
||||
/* VEC Registers */
|
||||
#define VEC_REVID 0x100
|
||||
|
||||
#define VEC_CONFIG0 0x104
|
||||
#define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26)
|
||||
#define VEC_CONFIG0_YDEL(x) ((x) << 26)
|
||||
#define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24)
|
||||
#define VEC_CONFIG0_CDEL(x) ((x) << 24)
|
||||
#define VEC_CONFIG0_PBPR_FIL BIT(18)
|
||||
#define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16)
|
||||
#define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16)
|
||||
#define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16)
|
||||
#define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16)
|
||||
#define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16)
|
||||
#define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13)
|
||||
#define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13)
|
||||
#define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13)
|
||||
#define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13)
|
||||
#define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13)
|
||||
#define VEC_CONFIG0_CHRBW1 BIT(11)
|
||||
#define VEC_CONFIG0_CHRBW0 BIT(10)
|
||||
#define VEC_CONFIG0_SYNCDIS BIT(9)
|
||||
#define VEC_CONFIG0_BURDIS BIT(8)
|
||||
#define VEC_CONFIG0_CHRDIS BIT(7)
|
||||
#define VEC_CONFIG0_PDEN BIT(6)
|
||||
#define VEC_CONFIG0_YCDELAY BIT(4)
|
||||
#define VEC_CONFIG0_RAMPEN BIT(2)
|
||||
#define VEC_CONFIG0_YCDIS BIT(2)
|
||||
#define VEC_CONFIG0_STD_MASK GENMASK(1, 0)
|
||||
#define VEC_CONFIG0_NTSC_STD 0
|
||||
#define VEC_CONFIG0_PAL_BDGHI_STD 1
|
||||
#define VEC_CONFIG0_PAL_N_STD 3
|
||||
|
||||
#define VEC_SCHPH 0x108
|
||||
#define VEC_SOFT_RESET 0x10c
|
||||
#define VEC_CLMP0_START 0x144
|
||||
#define VEC_CLMP0_END 0x148
|
||||
#define VEC_FREQ3_2 0x180
|
||||
#define VEC_FREQ1_0 0x184
|
||||
|
||||
#define VEC_CONFIG1 0x188
|
||||
#define VEC_CONFIG_VEC_RESYNC_OFF BIT(18)
|
||||
#define VEC_CONFIG_RGB219 BIT(17)
|
||||
#define VEC_CONFIG_CBAR_EN BIT(16)
|
||||
#define VEC_CONFIG_TC_OBB BIT(15)
|
||||
#define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10)
|
||||
#define VEC_CONFIG1_C_Y_CVBS (0 << 10)
|
||||
#define VEC_CONFIG1_CVBS_Y_C (1 << 10)
|
||||
#define VEC_CONFIG1_PR_Y_PB (2 << 10)
|
||||
#define VEC_CONFIG1_RGB (4 << 10)
|
||||
#define VEC_CONFIG1_Y_C_CVBS (5 << 10)
|
||||
#define VEC_CONFIG1_C_CVBS_Y (6 << 10)
|
||||
#define VEC_CONFIG1_C_CVBS_CVBS (7 << 10)
|
||||
#define VEC_CONFIG1_DIS_CHR BIT(9)
|
||||
#define VEC_CONFIG1_DIS_LUMA BIT(8)
|
||||
#define VEC_CONFIG1_YCBCR_IN BIT(6)
|
||||
#define VEC_CONFIG1_DITHER_TYPE_LFSR 0
|
||||
#define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5)
|
||||
#define VEC_CONFIG1_DITHER_EN BIT(4)
|
||||
#define VEC_CONFIG1_CYDELAY BIT(3)
|
||||
#define VEC_CONFIG1_LUMADIS BIT(2)
|
||||
#define VEC_CONFIG1_COMPDIS BIT(1)
|
||||
#define VEC_CONFIG1_CUSTOM_FREQ BIT(0)
|
||||
|
||||
#define VEC_CONFIG2 0x18c
|
||||
#define VEC_CONFIG2_PROG_SCAN BIT(15)
|
||||
#define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12)
|
||||
#define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12)
|
||||
#define VEC_CONFIG2_PBPR_EN BIT(10)
|
||||
#define VEC_CONFIG2_UV_DIG_DIS BIT(6)
|
||||
#define VEC_CONFIG2_RGB_DIG_DIS BIT(5)
|
||||
#define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2)
|
||||
#define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2)
|
||||
#define VEC_CONFIG2_TMUX_RG_COMP (1 << 2)
|
||||
#define VEC_CONFIG2_TMUX_UV_YC (2 << 2)
|
||||
#define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2)
|
||||
|
||||
#define VEC_INTERRUPT_CONTROL 0x190
|
||||
#define VEC_INTERRUPT_STATUS 0x194
|
||||
#define VEC_FCW_SECAM_B 0x198
|
||||
#define VEC_SECAM_GAIN_VAL 0x19c
|
||||
|
||||
#define VEC_CONFIG3 0x1a0
|
||||
#define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0)
|
||||
#define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0)
|
||||
#define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1)
|
||||
|
||||
#define VEC_STATUS0 0x200
|
||||
#define VEC_MASK0 0x204
|
||||
|
||||
#define VEC_CFG 0x208
|
||||
#define VEC_CFG_SG_MODE_MASK GENMASK(6, 5)
|
||||
#define VEC_CFG_SG_MODE(x) ((x) << 5)
|
||||
#define VEC_CFG_SG_EN BIT(4)
|
||||
#define VEC_CFG_VEC_EN BIT(3)
|
||||
#define VEC_CFG_MB_EN BIT(2)
|
||||
#define VEC_CFG_ENABLE BIT(1)
|
||||
#define VEC_CFG_TB_EN BIT(0)
|
||||
|
||||
#define VEC_DAC_TEST 0x20c
|
||||
|
||||
#define VEC_DAC_CONFIG 0x210
|
||||
#define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24)
|
||||
#define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16)
|
||||
#define VEC_DAC_CONFIG_DAC_CTRL(x) (x)
|
||||
|
||||
#define VEC_DAC_MISC 0x214
|
||||
#define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16)
|
||||
#define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16)
|
||||
#define VEC_DAC_MISC_VID_ACT BIT(8)
|
||||
#define VEC_DAC_MISC_VCD_PWRDN BIT(6)
|
||||
#define VEC_DAC_MISC_BIAS_PWRDN BIT(5)
|
||||
#define VEC_DAC_MISC_DAC_PWRDN BIT(2)
|
||||
#define VEC_DAC_MISC_LDO_PWRDN BIT(1)
|
||||
#define VEC_DAC_MISC_DAC_RST_N BIT(0)
|
||||
|
||||
|
||||
/* General VEC hardware state. */
|
||||
struct vc4_vec {
|
||||
struct platform_device *pdev;
|
||||
|
||||
struct drm_encoder *encoder;
|
||||
struct drm_connector *connector;
|
||||
|
||||
void __iomem *regs;
|
||||
|
||||
struct clk *clock;
|
||||
|
||||
const struct vc4_vec_tv_mode *tv_mode;
|
||||
};
|
||||
|
||||
#define VEC_READ(offset) readl(vec->regs + (offset))
|
||||
#define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))
|
||||
|
||||
/* VC4 VEC encoder KMS struct */
|
||||
struct vc4_vec_encoder {
|
||||
struct vc4_encoder base;
|
||||
struct vc4_vec *vec;
|
||||
};
|
||||
|
||||
static inline struct vc4_vec_encoder *
|
||||
to_vc4_vec_encoder(struct drm_encoder *encoder)
|
||||
{
|
||||
return container_of(encoder, struct vc4_vec_encoder, base.base);
|
||||
}
|
||||
|
||||
/* VC4 VEC connector KMS struct */
|
||||
struct vc4_vec_connector {
|
||||
struct drm_connector base;
|
||||
struct vc4_vec *vec;
|
||||
|
||||
/* Since the connector is attached to just the one encoder,
|
||||
* this is the reference to it so we can do the best_encoder()
|
||||
* hook.
|
||||
*/
|
||||
struct drm_encoder *encoder;
|
||||
};
|
||||
|
||||
static inline struct vc4_vec_connector *
|
||||
to_vc4_vec_connector(struct drm_connector *connector)
|
||||
{
|
||||
return container_of(connector, struct vc4_vec_connector, base);
|
||||
}
|
||||
|
||||
enum vc4_vec_tv_mode_id {
|
||||
VC4_VEC_TV_MODE_NTSC,
|
||||
VC4_VEC_TV_MODE_NTSC_J,
|
||||
VC4_VEC_TV_MODE_PAL,
|
||||
VC4_VEC_TV_MODE_PAL_M,
|
||||
};
|
||||
|
||||
struct vc4_vec_tv_mode {
|
||||
const struct drm_display_mode *mode;
|
||||
void (*mode_set)(struct vc4_vec *vec);
|
||||
};
|
||||
|
||||
#define VEC_REG(reg) { reg, #reg }
|
||||
static const struct {
|
||||
u32 reg;
|
||||
const char *name;
|
||||
} vec_regs[] = {
|
||||
VEC_REG(VEC_WSE_CONTROL),
|
||||
VEC_REG(VEC_WSE_WSS_DATA),
|
||||
VEC_REG(VEC_WSE_VPS_DATA1),
|
||||
VEC_REG(VEC_WSE_VPS_CONTROL),
|
||||
VEC_REG(VEC_REVID),
|
||||
VEC_REG(VEC_CONFIG0),
|
||||
VEC_REG(VEC_SCHPH),
|
||||
VEC_REG(VEC_CLMP0_START),
|
||||
VEC_REG(VEC_CLMP0_END),
|
||||
VEC_REG(VEC_FREQ3_2),
|
||||
VEC_REG(VEC_FREQ1_0),
|
||||
VEC_REG(VEC_CONFIG1),
|
||||
VEC_REG(VEC_CONFIG2),
|
||||
VEC_REG(VEC_INTERRUPT_CONTROL),
|
||||
VEC_REG(VEC_INTERRUPT_STATUS),
|
||||
VEC_REG(VEC_FCW_SECAM_B),
|
||||
VEC_REG(VEC_SECAM_GAIN_VAL),
|
||||
VEC_REG(VEC_CONFIG3),
|
||||
VEC_REG(VEC_STATUS0),
|
||||
VEC_REG(VEC_MASK0),
|
||||
VEC_REG(VEC_CFG),
|
||||
VEC_REG(VEC_DAC_TEST),
|
||||
VEC_REG(VEC_DAC_CONFIG),
|
||||
VEC_REG(VEC_DAC_MISC),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
int vc4_vec_debugfs_regs(struct seq_file *m, void *unused)
|
||||
{
|
||||
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
||||
struct drm_device *dev = node->minor->dev;
|
||||
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
||||
struct vc4_vec *vec = vc4->vec;
|
||||
int i;
|
||||
|
||||
if (!vec)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(vec_regs); i++) {
|
||||
seq_printf(m, "%s (0x%04x): 0x%08x\n",
|
||||
vec_regs[i].name, vec_regs[i].reg,
|
||||
VEC_READ(vec_regs[i].reg));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void vc4_vec_ntsc_mode_set(struct vc4_vec *vec)
|
||||
{
|
||||
VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN);
|
||||
VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
|
||||
}
|
||||
|
||||
static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec)
|
||||
{
|
||||
VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD);
|
||||
VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
|
||||
}
|
||||
|
||||
static const struct drm_display_mode ntsc_mode = {
|
||||
DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
|
||||
720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
|
||||
480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0,
|
||||
DRM_MODE_FLAG_INTERLACE)
|
||||
};
|
||||
|
||||
static void vc4_vec_pal_mode_set(struct vc4_vec *vec)
|
||||
{
|
||||
VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);
|
||||
VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
|
||||
}
|
||||
|
||||
static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec)
|
||||
{
|
||||
VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);
|
||||
VEC_WRITE(VEC_CONFIG1,
|
||||
VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ);
|
||||
VEC_WRITE(VEC_FREQ3_2, 0x223b);
|
||||
VEC_WRITE(VEC_FREQ1_0, 0x61d1);
|
||||
}
|
||||
|
||||
static const struct drm_display_mode pal_mode = {
|
||||
DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
|
||||
720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
|
||||
576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0,
|
||||
DRM_MODE_FLAG_INTERLACE)
|
||||
};
|
||||
|
||||
static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
|
||||
[VC4_VEC_TV_MODE_NTSC] = {
|
||||
.mode = &ntsc_mode,
|
||||
.mode_set = vc4_vec_ntsc_mode_set,
|
||||
},
|
||||
[VC4_VEC_TV_MODE_NTSC_J] = {
|
||||
.mode = &ntsc_mode,
|
||||
.mode_set = vc4_vec_ntsc_j_mode_set,
|
||||
},
|
||||
[VC4_VEC_TV_MODE_PAL] = {
|
||||
.mode = &pal_mode,
|
||||
.mode_set = vc4_vec_pal_mode_set,
|
||||
},
|
||||
[VC4_VEC_TV_MODE_PAL_M] = {
|
||||
.mode = &pal_mode,
|
||||
.mode_set = vc4_vec_pal_m_mode_set,
|
||||
},
|
||||
};
|
||||
|
||||
static enum drm_connector_status
|
||||
vc4_vec_connector_detect(struct drm_connector *connector, bool force)
|
||||
{
|
||||
return connector_status_unknown;
|
||||
}
|
||||
|
||||
static void vc4_vec_connector_destroy(struct drm_connector *connector)
|
||||
{
|
||||
drm_connector_unregister(connector);
|
||||
drm_connector_cleanup(connector);
|
||||
}
|
||||
|
||||
static int vc4_vec_connector_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_connector_state *state = connector->state;
|
||||
struct drm_display_mode *mode;
|
||||
|
||||
mode = drm_mode_duplicate(connector->dev,
|
||||
vc4_vec_tv_modes[state->tv.mode].mode);
|
||||
if (!mode) {
|
||||
DRM_ERROR("Failed to create a new display mode\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
drm_mode_probed_add(connector, mode);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static const struct drm_connector_funcs vc4_vec_connector_funcs = {
|
||||
.dpms = drm_atomic_helper_connector_dpms,
|
||||
.detect = vc4_vec_connector_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.set_property = drm_atomic_helper_connector_set_property,
|
||||
.destroy = vc4_vec_connector_destroy,
|
||||
.reset = drm_atomic_helper_connector_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
||||
};
|
||||
|
||||
static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {
|
||||
.get_modes = vc4_vec_connector_get_modes,
|
||||
};
|
||||
|
||||
static struct drm_connector *vc4_vec_connector_init(struct drm_device *dev,
|
||||
struct vc4_vec *vec)
|
||||
{
|
||||
struct drm_connector *connector = NULL;
|
||||
struct vc4_vec_connector *vec_connector;
|
||||
|
||||
vec_connector = devm_kzalloc(dev->dev, sizeof(*vec_connector),
|
||||
GFP_KERNEL);
|
||||
if (!vec_connector)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
connector = &vec_connector->base;
|
||||
connector->interlace_allowed = true;
|
||||
|
||||
vec_connector->encoder = vec->encoder;
|
||||
vec_connector->vec = vec;
|
||||
|
||||
drm_connector_init(dev, connector, &vc4_vec_connector_funcs,
|
||||
DRM_MODE_CONNECTOR_Composite);
|
||||
drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);
|
||||
|
||||
drm_object_attach_property(&connector->base,
|
||||
dev->mode_config.tv_mode_property,
|
||||
VC4_VEC_TV_MODE_NTSC);
|
||||
vec->tv_mode = &vc4_vec_tv_modes[VC4_VEC_TV_MODE_NTSC];
|
||||
|
||||
drm_mode_connector_attach_encoder(connector, vec->encoder);
|
||||
|
||||
return connector;
|
||||
}
|
||||
|
||||
static const struct drm_encoder_funcs vc4_vec_encoder_funcs = {
|
||||
.destroy = drm_encoder_cleanup,
|
||||
};
|
||||
|
||||
static void vc4_vec_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
|
||||
struct vc4_vec *vec = vc4_vec_encoder->vec;
|
||||
int ret;
|
||||
|
||||
VEC_WRITE(VEC_CFG, 0);
|
||||
VEC_WRITE(VEC_DAC_MISC,
|
||||
VEC_DAC_MISC_VCD_PWRDN |
|
||||
VEC_DAC_MISC_BIAS_PWRDN |
|
||||
VEC_DAC_MISC_DAC_PWRDN |
|
||||
VEC_DAC_MISC_LDO_PWRDN);
|
||||
|
||||
clk_disable_unprepare(vec->clock);
|
||||
|
||||
ret = pm_runtime_put(&vec->pdev->dev);
|
||||
if (ret < 0) {
|
||||
DRM_ERROR("Failed to release power domain: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void vc4_vec_encoder_enable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
|
||||
struct vc4_vec *vec = vc4_vec_encoder->vec;
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_get_sync(&vec->pdev->dev);
|
||||
if (ret < 0) {
|
||||
DRM_ERROR("Failed to retain power domain: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* We need to set the clock rate each time we enable the encoder
|
||||
* because there's a chance we share the same parent with the HDMI
|
||||
* clock, and both drivers are requesting different rates.
|
||||
* The good news is, these 2 encoders cannot be enabled at the same
|
||||
* time, thus preventing incompatible rate requests.
|
||||
*/
|
||||
ret = clk_set_rate(vec->clock, 108000000);
|
||||
if (ret) {
|
||||
DRM_ERROR("Failed to set clock rate: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(vec->clock);
|
||||
if (ret) {
|
||||
DRM_ERROR("Failed to turn on core clock: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Reset the different blocks */
|
||||
VEC_WRITE(VEC_WSE_RESET, 1);
|
||||
VEC_WRITE(VEC_SOFT_RESET, 1);
|
||||
|
||||
/* Disable the CGSM-A and WSE blocks */
|
||||
VEC_WRITE(VEC_WSE_CONTROL, 0);
|
||||
|
||||
/* Write config common to all modes. */
|
||||
|
||||
/*
|
||||
* Color subcarrier phase: phase = 360 * SCHPH / 256.
|
||||
* 0x28 <=> 39.375 deg.
|
||||
*/
|
||||
VEC_WRITE(VEC_SCHPH, 0x28);
|
||||
|
||||
/*
|
||||
* Reset to default values.
|
||||
*/
|
||||
VEC_WRITE(VEC_CLMP0_START, 0xac);
|
||||
VEC_WRITE(VEC_CLMP0_END, 0xec);
|
||||
VEC_WRITE(VEC_CONFIG2,
|
||||
VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS);
|
||||
VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);
|
||||
VEC_WRITE(VEC_DAC_CONFIG,
|
||||
VEC_DAC_CONFIG_DAC_CTRL(0xc) |
|
||||
VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |
|
||||
VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46));
|
||||
|
||||
/* Mask all interrupts. */
|
||||
VEC_WRITE(VEC_MASK0, 0);
|
||||
|
||||
vec->tv_mode->mode_set(vec);
|
||||
|
||||
VEC_WRITE(VEC_DAC_MISC,
|
||||
VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);
|
||||
VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);
|
||||
}
|
||||
|
||||
|
||||
static bool vc4_vec_encoder_mode_fixup(struct drm_encoder *encoder,
|
||||
const struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static void vc4_vec_encoder_atomic_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
|
||||
struct vc4_vec *vec = vc4_vec_encoder->vec;
|
||||
|
||||
vec->tv_mode = &vc4_vec_tv_modes[conn_state->tv.mode];
|
||||
}
|
||||
|
||||
static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
const struct vc4_vec_tv_mode *vec_mode;
|
||||
|
||||
vec_mode = &vc4_vec_tv_modes[conn_state->tv.mode];
|
||||
|
||||
if (conn_state->crtc &&
|
||||
!drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode))
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {
|
||||
.disable = vc4_vec_encoder_disable,
|
||||
.enable = vc4_vec_encoder_enable,
|
||||
.mode_fixup = vc4_vec_encoder_mode_fixup,
|
||||
.atomic_check = vc4_vec_encoder_atomic_check,
|
||||
.atomic_mode_set = vc4_vec_encoder_atomic_mode_set,
|
||||
};
|
||||
|
||||
static const struct of_device_id vc4_vec_dt_match[] = {
|
||||
{ .compatible = "brcm,bcm2835-vec", .data = NULL },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const char * const tv_mode_names[] = {
|
||||
[VC4_VEC_TV_MODE_NTSC] = "NTSC",
|
||||
[VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J",
|
||||
[VC4_VEC_TV_MODE_PAL] = "PAL",
|
||||
[VC4_VEC_TV_MODE_PAL_M] = "PAL-M",
|
||||
};
|
||||
|
||||
static int vc4_vec_bind(struct device *dev, struct device *master, void *data)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct drm_device *drm = dev_get_drvdata(master);
|
||||
struct vc4_dev *vc4 = to_vc4_dev(drm);
|
||||
struct vc4_vec *vec;
|
||||
struct vc4_vec_encoder *vc4_vec_encoder;
|
||||
int ret;
|
||||
|
||||
ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names),
|
||||
tv_mode_names);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
vec = devm_kzalloc(dev, sizeof(*vec), GFP_KERNEL);
|
||||
if (!vec)
|
||||
return -ENOMEM;
|
||||
|
||||
vc4_vec_encoder = devm_kzalloc(dev, sizeof(*vc4_vec_encoder),
|
||||
GFP_KERNEL);
|
||||
if (!vc4_vec_encoder)
|
||||
return -ENOMEM;
|
||||
vc4_vec_encoder->base.type = VC4_ENCODER_TYPE_VEC;
|
||||
vc4_vec_encoder->vec = vec;
|
||||
vec->encoder = &vc4_vec_encoder->base.base;
|
||||
|
||||
vec->pdev = pdev;
|
||||
vec->regs = vc4_ioremap_regs(pdev, 0);
|
||||
if (IS_ERR(vec->regs))
|
||||
return PTR_ERR(vec->regs);
|
||||
|
||||
vec->clock = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(vec->clock)) {
|
||||
ret = PTR_ERR(vec->clock);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
DRM_ERROR("Failed to get clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
drm_encoder_init(drm, vec->encoder, &vc4_vec_encoder_funcs,
|
||||
DRM_MODE_ENCODER_TVDAC, NULL);
|
||||
drm_encoder_helper_add(vec->encoder, &vc4_vec_encoder_helper_funcs);
|
||||
|
||||
vec->connector = vc4_vec_connector_init(drm, vec);
|
||||
if (IS_ERR(vec->connector)) {
|
||||
ret = PTR_ERR(vec->connector);
|
||||
goto err_destroy_encoder;
|
||||
}
|
||||
|
||||
dev_set_drvdata(dev, vec);
|
||||
|
||||
vc4->vec = vec;
|
||||
|
||||
return 0;
|
||||
|
||||
err_destroy_encoder:
|
||||
drm_encoder_cleanup(vec->encoder);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void vc4_vec_unbind(struct device *dev, struct device *master,
|
||||
void *data)
|
||||
{
|
||||
struct drm_device *drm = dev_get_drvdata(master);
|
||||
struct vc4_dev *vc4 = to_vc4_dev(drm);
|
||||
struct vc4_vec *vec = dev_get_drvdata(dev);
|
||||
|
||||
vc4_vec_connector_destroy(vec->connector);
|
||||
drm_encoder_cleanup(vec->encoder);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
vc4->vec = NULL;
|
||||
}
|
||||
|
||||
static const struct component_ops vc4_vec_ops = {
|
||||
.bind = vc4_vec_bind,
|
||||
.unbind = vc4_vec_unbind,
|
||||
};
|
||||
|
||||
static int vc4_vec_dev_probe(struct platform_device *pdev)
|
||||
{
|
||||
return component_add(&pdev->dev, &vc4_vec_ops);
|
||||
}
|
||||
|
||||
static int vc4_vec_dev_remove(struct platform_device *pdev)
|
||||
{
|
||||
component_del(&pdev->dev, &vc4_vec_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct platform_driver vc4_vec_driver = {
|
||||
.probe = vc4_vec_dev_probe,
|
||||
.remove = vc4_vec_dev_remove,
|
||||
.driver = {
|
||||
.name = "vc4_vec",
|
||||
.of_match_table = vc4_vec_dt_match,
|
||||
},
|
||||
};
|
||||
@ -194,11 +194,41 @@ int drm_display_info_set_bus_formats(struct drm_display_info *info,
|
||||
const u32 *formats,
|
||||
unsigned int num_formats);
|
||||
|
||||
/**
|
||||
* struct drm_tv_connector_state - TV connector related states
|
||||
* @subconnector: selected subconnector
|
||||
* @margins: left/right/top/bottom margins
|
||||
* @mode: TV mode
|
||||
* @brightness: brightness in percent
|
||||
* @contrast: contrast in percent
|
||||
* @flicker_reduction: flicker reduction in percent
|
||||
* @overscan: overscan in percent
|
||||
* @saturation: saturation in percent
|
||||
* @hue: hue in percent
|
||||
*/
|
||||
struct drm_tv_connector_state {
|
||||
enum drm_mode_subconnector subconnector;
|
||||
struct {
|
||||
unsigned int left;
|
||||
unsigned int right;
|
||||
unsigned int top;
|
||||
unsigned int bottom;
|
||||
} margins;
|
||||
unsigned int mode;
|
||||
unsigned int brightness;
|
||||
unsigned int contrast;
|
||||
unsigned int flicker_reduction;
|
||||
unsigned int overscan;
|
||||
unsigned int saturation;
|
||||
unsigned int hue;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_connector_state - mutable connector state
|
||||
* @connector: backpointer to the connector
|
||||
* @best_encoder: can be used by helpers and drivers to select the encoder
|
||||
* @state: backpointer to global drm_atomic_state
|
||||
* @tv: TV connector state
|
||||
*/
|
||||
struct drm_connector_state {
|
||||
struct drm_connector *connector;
|
||||
@ -214,6 +244,8 @@ struct drm_connector_state {
|
||||
struct drm_encoder *best_encoder;
|
||||
|
||||
struct drm_atomic_state *state;
|
||||
|
||||
struct drm_tv_connector_state tv;
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@ -236,14 +236,16 @@ struct drm_mode_get_encoder {
|
||||
|
||||
/* This is for connectors with multiple signal types. */
|
||||
/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
|
||||
#define DRM_MODE_SUBCONNECTOR_Automatic 0
|
||||
#define DRM_MODE_SUBCONNECTOR_Unknown 0
|
||||
#define DRM_MODE_SUBCONNECTOR_DVID 3
|
||||
#define DRM_MODE_SUBCONNECTOR_DVIA 4
|
||||
#define DRM_MODE_SUBCONNECTOR_Composite 5
|
||||
#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
|
||||
#define DRM_MODE_SUBCONNECTOR_Component 8
|
||||
#define DRM_MODE_SUBCONNECTOR_SCART 9
|
||||
enum drm_mode_subconnector {
|
||||
DRM_MODE_SUBCONNECTOR_Automatic = 0,
|
||||
DRM_MODE_SUBCONNECTOR_Unknown = 0,
|
||||
DRM_MODE_SUBCONNECTOR_DVID = 3,
|
||||
DRM_MODE_SUBCONNECTOR_DVIA = 4,
|
||||
DRM_MODE_SUBCONNECTOR_Composite = 5,
|
||||
DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
|
||||
DRM_MODE_SUBCONNECTOR_Component = 8,
|
||||
DRM_MODE_SUBCONNECTOR_SCART = 9,
|
||||
};
|
||||
|
||||
#define DRM_MODE_CONNECTOR_Unknown 0
|
||||
#define DRM_MODE_CONNECTOR_VGA 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user