From 4a92b6d75bab5dab83d59f393f01b7f4ded5d07c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 1 Feb 2018 10:00:55 +0530 Subject: [PATCH 01/10] arm64: dts: msm8996: Fix wrong use of GIC_CPU_MASK_SIMPLE() GICv3 does not have affinity bitmap in the binding for PPI interrupts. It can be specified using a 4th cell if needed as documented in the bindings. Clean up the wrong use of the affinity bitmap using the GIC_CPU_MASK_SIMPLE() macro Reported-by: Stephen Boyd Signed-off-by: Rajendra Nayak Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4b2afcc4fdf4..07bd89978117 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -232,10 +232,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; clocks { From d0bf04acd12f5c702ac2b21dca6729a1de1308a7 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Mon, 5 Feb 2018 16:46:48 +0200 Subject: [PATCH 02/10] arm64: dts: qcom: msm8916: Add msm8916 A53 PLL DT node Add a device tree node for the A53 PLL, which exists on msm8916 platforms. Signed-off-by: Georgi Djakov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e51b04900726..d3592b19cfc9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -326,6 +326,12 @@ status = "disabled"; }; + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + apcs: syscon@b011000 { compatible = "syscon"; reg = <0x0b011000 0x1000>; From 05e1632f62fe8da662c517cc11ff810df4a3dcab Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Mon, 5 Feb 2018 16:46:49 +0200 Subject: [PATCH 03/10] arm64: dts: qcom: msm8916: Probe the APCS mailbox driver The APCS block was exposed until now as a syscon, but now we have a proper driver for this block. Add the compatible string of the new driver to probe and register the mailbox functionality. Signed-off-by: Georgi Djakov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d3592b19cfc9..5414f53a0fa1 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -332,9 +332,10 @@ #clock-cells = <0>; }; - apcs: syscon@b011000 { - compatible = "syscon"; - reg = <0x0b011000 0x1000>; + apcs: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; + reg = <0xb011000 0x1000>; + #mbox-cells = <1>; }; blsp1_uart2: serial@78b0000 { From 025b995f47daece7b9856b9509748db02a0971be Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Mon, 5 Feb 2018 16:46:50 +0200 Subject: [PATCH 04/10] arm64: dts: qcom: msm8916: Add clock properties to the APCS node There are clock controller registers in the APCS block, which purpose is to control the main CPU mux and divider. Add the clock properties as part of the APCS device-tree node. Signed-off-by: Georgi Djakov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5414f53a0fa1..4539571a36b2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -336,6 +336,8 @@ compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; reg = <0xb011000 0x1000>; #mbox-cells = <1>; + clocks = <&a53pll>; + #clock-cells = <0>; }; blsp1_uart2: serial@78b0000 { From 65afdf458360f65cd4ddb7d165b673feece087a3 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Mon, 5 Feb 2018 16:46:51 +0200 Subject: [PATCH 05/10] arm64: dts: qcom: msm8916: Add CPU frequency scaling support Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms. Signed-off-by: Georgi Djakov Reviewed-by: Amit Kucheria Tested-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4539571a36b2..e4682779eec7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -113,6 +113,8 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; + clocks = <&apcs 0>; + operating-points-v2 = <&cpu_opp_table>; }; CPU1: cpu@1 { @@ -122,6 +124,8 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; + clocks = <&apcs 0>; + operating-points-v2 = <&cpu_opp_table>; }; CPU2: cpu@2 { @@ -131,6 +135,8 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; + clocks = <&apcs 0>; + operating-points-v2 = <&cpu_opp_table>; }; CPU3: cpu@3 { @@ -140,6 +146,8 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; + clocks = <&apcs 0>; + operating-points-v2 = <&cpu_opp_table>; }; L2_0: l2-cache { @@ -212,6 +220,24 @@ }; + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + }; + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + }; + }; + gpu_opp_table: opp_table { compatible = "operating-points-v2"; From 68ae3d0cac449136407fca8dc7ad2078341d67de Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Feb 2018 17:37:24 -0800 Subject: [PATCH 06/10] arm64: dts: msm8996: Add rmtfs sharedmem node A 2MB shared memory region is used on MSM8996 for exchanging sector data in rmtfs. Add this chunk of reserved memory now that we have the rmtfs-mem compatible to describe it and its memory protection properties. Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 07bd89978117..6cf31fe8c220 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -75,6 +75,17 @@ reg = <0x0 0x86200000 0x0 0x2600000>; no-map; }; + + rmtfs@86700000 { + compatible = "qcom,rmtfs-mem"; + + size = <0x0 0x200000>; + alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; }; cpus { From 15ee8f021d9bd64a124829cbe1794491ed070444 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 7 Mar 2018 10:30:02 +0530 Subject: [PATCH 07/10] arm64: dts: msm8916: Add cpu cooling maps Add cpu cooling maps for cpu passive trip points. The cpu cooling device states are mapped to cpufreq based scaling frequencies. Signed-off-by: Rajendra Nayak Signed-off-by: Amit Kucheria Reviewed-by: Viresh Kumar Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e4682779eec7..66b318e1de80 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. MSM8916"; @@ -115,6 +116,7 @@ cpu-idle-states = <&CPU_SPC>; clocks = <&apcs 0>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -126,6 +128,7 @@ cpu-idle-states = <&CPU_SPC>; clocks = <&apcs 0>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -137,6 +140,7 @@ cpu-idle-states = <&CPU_SPC>; clocks = <&apcs 0>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -148,6 +152,7 @@ cpu-idle-states = <&CPU_SPC>; clocks = <&apcs 0>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; L2_0: l2-cache { @@ -196,6 +201,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu-thermal1 { @@ -216,6 +228,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; From 612123af86a4470d59bba5986c24eaa48611575f Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 22 Feb 2018 11:42:05 +0530 Subject: [PATCH 08/10] dt-bindings: arm: Document kryo385 cpu Document the compatible string for the Kryo385 cpus found in qualcomm SoCs. Signed-off-by: Rajendra Nayak Reviewed-by: Rob Herring Reviewed-by: Douglas Anderson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index f4a777039f03..8b0328ff951d 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -185,6 +185,7 @@ described below. "nvidia,tegra186-denver" "qcom,krait" "qcom,kryo" + "qcom,kryo385" "qcom,scorpion" - enable-method Value type: From d46bd5ce1b3936958e2139830642fda46dd61253 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 22 Feb 2018 11:42:06 +0530 Subject: [PATCH 09/10] dt-bindings: qcom: Add SDM845 bindings Add a SoC string 'sdm845' for the qualcomm SDM845 SoC Signed-off-by: Rajendra Nayak Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index 0ed4d39d7fe1..ee532e705d6c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074 + sdm845 The 'board' element must be one of the following strings: From e723795c702b52cfceb3bb3faa63059eb4658313 Mon Sep 17 00:00:00 2001 From: Ilia Lin Date: Tue, 23 Jan 2018 09:36:18 +0200 Subject: [PATCH 10/10] arm64: dts: qcom: Fix SPI5 config on MSM8996 Set correct clocks and interrupt values. Fixes the incorrect SPI master configuration. This is mandatory to make the SPI5 interface functional. Signed-off-by: Ilia Lin Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6cf31fe8c220..f39735be2243 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -508,8 +508,8 @@ blsp2_spi5: spi@75ba000{ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x075ba000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep";