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spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi'

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The ispi->swseq is used for register access. Let's rename it to
swseq_reg to better describe its usage.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
This commit is contained in:
Bin Meng 2017-09-11 02:41:59 -07:00 committed by Cyrille Pitchen
parent 6e995b84ce
commit 2421f1ccbd
1 changed files with 8 additions and 8 deletions
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16
drivers/mtd/spi-nor/intel-spi.c
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@ -126,7 +126,7 @@
* @pr_num: Maximum number of protected range registers * @pr_num: Maximum number of protected range registers
* @writeable: Is the chip writeable * @writeable: Is the chip writeable
* @locked: Is SPI setting locked * @locked: Is SPI setting locked
* @swseq: Use SW sequencer in register reads/writes * @swseq_reg: Use SW sequencer in register reads/writes
* @erase_64k: 64k erase supported * @erase_64k: 64k erase supported
* @opcodes: Opcodes which are supported. This are programmed by BIOS * @opcodes: Opcodes which are supported. This are programmed by BIOS
* before it locks down the controller. * before it locks down the controller.
@ -143,7 +143,7 @@ struct intel_spi {
size_t pr_num; size_t pr_num;
bool writeable; bool writeable;
bool locked; bool locked;
bool swseq; bool swseq_reg;
bool erase_64k; bool erase_64k;
u8 opcodes[8]; u8 opcodes[8];
u8 preopcodes[2]; u8 preopcodes[2];
@ -224,7 +224,7 @@ static void intel_spi_dump_regs(struct intel_spi *ispi)
} }
dev_dbg(ispi->dev, "Using %cW sequencer for register access\n", dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
ispi->swseq ? 'S' : 'H'); ispi->swseq_reg ? 'S' : 'H');
} }
/* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */ /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
@ -297,7 +297,7 @@ static int intel_spi_init(struct intel_spi *ispi)
ispi->pregs = ispi->base + BYT_PR; ispi->pregs = ispi->base + BYT_PR;
ispi->nregions = BYT_FREG_NUM; ispi->nregions = BYT_FREG_NUM;
ispi->pr_num = BYT_PR_NUM; ispi->pr_num = BYT_PR_NUM;
ispi->swseq = true; ispi->swseq_reg = true;
if (writeable) { if (writeable) {
/* Disable write protection */ /* Disable write protection */
@ -318,7 +318,7 @@ static int intel_spi_init(struct intel_spi *ispi)
ispi->pregs = ispi->base + LPT_PR; ispi->pregs = ispi->base + LPT_PR;
ispi->nregions = LPT_FREG_NUM; ispi->nregions = LPT_FREG_NUM;
ispi->pr_num = LPT_PR_NUM; ispi->pr_num = LPT_PR_NUM;
ispi->swseq = true; ispi->swseq_reg = true;
break; break;
case INTEL_SPI_BXT: case INTEL_SPI_BXT:
@ -343,7 +343,7 @@ static int intel_spi_init(struct intel_spi *ispi)
* sequencer. All other operations are supposed to be carried out * sequencer. All other operations are supposed to be carried out
* using software sequencer. * using software sequencer.
*/ */
if (ispi->swseq) { if (ispi->swseq_reg) {
/* Disable #SMI generation from SW sequencer */ /* Disable #SMI generation from SW sequencer */
val = readl(ispi->sregs + SSFSTS_CTL); val = readl(ispi->sregs + SSFSTS_CTL);
val &= ~SSFSTS_CTL_FSMIE; val &= ~SSFSTS_CTL_FSMIE;
@ -493,7 +493,7 @@ static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
/* Address of the first chip */ /* Address of the first chip */
writel(0, ispi->base + FADDR); writel(0, ispi->base + FADDR);
if (ispi->swseq) if (ispi->swseq_reg)
ret = intel_spi_sw_cycle(ispi, opcode, len, ret = intel_spi_sw_cycle(ispi, opcode, len,
OPTYPE_READ_NO_ADDR); OPTYPE_READ_NO_ADDR);
else else
@ -529,7 +529,7 @@ static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
if (ret) if (ret)
return ret; return ret;
if (ispi->swseq) if (ispi->swseq_reg)
return intel_spi_sw_cycle(ispi, opcode, len, return intel_spi_sw_cycle(ispi, opcode, len,
OPTYPE_WRITE_NO_ADDR); OPTYPE_WRITE_NO_ADDR);
return intel_spi_hw_cycle(ispi, opcode, len); return intel_spi_hw_cycle(ispi, opcode, len);