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misc: hpilo: map iLO shared memory by PCI revision id

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Starting from iLO ASIC 'Neches' with subsystem device id 0x00E4,
bar 5 is used for shared memory region mapping instead of bar 2
because bar 2 is made inaccessible after system POST for security
reason.

As this holds true for future iLO ASIC generations, it does not
make sense to map shared memory region according to the subsystem
device id of each following generations.

Map iLO shared memory region with PCI revision id that maps to the
iLO ASIC generation, starting from Neches (Rev 7).

Signed-off-by: Matt Hsiao <matt.hsiao@hpe.com>
Link: https://lore.kernel.org/r/20210531085551.26421-1-matt.hsiao@hpe.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Matt Hsiao 2021-05-31 16:55:51 +08:00 committed by Greg Kroah-Hartman
parent ce52ec5bee
commit 23d51b8181
2 changed files with 12 additions and 1 deletions
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10
drivers/misc/hpilo.c
View File

@ -693,6 +693,8 @@ static int ilo_map_device(struct pci_dev *pdev, struct ilo_hwinfo *hw)
{
int bar;
unsigned long off;
u8 pci_rev_id;
int rc;
/* map the memory mapped i/o registers */
hw->mmio_vaddr = pci_iomap(pdev, 1, 0);
@ -702,7 +704,13 @@ static int ilo_map_device(struct pci_dev *pdev, struct ilo_hwinfo *hw)
}
/* map the adapter shared memory region */
if (pdev->subsystem_device == 0x00E4) {
rc = pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev_id);
if (rc != 0) {
dev_err(&pdev->dev, "Error reading PCI rev id: %d\n", rc);
goto out;
}
if (pci_rev_id >= PCI_REV_ID_NECHES) {
bar = 5;
/* Last 8k is reserved for CCBs */
off = pci_resource_len(pdev, bar) - 0x2000;

3
drivers/misc/hpilo.h
View File

@ -10,6 +10,9 @@
#define ILO_NAME "hpilo"
/* iLO ASIC PCI revision id */
#define PCI_REV_ID_NECHES 7
/* max number of open channel control blocks per device, hw limited to 32 */
#define MAX_CCB 24
/* min number of open channel control blocks per device, hw limited to 32 */