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MIPS: Malta: Make use of generic CM support

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Remove the Malta-specific CM probe code and instead make use of the
newly added generic CM code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6364/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2014-01-15 10:31:54 +00:00 committed by Ralf Baechle
parent 0ee958e102
commit 237036de65
6 changed files with 38 additions and 74 deletions
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3
arch/mips/Kconfig
View File

@ -868,6 +868,7 @@ config CEVT_R4K
bool
config CEVT_GIC
select MIPS_CM
bool
config CEVT_SB1250
@ -886,6 +887,7 @@ config CSRC_R4K
bool
config CSRC_GIC
select MIPS_CM
bool
config CSRC_SB1250
@ -1030,6 +1032,7 @@ config IRQ_GT641XX
bool
config IRQ_GIC
select MIPS_CM
bool
config PCI_GT64XXX_PCI0

5
arch/mips/include/asm/smp-ops.h
View File

@ -13,6 +13,8 @@
#include <linux/errno.h>
#include <asm/mips-cm.h>
#ifdef CONFIG_SMP
#include <linux/cpumask.h>
@ -79,6 +81,9 @@ static inline int register_cmp_smp_ops(void)
#ifdef CONFIG_MIPS_CMP
extern struct plat_smp_ops cmp_smp_ops;
if (!mips_cm_present())
return -ENODEV;
register_smp_ops(&cmp_smp_ops);
return 0;

6
arch/mips/mti-malta/malta-init.c
View File

@ -20,7 +20,7 @@
#include <asm/smp-ops.h>
#include <asm/traps.h>
#include <asm/fw/fw.h>
#include <asm/gcmpregs.h>
#include <asm/mips-cm.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/malta.h>
@ -276,10 +276,10 @@ mips_pci_controller:
console_config();
#endif
/* Early detection of CMP support */
if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ))
mips_cm_probe();
if (!register_cmp_smp_ops())
return;
if (!register_vsmp_smp_ops())
return;

70
arch/mips/mti-malta/malta-int.c
View File

@ -26,6 +26,7 @@
#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/irq_regs.h>
#include <asm/mips-cm.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/gt64120.h>
@ -33,13 +34,10 @@
#include <asm/mips-boards/msc01_pci.h>
#include <asm/msc01_ic.h>
#include <asm/gic.h>
#include <asm/gcmpregs.h>
#include <asm/setup.h>
#include <asm/rtlx.h>
int gcmp_present = -1;
static unsigned long _msc01_biu_base;
static unsigned long _gcmp_base;
static unsigned int ipi_map[NR_CPUS];
static DEFINE_RAW_SPINLOCK(mips_irq_lock);
@ -418,48 +416,6 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
};
#undef X
/*
* GCMP needs to be detected before any SMP initialisation
*/
int __init gcmp_probe(unsigned long addr, unsigned long size)
{
if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) &&
(mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) {
gcmp_present = 0;
pr_debug("GCMP NOT present\n");
return gcmp_present;
}
if (gcmp_present >= 0)
return gcmp_present;
_gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR,
GCMP_ADDRSPACE_SZ);
_msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE,
MSC01_BIU_ADDRSPACE_SZ);
gcmp_present = ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) ==
GCMP_BASE_ADDR);
if (gcmp_present)
pr_debug("GCMP present\n");
return gcmp_present;
}
/* Return the number of IOCU's present */
int __init gcmp_niocu(void)
{
return gcmp_present ? ((GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >>
GCMP_GCB_GC_NUMIOCU_SHF) : 0;
}
/* Set GCMP region attributes */
void __init gcmp_setregion(int region, unsigned long base,
unsigned long mask, int type)
{
GCMPGCBn(CMxBASE, region) = base;
GCMPGCBn(CMxMASK, region) = mask | type;
}
#if defined(CONFIG_MIPS_MT_SMP)
static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
{
@ -496,8 +452,8 @@ void __init arch_init_irq(void)
if (!cpu_has_veic)
mips_cpu_irq_init();
if (gcmp_present) {
GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
if (mips_cm_present()) {
write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
gic_present = 1;
} else {
if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
@ -584,7 +540,7 @@ void __init arch_init_irq(void)
#endif
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
if (!gcmp_present) {
if (!mips_cm_present()) {
/* Enable the GIC */
i = REG(_msc01_biu_base, MSC01_SC_CFG);
REG(_msc01_biu_base, MSC01_SC_CFG) =
@ -708,16 +664,16 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
/* This duplicates the handling in do_be which seems wrong */
int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
if (gcmp_present) {
unsigned long cm_error = GCMPGCB(GCMEC);
unsigned long cm_addr = GCMPGCB(GCMEA);
unsigned long cm_other = GCMPGCB(GCMEO);
if (mips_cm_present()) {
unsigned long cm_error = read_gcr_error_cause();
unsigned long cm_addr = read_gcr_error_addr();
unsigned long cm_other = read_gcr_error_mult();
unsigned long cause, ocause;
char buf[256];
cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK;
if (cause != 0) {
cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
if (cause < 16) {
unsigned long cca_bits = (cm_error >> 15) & 7;
unsigned long tr_bits = (cm_error >> 12) & 7;
@ -748,8 +704,8 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
mcmd[cmd_bits], sport_bits);
}
ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
GCMP_GCB_GMEO_ERROR_2ND_SHF;
ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >>
CM_GCR_ERROR_MULT_ERR2ND_SHF;
pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
causes[cause], buf);
@ -757,7 +713,7 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
/* reprime cause register */
GCMPGCB(GCMEC) = 0;
write_gcr_error_cause(0);
}
}

4
arch/mips/mti-malta/malta-setup.c
View File

@ -26,12 +26,12 @@
#include <linux/time.h>
#include <asm/fw/fw.h>
#include <asm/mips-cm.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/dma.h>
#include <asm/traps.h>
#include <asm/gcmpregs.h>
#ifdef CONFIG_VT
#include <linux/console.h>
#endif
@ -127,7 +127,7 @@ static int __init plat_enable_iocoherency(void)
BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
pr_info("Enabled Bonito IOBC coherency\n");
}
} else if (gcmp_niocu() != 0) {
} else if (mips_cm_numiocu() != 0) {
/* Nothing special needs to be done to enable coherency */
pr_info("CMP IOCU detected\n");
if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {

22
arch/mips/pci/pci-malta.c
View File

@ -27,7 +27,7 @@
#include <linux/init.h>
#include <asm/gt64120.h>
#include <asm/gcmpregs.h>
#include <asm/mips-cm.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/bonito64.h>
#include <asm/mips-boards/msc01_pci.h>
@ -201,11 +201,11 @@ void __init mips_pcibios_init(void)
msc_mem_resource.start = start & mask;
msc_mem_resource.end = (start & mask) | ~mask;
msc_controller.mem_offset = (start & mask) - (map & mask);
#ifdef CONFIG_MIPS_CMP
if (gcmp_niocu())
gcmp_setregion(0, start, mask,
GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
#endif
if (mips_cm_numiocu()) {
write_gcr_reg0_base(start);
write_gcr_reg0_mask(mask |
CM_GCR_REGn_MASK_CMTGT_IOCU0);
}
MSC_READ(MSC01_PCI_SC2PIOBASL, start);
MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
@ -213,11 +213,11 @@ void __init mips_pcibios_init(void)
msc_io_resource.end = (map & mask) | ~mask;
msc_controller.io_offset = 0;
ioport_resource.end = ~mask;
#ifdef CONFIG_MIPS_CMP
if (gcmp_niocu())
gcmp_setregion(1, start, mask,
GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
#endif
if (mips_cm_numiocu()) {
write_gcr_reg1_base(start);
write_gcr_reg1_mask(mask |
CM_GCR_REGn_MASK_CMTGT_IOCU0);
}
/* If ranges overlap I/O takes precedence. */
start = start & mask;
end = start | ~mask;