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[SCSI] qla2xxx: Update firmware-dump procedure for ISP24xx.

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Small changes to register retrieval and order as per latest
firmware specification.

Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
This commit is contained in:
andrew.vasquez@qlogic.com 2006-01-13 17:05:21 -08:00 committed by James Bottomley
parent e978010ceb
commit 210d53507e
2 changed files with 55 additions and 54 deletions
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105
drivers/scsi/qla2xxx/qla_dbg.c
View File

@ -1003,10 +1003,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
fw = (struct qla24xx_fw_dump *) ha->fw_dump24; fw = (struct qla24xx_fw_dump *) ha->fw_dump24;
rval = QLA_SUCCESS; rval = QLA_SUCCESS;
fw->hccr = RD_REG_DWORD(&reg->hccr); fw->host_status = RD_REG_DWORD(&reg->host_status);
/* Pause RISC. */ /* Pause RISC. */
if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) { if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) {
WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET | WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
HCCRX_CLR_HOST_INT); HCCRX_CLR_HOST_INT);
RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
@ -1021,16 +1021,54 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
} }
} }
/* Disable interrupts. */
WRT_REG_DWORD(&reg->ictrl, 0);
RD_REG_DWORD(&reg->ictrl);
if (rval == QLA_SUCCESS) { if (rval == QLA_SUCCESS) {
/* Host interface registers. */ /* Host interface registers. */
dmp_reg = (uint32_t __iomem *)(reg + 0); dmp_reg = (uint32_t __iomem *)(reg + 0);
for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++); fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);
/* Disable interrupts. */
WRT_REG_DWORD(&reg->ictrl, 0);
RD_REG_DWORD(&reg->ictrl);
/* Shadow registers. */
WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
RD_REG_DWORD(&reg->iobase_addr);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0000000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0100000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0200000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0300000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0400000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0500000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0600000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
/* Mailbox registers. */ /* Mailbox registers. */
mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
@ -1308,43 +1346,6 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
for (cnt = 0; cnt < 16; cnt++) for (cnt = 0; cnt < 16; cnt++)
*iter_reg++ = RD_REG_DWORD(dmp_reg++); *iter_reg++ = RD_REG_DWORD(dmp_reg++);
WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
RD_REG_DWORD(&reg->iobase_addr);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0000000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0100000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0200000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0300000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0400000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0500000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
WRT_REG_DWORD(dmp_reg, 0xB0600000);
dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
/* Local memory controller registers. */ /* Local memory controller registers. */
iter_reg = fw->lmc_reg; iter_reg = fw->lmc_reg;
WRT_REG_DWORD(&reg->iobase_addr, 0x3000); WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
@ -1677,7 +1678,7 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
ha->fw_major_version, ha->fw_minor_version, ha->fw_major_version, ha->fw_minor_version,
ha->fw_subminor_version, ha->fw_attributes); ha->fw_subminor_version, ha->fw_attributes);
qla_uprintf(&uiter, "\nHCCR Register\n%04x\n", fw->hccr); qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status);
qla_uprintf(&uiter, "\nHost Interface Registers"); qla_uprintf(&uiter, "\nHost Interface Registers");
for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) { for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
@ -1687,6 +1688,14 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]); qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
} }
qla_uprintf(&uiter, "\n\nShadow Registers");
for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
if (cnt % 8 == 0)
qla_uprintf(&uiter, "\n");
qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
}
qla_uprintf(&uiter, "\n\nMailbox Registers"); qla_uprintf(&uiter, "\n\nMailbox Registers");
for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) { for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
if (cnt % 8 == 0) if (cnt % 8 == 0)
@ -1855,14 +1864,6 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]); qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
} }
qla_uprintf(&uiter, "\n\nShadow Registers");
for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
if (cnt % 8 == 0)
qla_uprintf(&uiter, "\n");
qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
}
qla_uprintf(&uiter, "\n\nLMC Registers"); qla_uprintf(&uiter, "\n\nLMC Registers");
for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) { for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
if (cnt % 8 == 0) if (cnt % 8 == 0)

4
drivers/scsi/qla2xxx/qla_dbg.h
View File

@ -227,8 +227,9 @@ struct qla2100_fw_dump {
#define FW_DUMP_SIZE_24XX 0x2B0000 #define FW_DUMP_SIZE_24XX 0x2B0000
struct qla24xx_fw_dump { struct qla24xx_fw_dump {
uint32_t hccr; uint32_t host_status;
uint32_t host_reg[32]; uint32_t host_reg[32];
uint32_t shadow_reg[7];
uint16_t mailbox_reg[32]; uint16_t mailbox_reg[32];
uint32_t xseq_gp_reg[128]; uint32_t xseq_gp_reg[128];
uint32_t xseq_0_reg[16]; uint32_t xseq_0_reg[16];
@ -250,7 +251,6 @@ struct qla24xx_fw_dump {
uint32_t rcvt0_data_dma_reg[32]; uint32_t rcvt0_data_dma_reg[32];
uint32_t rcvt1_data_dma_reg[32]; uint32_t rcvt1_data_dma_reg[32];
uint32_t risc_gp_reg[128]; uint32_t risc_gp_reg[128];
uint32_t shadow_reg[7];
uint32_t lmc_reg[112]; uint32_t lmc_reg[112];
uint32_t fpm_hdw_reg[192]; uint32_t fpm_hdw_reg[192];
uint32_t fb_hdw_reg[176]; uint32_t fb_hdw_reg[176];