e1000e: clear REQ and GNT in EECD (82571 && 82572)
Clear the REQ and GNT bit in the eeprom control register (EECD). This is required if the eeprom is to be accessed with auto read EERD register. After a cold reset this doesn't matter but if PBIST MAC test was executed before booting, the register was left in a dirty state (the 2 bits where set), which caused the read operation to time out and returning 0. Reference (page 312): http://download.intel.com/design/network/manuals/316080.pdf Reported-by: Aleksandar Igic <aleksandar.igic@dektech.com.au> Signed-off-by: Richard Alpe <richard.alpe@ericsson.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -999,7 +999,7 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
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**/
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**/
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static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
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static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
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{
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{
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u32 ctrl, ctrl_ext;
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u32 ctrl, ctrl_ext, eecd;
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s32 ret_val;
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s32 ret_val;
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/*
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/*
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@ -1072,6 +1072,16 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
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*/
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*/
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switch (hw->mac.type) {
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switch (hw->mac.type) {
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case e1000_82571:
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case e1000_82572:
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/*
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* REQ and GNT bits need to be cleared when using AUTO_RD
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* to access the EEPROM.
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*/
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eecd = er32(EECD);
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eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
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ew32(EECD, eecd);
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break;
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case e1000_82573:
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case e1000_82573:
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case e1000_82574:
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case e1000_82574:
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case e1000_82583:
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case e1000_82583:
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