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MIPS: MSA: Fix big-endian FPR_IDX implementation

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The maximum word size is 64-bits since MSA state is saved using st.d
which stores two 64-bit words, therefore reimplement FPR_IDX using xor,
and only within each 64-bit word.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9169/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan 2015-01-30 12:09:39 +00:00 committed by Ralf Baechle
parent 466aec5f29
commit 1f3a2c6e22
1 changed files with 1 additions and 1 deletions
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2
arch/mips/include/asm/processor.h
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@ -105,7 +105,7 @@ union fpureg {
#ifdef CONFIG_CPU_LITTLE_ENDIAN
# define FPR_IDX(width, idx) (idx)
#else
# define FPR_IDX(width, idx) ((FPU_REG_WIDTH / (width)) - 1 - (idx))
# define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
#endif
#define BUILD_FPR_ACCESS(width) \