x86/mm/cpa: Generalize __set_memory_enc_pgtable()
The kernel provides infrastructure to set or clear the encryption mask from the pages for AMD SEV, but TDX requires few tweaks. - TDX and SEV have different requirements to the cache and TLB flushing. - TDX has own routine to notify VMM about page encryption status change. Modify __set_memory_enc_pgtable() and make it flexible enough to cover both AMD SEV and Intel TDX. The AMD-specific behavior is isolated in the callbacks under x86_platform.guest. TDX will provide own version of said callbacks. [ bp: Beat into submission. ] Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Link: https://lore.kernel.org/r/20220223043528.2093214-1-brijesh.singh@amd.com
This commit is contained in:
committed by
Borislav Petkov
parent
b577f542f9
commit
1e8c5971c2
@@ -141,6 +141,21 @@ struct x86_init_acpi {
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void (*reduced_hw_early_init)(void);
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};
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/**
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* struct x86_guest - Functions used by misc guest incarnations like SEV, TDX, etc.
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*
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* @enc_status_change_prepare Notify HV before the encryption status of a range is changed
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* @enc_status_change_finish Notify HV after the encryption status of a range is changed
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* @enc_tlb_flush_required Returns true if a TLB flush is needed before changing page encryption status
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* @enc_cache_flush_required Returns true if a cache flush is needed before changing page encryption status
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*/
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struct x86_guest {
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void (*enc_status_change_prepare)(unsigned long vaddr, int npages, bool enc);
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bool (*enc_status_change_finish)(unsigned long vaddr, int npages, bool enc);
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bool (*enc_tlb_flush_required)(bool enc);
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bool (*enc_cache_flush_required)(void);
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};
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/**
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* struct x86_init_ops - functions for platform specific setup
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*
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@@ -287,6 +302,7 @@ struct x86_platform_ops {
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struct x86_legacy_features legacy;
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void (*set_legacy_features)(void);
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struct x86_hyper_runtime hyper;
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struct x86_guest guest;
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};
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struct x86_apic_ops {
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