forked from Minki/linux
ARM: Add platform support for LSI AXM55xx SoC
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15 cores (in a 4x4 cluster configuration). The cores within each cluster share an L2 cache, and the clusters are connected to each other via a CCN-504 cache coherent interconnect. This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located above 4GB in the memory map. Signed-off-by: Anders Berg <anders.berg@lsi.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Anders Berg
Arnd Bergmann
parent
a798c10faf
commit
1d22924e1c
12
Documentation/devicetree/bindings/arm/axxia.txt
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12
Documentation/devicetree/bindings/arm/axxia.txt
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@ -0,0 +1,12 @@
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Axxia AXM55xx device tree bindings
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Boards using the AXM55xx SoC need to have the following properties:
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Required root node property:
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- compatible = "lsi,axm5516"
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Boards:
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LSI AXM5516 Validation board (Amarillo)
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compatible = "lsi,axm5516-amarillo", "lsi,axm5516"
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@ -950,6 +950,8 @@ source "arch/arm/mach-mvebu/Kconfig"
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source "arch/arm/mach-at91/Kconfig"
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source "arch/arm/mach-axxia/Kconfig"
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source "arch/arm/mach-bcm/Kconfig"
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source "arch/arm/mach-berlin/Kconfig"
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@ -138,10 +138,12 @@ endif
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textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
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textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
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textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
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textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
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# Machine directory name. This list is sorted alphanumerically
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# by CONFIG_* macro name.
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machine-$(CONFIG_ARCH_AT91) += at91
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machine-$(CONFIG_ARCH_AXXIA) += axxia
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machine-$(CONFIG_ARCH_BCM) += bcm
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machine-$(CONFIG_ARCH_BERLIN) += berlin
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machine-$(CONFIG_ARCH_CLPS711X) += clps711x
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16
arch/arm/mach-axxia/Kconfig
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16
arch/arm/mach-axxia/Kconfig
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@ -0,0 +1,16 @@
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config ARCH_AXXIA
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bool "LSI Axxia platforms" if (ARCH_MULTI_V7 && ARM_LPAE)
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select ARCH_DMA_ADDR_T_64BIT
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select ARM_AMBA
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select ARM_GIC
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select ARM_TIMER_SP804
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select HAVE_ARM_ARCH_TIMER
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select MFD_SYSCON
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select MIGHT_HAVE_PCI
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select PCI_DOMAINS if PCI
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select ZONE_DMA
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help
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This enables support for the LSI Axxia devices.
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The LSI Axxia platforms require a Flattened Device Tree to be passed
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to the kernel.
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2
arch/arm/mach-axxia/Makefile
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2
arch/arm/mach-axxia/Makefile
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@ -0,0 +1,2 @@
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obj-y += axxia.o
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obj-$(CONFIG_SMP) += platsmp.o
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28
arch/arm/mach-axxia/axxia.c
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28
arch/arm/mach-axxia/axxia.c
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@ -0,0 +1,28 @@
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/*
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* Support for the LSI Axxia SoC devices based on ARM cores.
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*
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* Copyright (C) 2012 LSI
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <asm/mach/arch.h>
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static const char *axxia_dt_match[] __initconst = {
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"lsi,axm5516",
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"lsi,axm5516-sim",
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"lsi,axm5516-emu",
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NULL
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};
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DT_MACHINE_START(AXXIA_DT, "LSI Axxia AXM55XX")
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.dt_compat = axxia_dt_match,
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MACHINE_END
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89
arch/arm/mach-axxia/platsmp.c
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89
arch/arm/mach-axxia/platsmp.c
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@ -0,0 +1,89 @@
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/*
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* linux/arch/arm/mach-axxia/platsmp.c
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*
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* Copyright (C) 2012 LSI Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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/* Syscon register offsets for releasing cores from reset */
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#define SC_CRIT_WRITE_KEY 0x1000
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#define SC_RST_CPU_HOLD 0x1010
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/*
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* Write the kernel entry point for secondary CPUs to the specified address
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*/
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static void write_release_addr(u32 release_phys)
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{
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u32 *virt = (u32 *) phys_to_virt(release_phys);
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writel_relaxed(virt_to_phys(secondary_startup), virt);
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/* Make sure this store is visible to other CPUs */
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smp_wmb();
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__cpuc_flush_dcache_area(virt, sizeof(u32));
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}
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static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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struct device_node *syscon_np;
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void __iomem *syscon;
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u32 tmp;
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syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon");
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if (!syscon_np)
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return -ENOENT;
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syscon = of_iomap(syscon_np, 0);
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if (!syscon)
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return -ENOMEM;
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tmp = readl(syscon + SC_RST_CPU_HOLD);
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writel(0xab, syscon + SC_CRIT_WRITE_KEY);
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tmp &= ~(1 << cpu);
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writel(tmp, syscon + SC_RST_CPU_HOLD);
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return 0;
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}
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static void __init axxia_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu_count = 0;
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int cpu;
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/*
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* Initialise the present map, which describes the set of CPUs actually
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* populated at the present time.
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*/
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for_each_possible_cpu(cpu) {
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struct device_node *np;
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u32 release_phys;
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np = of_get_cpu_node(cpu, NULL);
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if (!np)
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continue;
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if (of_property_read_u32(np, "cpu-release-addr", &release_phys))
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continue;
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if (cpu_count < max_cpus) {
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set_cpu_present(cpu, true);
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cpu_count++;
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}
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if (release_phys != 0)
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write_release_addr(release_phys);
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}
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}
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static struct smp_operations axxia_smp_ops __initdata = {
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.smp_prepare_cpus = axxia_smp_prepare_cpus,
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.smp_boot_secondary = axxia_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(axxia_smp, "lsi,syscon-release", &axxia_smp_ops);
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36
include/dt-bindings/clock/lsi,axm5516-clks.h
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36
include/dt-bindings/clock/lsi,axm5516-clks.h
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@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2014 LSI Corporation
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*/
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#ifndef _DT_BINDINGS_CLK_AXM5516_H
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#define _DT_BINDINGS_CLK_AXM5516_H
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#define AXXIA_CLK_FAB_PLL 0
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#define AXXIA_CLK_CPU_PLL 1
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#define AXXIA_CLK_SYS_PLL 2
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#define AXXIA_CLK_SM0_PLL 3
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#define AXXIA_CLK_SM1_PLL 4
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#define AXXIA_CLK_FAB_DIV 5
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#define AXXIA_CLK_SYS_DIV 6
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#define AXXIA_CLK_NRCP_DIV 7
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#define AXXIA_CLK_CPU0_DIV 8
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#define AXXIA_CLK_CPU1_DIV 9
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#define AXXIA_CLK_CPU2_DIV 10
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#define AXXIA_CLK_CPU3_DIV 11
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#define AXXIA_CLK_PER_DIV 12
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#define AXXIA_CLK_MMC_DIV 13
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#define AXXIA_CLK_FAB 14
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#define AXXIA_CLK_SYS 15
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#define AXXIA_CLK_NRCP 16
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#define AXXIA_CLK_CPU0 17
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#define AXXIA_CLK_CPU1 18
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#define AXXIA_CLK_CPU2 19
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#define AXXIA_CLK_CPU3 20
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#define AXXIA_CLK_PER 21
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#define AXXIA_CLK_MMC 22
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#endif
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