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ARM: dts: imx6: Add imx-weim parameters to dtsi's

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imx-weim should always set address-cells to 2,
and size_cells to 1.
On imx6, fsl,weim-cs-gpr will always be &gpr

Set these common parameters in the dtsi file,
rather than in a downstream dts.

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Joshua Clayton 2016-11-01 16:51:45 -07:00 committed by Shawn Guo
parent 4631170793
commit 1be81ea586
5 changed files with 9 additions and 5 deletions
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3
arch/arm/boot/dts/imx6q-evi.dts
View File

@ -232,10 +232,7 @@
}; };
&weim { &weim {
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>; ranges = <0 0 0x08000000 0x08000000>;
fsl,weim-cs-gpr = <&gpr>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>; pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
status = "okay"; status = "okay";

2
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View File

@ -613,8 +613,6 @@
&weim { &weim {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>; ranges = <0 0 0x08000000 0x08000000>;
status = "disabled"; /* pin conflict with SPI NOR */ status = "disabled"; /* pin conflict with SPI NOR */

3
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -1092,10 +1092,13 @@
}; };
weim: weim@021b8000 { weim: weim@021b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6q-weim"; compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>; reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
fsl,weim-cs-gpr = <&gpr>;
}; };
ocotp: ocotp@021bc000 { ocotp: ocotp@021bc000 {

3
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -893,8 +893,11 @@
}; };
weim: weim@021b8000 { weim: weim@021b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>; reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
fsl,weim-cs-gpr = <&gpr>;
}; };
ocotp: ocotp@021bc000 { ocotp: ocotp@021bc000 {

3
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -968,10 +968,13 @@
}; };
weim: weim@021b8000 { weim: weim@021b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>; reg = <0x021b8000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_EIM_SLOW>; clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
fsl,weim-cs-gpr = <&gpr>;
}; };
ocotp: ocotp@021bc000 { ocotp: ocotp@021bc000 {