scsi: mpt3sas: Update MPI Headers to v02.00.57
Update MPI Headers to version 02.00.57. Link: https://lore.kernel.org/r/20191226111333.26131-2-sreekanth.reddy@broadcom.com Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Sreekanth Reddy
Martin K. Petersen
parent
5d74e18edd
commit
1ade26b616
@ -122,6 +122,9 @@
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* 08-28-18 02.00.53 Bumped MPI2_HEADER_VERSION_UNIT.
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* Added MPI2_IOCSTATUS_FAILURE
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* 12-17-18 02.00.54 Bumped MPI2_HEADER_VERSION_UNIT
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* 06-24-19 02.00.55 Bumped MPI2_HEADER_VERSION_UNIT
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* 08-01-19 02.00.56 Bumped MPI2_HEADER_VERSION_UNIT
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* 10-02-19 02.00.57 Bumped MPI2_HEADER_VERSION_UNIT
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* --------------------------------------------------------------------------
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*/
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@ -162,7 +165,7 @@
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/* Unit and Dev versioning for this MPI header set */
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#define MPI2_HEADER_VERSION_UNIT (0x36)
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#define MPI2_HEADER_VERSION_UNIT (0x39)
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#define MPI2_HEADER_VERSION_DEV (0x00)
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#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
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#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
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@ -181,6 +184,7 @@
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#define MPI2_IOC_STATE_READY (0x10000000)
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#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
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#define MPI2_IOC_STATE_FAULT (0x40000000)
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#define MPI2_IOC_STATE_COREDUMP (0x50000000)
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#define MPI2_IOC_STATE_MASK (0xF0000000)
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#define MPI2_IOC_STATE_SHIFT (28)
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@ -249,6 +249,8 @@
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* 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1
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* Added DMDReport Delay Time defines to PCIeIOUnitPage1
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* 12-17-18 02.00.47 Swap locations of Slotx2 and Slotx4 in ManPage 7.
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* 08-01-19 02.00.49 Add MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID
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* Add MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT
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*/
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#ifndef MPI2_CNFG_H
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@ -891,6 +893,8 @@ typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
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#define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
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#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
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#define MPI26_MANPAGE7_FLAG_CONN_LANE_USE_PINOUT (0x00000020)
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#define MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID (0x00000010)
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/*
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*Generic structure to use for product-specific manufacturing pages
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@ -962,9 +966,10 @@ typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
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/* IO Unit Page 1 Flags defines */
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#define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK (0x00030000)
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#define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00000000)
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#define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00010000)
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#define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00020000)
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#define MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT (16)
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#define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00000000)
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#define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00010000)
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#define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00020000)
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#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
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#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
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#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
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@ -3931,7 +3936,13 @@ typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 {
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U32 MaximumDataTransferSize; /*0x0C */
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U32 Capabilities; /*0x10 */
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U16 NOIOB; /* 0x14 */
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U16 Reserved2; /* 0x16 */
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U16 ShutdownLatency; /* 0x16 */
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U16 VendorID; /* 0x18 */
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U16 DeviceID; /* 0x1A */
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U16 SubsystemVendorID; /* 0x1C */
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U16 SubsystemID; /* 0x1E */
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U8 RevisionID; /* 0x20 */
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U8 Reserved21[3]; /* 0x21 */
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} MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
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Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t;
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@ -19,6 +19,10 @@
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* 09-07-18 02.06.03 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES
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* 12-17-18 02.06.04 Addd MPI2_EXT_IMAGE_TYPE_PBLP
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* Shorten some defines to be compatible with DOS
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* 06-24-19 02.06.05 Whitespace adjustments to help with identifier
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* checking tool.
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* 10-02-19 02.06.06 Added MPI26_IMAGE_HEADER_SIG1_COREDUMP
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* Added MPI2_FLASH_REGION_COREDUMP
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*/
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#ifndef MPI2_IMAGE_H
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#define MPI2_IMAGE_H
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@ -213,6 +217,8 @@ typedef struct _MPI26_COMPONENT_IMAGE_HEADER {
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#define MPI26_IMAGE_HEADER_SIG1_NVDATA (0x5444564E)
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#define MPI26_IMAGE_HEADER_SIG1_GAS_GAUGE (0x20534147)
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#define MPI26_IMAGE_HEADER_SIG1_PBLP (0x504C4250)
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/* little-endian "DUMP" */
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#define MPI26_IMAGE_HEADER_SIG1_COREDUMP (0x504D5544)
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/**** Definitions for Signature2 field ****/
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#define MPI26_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)
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@ -359,6 +365,7 @@ typedef struct _MPI2_FLASH_LAYOUT_DATA {
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#define MPI2_FLASH_REGION_MR_NVDATA (0x14)
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#define MPI2_FLASH_REGION_CPLD (0x15)
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#define MPI2_FLASH_REGION_PSOC (0x16)
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#define MPI2_FLASH_REGION_COREDUMP (0x17)
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/*ImageRevision */
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#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
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@ -175,6 +175,10 @@
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* Moved FW image definitions ionto new mpi2_image,h
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* 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
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* 09-07-18 02.00.37 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES
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* 10-02-19 02.00.38 Added MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE
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* Added MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED
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* Added MPI2_FW_DOWNLOAD_ITYPE_COREDUMP
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* Added MPI2_FW_UPLOAD_ITYPE_COREDUMP
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* --------------------------------------------------------------------------
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*/
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@ -248,6 +252,7 @@ typedef struct _MPI2_IOC_INIT_REQUEST {
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/*ConfigurationFlags */
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#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
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#define MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE (0x0002)
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/*minimum depth for a Reply Descriptor Post Queue */
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#define MPI2_RDPQ_DEPTH_MIN (16)
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@ -377,6 +382,7 @@ typedef struct _MPI2_IOC_FACTS_REPLY {
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/*ProductID field uses MPI2_FW_HEADER_PID_ */
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/*IOCCapabilities */
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#define MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED (0x00200000)
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#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)
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#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
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#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
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@ -1458,8 +1464,8 @@ typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
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/*MPI v2.6 and newer */
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#define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15)
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#define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
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#define MPI2_FW_DOWNLOAD_ITYPE_COREDUMP (0x17)
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#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
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#define MPI2_FW_DOWNLOAD_ITYPE_TERMINATE (0xFF)
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/*MPI v2.0 FWDownload TransactionContext Element */
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typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
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