forked from Minki/linux
drm/i915/gvt: Disable compression workaround for Gen9
With enabling this workaround, can observe GPU hang issue on Gen9. As currently host side doesn't have this workaround, disable it from GVT side. v2: - Fix indent error.(Zhenyu) Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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1999f108c9
@ -1366,18 +1366,28 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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i915_reg_t reg = {.reg = offset};
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u32 v = *(u32 *)p_data;
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if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
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return intel_vgpu_default_mmio_write(vgpu,
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offset, p_data, bytes);
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switch (offset) {
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case 0x4ddc:
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vgpu_vreg(vgpu, offset) = 0x8000003c;
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/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */
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I915_WRITE(reg, vgpu_vreg(vgpu, offset));
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/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
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vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
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break;
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case 0x42080:
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vgpu_vreg(vgpu, offset) = 0x8000;
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/* WaCompressedResourceDisplayNewHashMode:skl */
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I915_WRITE(reg, vgpu_vreg(vgpu, offset));
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/* bypass WaCompressedResourceDisplayNewHashMode */
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vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
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break;
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case 0xe194:
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/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
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vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
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break;
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case 0x7014:
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/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
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vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
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break;
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default:
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return -EINVAL;
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@ -1634,7 +1644,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
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NULL, NULL);
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MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
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skl_misc_ctl_write);
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MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
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@ -2568,7 +2579,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
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MMIO_D(0x6e570, D_BDW_PLUS);
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MMIO_D(0x65f10, D_BDW_PLUS);
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MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
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skl_misc_ctl_write);
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MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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