forked from Minki/linux
mfd: Initial support for twl5031
TWL5031 introduces two new interrupts in PIH. Moreover, BCI has changed remarkably and, thus, it's disabled when TWL5031 is in use. Signed-off-by: Ilkka Koskinen <ilkka.koskinen@nokia.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Ilkka Koskinen
Samuel Ortiz
parent
6a6127462e
commit
1920a61e20
@ -158,6 +158,10 @@
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#define TWL4030_BASEADD_PWMB 0x00F1
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#define TWL4030_BASEADD_KEYPAD 0x00D2
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#define TWL5031_BASEADD_ACCESSORY 0x0074 /* Replaces Main Charge */
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#define TWL5031_BASEADD_INTERRUPTS 0x00B9 /* Different than TWL4030's
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one */
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/* subchip/slave 3 - POWER ID */
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#define TWL4030_BASEADD_BACKUP 0x0014
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#define TWL4030_BASEADD_INT 0x002E
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@ -189,6 +193,7 @@
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/* chip-specific feature flags, for i2c_device_id.driver_data */
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#define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */
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#define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */
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#define TWL5031 BIT(2) /* twl5031 has different registers */
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/*----------------------------------------------------------------------*/
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@ -241,6 +246,8 @@ static struct twl4030mapping twl4030_map[TWL4030_MODULE_LAST + 1] = {
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{ 2, TWL4030_BASEADD_PWM1 },
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{ 2, TWL4030_BASEADD_PWMA },
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{ 2, TWL4030_BASEADD_PWMB },
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{ 2, TWL5031_BASEADD_ACCESSORY },
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{ 2, TWL5031_BASEADD_INTERRUPTS },
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{ 3, TWL4030_BASEADD_BACKUP },
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{ 3, TWL4030_BASEADD_INT },
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@ -488,7 +495,8 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
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{
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struct device *child;
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if (twl_has_bci() && pdata->bci && !(features & TPS_SUBSET)) {
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if (twl_has_bci() && pdata->bci &&
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!(features & (TPS_SUBSET | TWL5031))) {
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child = add_child(3, "twl4030_bci",
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pdata->bci, sizeof(*pdata->bci),
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false,
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@ -760,6 +768,7 @@ static void clocks_init(struct device *dev,
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int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end);
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int twl_exit_irq(void);
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int twl_init_chip_irq(const char *chip);
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static int twl4030_remove(struct i2c_client *client)
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{
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@ -835,6 +844,7 @@ twl4030_probe(struct i2c_client *client, const struct i2c_device_id *id)
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if (client->irq
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&& pdata->irq_base
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&& pdata->irq_end > pdata->irq_base) {
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twl_init_chip_irq(id->name);
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status = twl_init_irq(client->irq, pdata->irq_base, pdata->irq_end);
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if (status < 0)
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goto fail;
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@ -850,6 +860,7 @@ fail:
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static const struct i2c_device_id twl4030_ids[] = {
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{ "twl4030", TWL4030_VAUX2 }, /* "Triton 2" */
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{ "twl5030", 0 }, /* T2 updated */
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{ "twl5031", TWL5031 }, /* TWL5030 updated */
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{ "tps65950", 0 }, /* catalog version of twl5030 */
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{ "tps65930", TPS_SUBSET }, /* fewer LDOs and DACs; no charger */
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{ "tps65920", TPS_SUBSET }, /* fewer LDOs; no codec or charger */
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@ -74,6 +74,8 @@ struct sih {
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u8 edr_offset;
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u8 bytes_edr; /* bytelen of EDR */
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u8 irq_lines; /* number of supported irq lines */
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/* SIR ignored -- set interrupt, for testing only */
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struct irq_data {
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u8 isr_offset;
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@ -82,6 +84,9 @@ struct sih {
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/* + 2 bytes padding */
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};
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static const struct sih *sih_modules;
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static int nr_sih_modules;
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#define SIH_INITIALIZER(modname, nbits) \
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.module = TWL4030_MODULE_ ## modname, \
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.control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
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@ -89,6 +94,7 @@ struct sih {
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.bytes_ixr = DIV_ROUND_UP(nbits, 8), \
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.edr_offset = TWL4030_ ## modname ## _EDR, \
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.bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
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.irq_lines = 2, \
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.mask = { { \
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.isr_offset = TWL4030_ ## modname ## _ISR1, \
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.imr_offset = TWL4030_ ## modname ## _IMR1, \
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@ -107,7 +113,8 @@ struct sih {
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/* Order in this table matches order in PIH_ISR. That is,
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* BIT(n) in PIH_ISR is sih_modules[n].
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*/
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static const struct sih sih_modules[6] = {
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/* sih_modules_twl4030 is used both in twl4030 and twl5030 */
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static const struct sih sih_modules_twl4030[6] = {
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[0] = {
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.name = "gpio",
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.module = TWL4030_MODULE_GPIO,
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@ -118,6 +125,7 @@ static const struct sih sih_modules[6] = {
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/* Note: *all* of these IRQs default to no-trigger */
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.edr_offset = REG_GPIO_EDR1,
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.bytes_edr = 5,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = REG_GPIO_ISR1A,
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.imr_offset = REG_GPIO_IMR1A,
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@ -140,6 +148,7 @@ static const struct sih sih_modules[6] = {
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.edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
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/* Note: most of these IRQs default to no-trigger */
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.bytes_edr = 3,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
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.imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
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@ -164,6 +173,99 @@ static const struct sih sih_modules[6] = {
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/* there are no SIH modules #6 or #7 ... */
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};
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static const struct sih sih_modules_twl5031[8] = {
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[0] = {
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.name = "gpio",
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.module = TWL4030_MODULE_GPIO,
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.control_offset = REG_GPIO_SIH_CTRL,
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.set_cor = true,
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.bits = TWL4030_GPIO_MAX,
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.bytes_ixr = 3,
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/* Note: *all* of these IRQs default to no-trigger */
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.edr_offset = REG_GPIO_EDR1,
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.bytes_edr = 5,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = REG_GPIO_ISR1A,
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.imr_offset = REG_GPIO_IMR1A,
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}, {
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.isr_offset = REG_GPIO_ISR1B,
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.imr_offset = REG_GPIO_IMR1B,
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}, },
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},
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[1] = {
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.name = "keypad",
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.set_cor = true,
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SIH_INITIALIZER(KEYPAD_KEYP, 4)
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},
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[2] = {
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.name = "bci",
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.module = TWL5031_MODULE_INTERRUPTS,
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.control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
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.bits = 7,
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.bytes_ixr = 1,
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.edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
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/* Note: most of these IRQs default to no-trigger */
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.bytes_edr = 2,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = TWL5031_INTERRUPTS_BCIISR1,
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.imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
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}, {
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.isr_offset = TWL5031_INTERRUPTS_BCIISR2,
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.imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
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}, },
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},
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[3] = {
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.name = "madc",
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SIH_INITIALIZER(MADC, 4)
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},
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[4] = {
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/* USB doesn't use the same SIH organization */
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.name = "usb",
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},
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[5] = {
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.name = "power",
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.set_cor = true,
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SIH_INITIALIZER(INT_PWR, 8)
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},
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[6] = {
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/*
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* ACI doesn't use the same SIH organization.
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* For example, it supports only one interrupt line
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*/
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.name = "aci",
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.module = TWL5031_MODULE_ACCESSORY,
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.bits = 9,
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.bytes_ixr = 2,
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.irq_lines = 1,
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.mask = { {
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.isr_offset = TWL5031_ACIIDR_LSB,
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.imr_offset = TWL5031_ACIIMR_LSB,
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}, },
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},
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[7] = {
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/* Accessory */
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.name = "acc",
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.module = TWL5031_MODULE_ACCESSORY,
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.control_offset = TWL5031_ACCSIHCTRL,
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.bits = 2,
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.bytes_ixr = 1,
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.edr_offset = TWL5031_ACCEDR1,
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/* Note: most of these IRQs default to no-trigger */
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.bytes_edr = 1,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = TWL5031_ACCISR1,
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.imr_offset = TWL5031_ACCIMR1,
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}, {
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.isr_offset = TWL5031_ACCISR2,
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.imr_offset = TWL5031_ACCIMR2,
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}, },
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},
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};
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#undef TWL4030_MODULE_KEYPAD_KEYP
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#undef TWL4030_MODULE_INT_PWR
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#undef TWL4030_INT_PWR_EDR
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@ -284,12 +386,16 @@ static int twl4030_init_sih_modules(unsigned line)
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/* disable all interrupts on our line */
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memset(buf, 0xff, sizeof buf);
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sih = sih_modules;
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for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) {
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for (i = 0; i < nr_sih_modules; i++, sih++) {
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/* skip USB -- it's funky */
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if (!sih->bytes_ixr)
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continue;
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/* Not all the SIH modules support multiple interrupt lines */
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if (sih->irq_lines <= line)
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continue;
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status = twl4030_i2c_write(sih->module, buf,
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sih->mask[line].imr_offset, sih->bytes_ixr);
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if (status < 0)
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@ -314,7 +420,7 @@ static int twl4030_init_sih_modules(unsigned line)
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}
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sih = sih_modules;
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for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) {
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for (i = 0; i < nr_sih_modules; i++, sih++) {
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u8 rxbuf[4];
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int j;
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@ -322,6 +428,10 @@ static int twl4030_init_sih_modules(unsigned line)
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if (!sih->bytes_ixr)
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continue;
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/* Not all the SIH modules support multiple interrupt lines */
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if (sih->irq_lines <= line)
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continue;
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/* Clear pending interrupt status. Either the read was
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* enough, or we need to write those bits. Repeat, in
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* case an IRQ is pending (PENDDIS=0) ... that's not
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@ -611,7 +721,7 @@ int twl4030_sih_setup(int module)
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/* only support modules with standard clear-on-read for now */
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for (sih_mod = 0, sih = sih_modules;
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sih_mod < ARRAY_SIZE(sih_modules);
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sih_mod < nr_sih_modules;
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sih_mod++, sih++) {
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if (sih->module == module && sih->set_cor) {
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if (!WARN((irq_base + sih->bits) > NR_IRQS,
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@ -756,3 +866,16 @@ int twl_exit_irq(void)
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}
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return 0;
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}
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int twl_init_chip_irq(const char *chip)
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{
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if (!strcmp(chip, "twl5031")) {
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sih_modules = sih_modules_twl5031;
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nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
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} else {
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sih_modules = sih_modules_twl4030;
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nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
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}
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return 0;
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}
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@ -61,13 +61,16 @@
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#define TWL4030_MODULE_PWMA 0x0E
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#define TWL4030_MODULE_PWMB 0x0F
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#define TWL5031_MODULE_ACCESSORY 0x10
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#define TWL5031_MODULE_INTERRUPTS 0x11
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/* Slave 3 (i2c address 0x4b) */
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#define TWL4030_MODULE_BACKUP 0x10
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#define TWL4030_MODULE_INT 0x11
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#define TWL4030_MODULE_PM_MASTER 0x12
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#define TWL4030_MODULE_PM_RECEIVER 0x13
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#define TWL4030_MODULE_RTC 0x14
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#define TWL4030_MODULE_SECURED_REG 0x15
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#define TWL4030_MODULE_BACKUP 0x12
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#define TWL4030_MODULE_INT 0x13
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#define TWL4030_MODULE_PM_MASTER 0x14
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#define TWL4030_MODULE_PM_RECEIVER 0x15
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#define TWL4030_MODULE_RTC 0x16
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#define TWL4030_MODULE_SECURED_REG 0x17
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/*
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* Read and write single 8-bit registers
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@ -221,6 +224,38 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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/*----------------------------------------------------------------------*/
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/*
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* Accessory Interrupts
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*/
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#define TWL5031_ACIIMR_LSB 0x05
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#define TWL5031_ACIIMR_MSB 0x06
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#define TWL5031_ACIIDR_LSB 0x07
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#define TWL5031_ACIIDR_MSB 0x08
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#define TWL5031_ACCISR1 0x0F
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#define TWL5031_ACCIMR1 0x10
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#define TWL5031_ACCISR2 0x11
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#define TWL5031_ACCIMR2 0x12
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#define TWL5031_ACCSIR 0x13
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#define TWL5031_ACCEDR1 0x14
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#define TWL5031_ACCSIHCTRL 0x15
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/*----------------------------------------------------------------------*/
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/*
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* Battery Charger Controller
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*/
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#define TWL5031_INTERRUPTS_BCIISR1 0x0
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#define TWL5031_INTERRUPTS_BCIIMR1 0x1
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#define TWL5031_INTERRUPTS_BCIISR2 0x2
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#define TWL5031_INTERRUPTS_BCIIMR2 0x3
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#define TWL5031_INTERRUPTS_BCISIR 0x4
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#define TWL5031_INTERRUPTS_BCIEDR1 0x5
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#define TWL5031_INTERRUPTS_BCIEDR2 0x6
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#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
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/*----------------------------------------------------------------------*/
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/* Power bus message definitions */
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/* The TWL4030/5030 splits its power-management resources (the various
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