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drm/i915/adl_s: Add vbt port and aux channel settings for adls

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- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C,
  D and E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-10-aditya.swarup@intel.com
This commit is contained in:
Aditya Swarup
2021-01-25 06:07:52 -08:00
committed by Lucas De Marchi
parent 7dc1f92f27
commit 18c283df5a
1 changed files with 46 additions and 11 deletions
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57
drivers/gpu/drm/i915/display/intel_bios.c
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@@ -1719,8 +1719,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
}; };
/*
* Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
* PORT_F and PORT_G, we need to map that to correct VBT sections.
*/
static const int adls_port_mapping[][3] = {
[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
[PORT_B] = { -1 },
[PORT_C] = { -1 },
[PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
[PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
[PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
[PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
};
if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) if (IS_ALDERLAKE_S(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
ARRAY_SIZE(adls_port_mapping[0]),
adls_port_mapping,
dvo_port);
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]), ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping, rkl_port_mapping,
@@ -2672,27 +2690,44 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
return aux_ch; return aux_ch;
} }
/*
* RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
* map to DDI A,B,TC1,TC2 respectively.
*
* ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
* map to DDI A,TC1,TC2,TC3,TC4 respectively.
*/
switch (info->alternate_aux_channel) { switch (info->alternate_aux_channel) {
case DP_AUX_A: case DP_AUX_A:
aux_ch = AUX_CH_A; aux_ch = AUX_CH_A;
break; break;
case DP_AUX_B: case DP_AUX_B:
aux_ch = AUX_CH_B; if (IS_ALDERLAKE_S(dev_priv))
aux_ch = AUX_CH_USBC1;
else
aux_ch = AUX_CH_B;
break; break;
case DP_AUX_C: case DP_AUX_C:
/* if (IS_ALDERLAKE_S(dev_priv))
* RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D aux_ch = AUX_CH_USBC2;
* map to DDI A,B,TC1,TC2 respectively. else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
*/ aux_ch = AUX_CH_USBC1;
aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ? else
AUX_CH_USBC1 : AUX_CH_C; aux_ch = AUX_CH_C;
break; break;
case DP_AUX_D: case DP_AUX_D:
aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ? if (IS_ALDERLAKE_S(dev_priv))
AUX_CH_USBC2 : AUX_CH_D; aux_ch = AUX_CH_USBC3;
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
aux_ch = AUX_CH_USBC2;
else
aux_ch = AUX_CH_D;
break; break;
case DP_AUX_E: case DP_AUX_E:
aux_ch = AUX_CH_E; if (IS_ALDERLAKE_S(dev_priv))
aux_ch = AUX_CH_USBC4;
else
aux_ch = AUX_CH_E;
break; break;
case DP_AUX_F: case DP_AUX_F:
aux_ch = AUX_CH_F; aux_ch = AUX_CH_F;