arm64: Add missing Falkor part number for branch predictor hardening
References to CPU part number MIDR_QCOM_FALKOR were dropped from the
mailing list patch due to mainline/arm64 branch dependency. So this
patch adds the missing part number.
Fixes: ec82b567a7
("arm64: Implement branch predictor hardening for Falkor")
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
parent
7928b2cbe5
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@ -406,6 +406,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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},
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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.enable = qcom_enable_link_stack_sanitization,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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},
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{
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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@ -407,8 +407,10 @@ again:
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u32 midr = read_cpuid_id();
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u32 midr = read_cpuid_id();
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/* Apply BTAC predictors mitigation to all Falkor chips */
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/* Apply BTAC predictors mitigation to all Falkor chips */
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if ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)
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if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
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((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) {
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__qcom_hyp_sanitize_btac_predictors();
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__qcom_hyp_sanitize_btac_predictors();
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}
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}
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}
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fp_enabled = __fpsimd_enabled();
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fp_enabled = __fpsimd_enabled();
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