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Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm

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* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (161 commits)
  ARM: pxa: fix building issue of missing physmap.h
  ARM: mmp: PXA910 drive strength FAST using wrong value
  ARM: mmp: MMP2 drive strength FAST using wrong value
  ARM: pxa: fix recursive calls in pxa_low_gpio_chip
  AT91: Support for gsia18s board
  AT91: Acme Systems FOX Board G20 board files
  AT91: board-sam9m10g45ek.c: Remove duplicate inclusion of mach/hardware.h
  ARM: pxa: fix suspend/resume array index miscalculation
  ARM: pxa: use cpu_has_ipr() consistently in irq.c
  ARM: pxa: remove unused variable in clock-pxa3xx.c
  ARM: pxa: fix warning in zeus.c
  ARM: sa1111: fix typo in sa1111_retrigger_lowirq()
  ARM mxs: clkdev related compile fixes
  ARM i.MX mx31_3ds: Fix MC13783 regulator names
  ARM: plat-stmp3xxx: irq_data conversion.
  ARM: plat-spear: irq_data conversion.
  ARM: plat-orion: irq_data conversion.
  ARM: plat-omap: irq_data conversion.
  ARM: plat-nomadik: irq_data conversion.
  ARM: plat-mxc: irq_data conversion.
  ...

Fix up trivial conflict in arch/arm/plat-omap/gpio.c (Lennert
Buytenhek's irq_data conversion clashing with some omap irq updates)
This commit is contained in:
Linus Torvalds 2011-01-15 12:33:40 -08:00
commit 16c1020362
250 changed files with 6534 additions and 2397 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm/Kconfig
View File

@ -26,6 +26,8 @@ config ARM
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
select HAVE_C_RECORDMCOUNT
select HAVE_GENERIC_HARDIRQS
select HAVE_SPARSE_IRQ
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
@ -97,10 +99,6 @@ config MCA
<file:Documentation/mca.txt> (and especially the web page given
there) before attempting to build an MCA bus kernel.
config GENERIC_HARDIRQS
bool
default y
config STACKTRACE_SUPPORT
bool
default y
@ -180,9 +178,6 @@ config FIQ
config ARCH_MTD_XIP
bool
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config ARM_L1_CACHE_SHIFT_6
bool
help
@ -368,7 +363,7 @@ config ARCH_MXS
bool "Freescale MXS-based"
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select COMMON_CLKDEV
select CLKDEV_LOOKUP
help
Support for Freescale MXS-based family of processors
@ -771,6 +766,7 @@ config ARCH_S5PV310
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_I2C if I2C
@ -1452,15 +1448,6 @@ config HW_PERF_EVENTS
Enable hardware performance counter support for perf events. If
disabled, perf events will use software events only.
config SPARSE_IRQ
def_bool n
help
This enables support for sparse irqs. This is useful in general
as most CPUs have a fairly sparse array of IRQ vectors, which
the irq_desc then maps directly on to. Systems with a high
number of off-chip IRQs will want to treat this as
experimental until they have been independently verified.
source "mm/Kconfig"
config FORCE_MAX_ZONEORDER

66
arch/arm/common/gic.c
View File

@ -50,57 +50,56 @@ struct gic_chip_data {
static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
static inline void __iomem *gic_dist_base(unsigned int irq)
static inline void __iomem *gic_dist_base(struct irq_data *d)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
return gic_data->dist_base;
}
static inline void __iomem *gic_cpu_base(unsigned int irq)
static inline void __iomem *gic_cpu_base(struct irq_data *d)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
return gic_data->cpu_base;
}
static inline unsigned int gic_irq(unsigned int irq)
static inline unsigned int gic_irq(struct irq_data *d)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
return irq - gic_data->irq_offset;
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
return d->irq - gic_data->irq_offset;
}
/*
* Routines to acknowledge, disable and enable interrupts
*/
static void gic_ack_irq(unsigned int irq)
static void gic_ack_irq(struct irq_data *d)
{
spin_lock(&irq_controller_lock);
writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
spin_unlock(&irq_controller_lock);
}
static void gic_mask_irq(unsigned int irq)
static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 << (irq % 32);
u32 mask = 1 << (d->irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
spin_unlock(&irq_controller_lock);
}
static void gic_unmask_irq(unsigned int irq)
static void gic_unmask_irq(struct irq_data *d)
{
u32 mask = 1 << (irq % 32);
u32 mask = 1 << (d->irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
spin_unlock(&irq_controller_lock);
}
static int gic_set_type(unsigned int irq, unsigned int type)
static int gic_set_type(struct irq_data *d, unsigned int type)
{
void __iomem *base = gic_dist_base(irq);
unsigned int gicirq = gic_irq(irq);
void __iomem *base = gic_dist_base(d);
unsigned int gicirq = gic_irq(d);
u32 enablemask = 1 << (gicirq % 32);
u32 enableoff = (gicirq / 32) * 4;
u32 confmask = 0x2 << ((gicirq % 16) * 2);
@ -143,21 +142,22 @@ static int gic_set_type(unsigned int irq, unsigned int type)
}
#ifdef CONFIG_SMP
static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
static int
gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force)
{
void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
unsigned int shift = (irq % 4) * 8;
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
unsigned int shift = (d->irq % 4) * 8;
unsigned int cpu = cpumask_first(mask_val);
u32 val;
struct irq_desc *desc;
spin_lock(&irq_controller_lock);
desc = irq_to_desc(irq);
desc = irq_to_desc(d->irq);
if (desc == NULL) {
spin_unlock(&irq_controller_lock);
return -EINVAL;
}
desc->node = cpu;
d->node = cpu;
val = readl(reg) & ~(0xff << shift);
val |= 1 << (cpu + shift);
writel(val, reg);
@ -175,7 +175,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
unsigned long status;
/* primary controller ack'ing */
chip->ack(irq);
chip->irq_ack(&desc->irq_data);
spin_lock(&irq_controller_lock);
status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
@ -193,17 +193,17 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
out:
/* primary controller unmasking */
chip->unmask(irq);
chip->irq_unmask(&desc->irq_data);
}
static struct irq_chip gic_chip = {
.name = "GIC",
.ack = gic_ack_irq,
.mask = gic_mask_irq,
.unmask = gic_unmask_irq,
.set_type = gic_set_type,
.name = "GIC",
.irq_ack = gic_ack_irq,
.irq_mask = gic_mask_irq,
.irq_unmask = gic_unmask_irq,
.irq_set_type = gic_set_type,
#ifdef CONFIG_SMP
.set_affinity = gic_set_cpu,
.irq_set_affinity = gic_set_cpu,
#endif
};
@ -337,7 +337,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq)
local_irq_save(flags);
irq_to_desc(irq)->status |= IRQ_NOPROBE;
gic_unmask_irq(irq);
gic_unmask_irq(irq_get_irq_data(irq));
local_irq_restore(flags);
}

14
arch/arm/common/it8152.c
View File

@ -31,8 +31,10 @@
#define MAX_SLOTS 21
static void it8152_mask_irq(unsigned int irq)
static void it8152_mask_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
if (irq >= IT8152_LD_IRQ(0)) {
__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
(1 << (irq - IT8152_LD_IRQ(0)))),
@ -48,8 +50,10 @@ static void it8152_mask_irq(unsigned int irq)
}
}
static void it8152_unmask_irq(unsigned int irq)
static void it8152_unmask_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
if (irq >= IT8152_LD_IRQ(0)) {
__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
~(1 << (irq - IT8152_LD_IRQ(0)))),
@ -67,9 +71,9 @@ static void it8152_unmask_irq(unsigned int irq)
static struct irq_chip it8152_irq_chip = {
.name = "it8152",
.ack = it8152_mask_irq,
.mask = it8152_mask_irq,
.unmask = it8152_unmask_irq,
.irq_ack = it8152_mask_irq,
.irq_mask = it8152_mask_irq,
.irq_unmask = it8152_unmask_irq,
};
void it8152_init_irq(void)

24
arch/arm/common/locomo.c
View File

@ -144,7 +144,7 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc)
int req, i;
/* Acknowledge the parent IRQ */
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
/* check why this interrupt was generated */
req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00;
@ -161,33 +161,33 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc)
}
}
static void locomo_ack_irq(unsigned int irq)
static void locomo_ack_irq(struct irq_data *d)
{
}
static void locomo_mask_irq(unsigned int irq)
static void locomo_mask_irq(struct irq_data *d)
{
struct locomo *lchip = get_irq_chip_data(irq);
struct locomo *lchip = irq_data_get_irq_chip_data(d);
unsigned int r;
r = locomo_readl(lchip->base + LOCOMO_ICR);
r &= ~(0x0010 << (irq - lchip->irq_base));
r &= ~(0x0010 << (d->irq - lchip->irq_base));
locomo_writel(r, lchip->base + LOCOMO_ICR);
}
static void locomo_unmask_irq(unsigned int irq)
static void locomo_unmask_irq(struct irq_data *d)
{
struct locomo *lchip = get_irq_chip_data(irq);
struct locomo *lchip = irq_data_get_irq_chip_data(d);
unsigned int r;
r = locomo_readl(lchip->base + LOCOMO_ICR);
r |= (0x0010 << (irq - lchip->irq_base));
r |= (0x0010 << (d->irq - lchip->irq_base));
locomo_writel(r, lchip->base + LOCOMO_ICR);
}
static struct irq_chip locomo_chip = {
.name = "LOCOMO",
.ack = locomo_ack_irq,
.mask = locomo_mask_irq,
.unmask = locomo_unmask_irq,
.name = "LOCOMO",
.irq_ack = locomo_ack_irq,
.irq_mask = locomo_mask_irq,
.irq_unmask = locomo_unmask_irq,
};
static void locomo_setup_irq(struct locomo *lchip)

96
arch/arm/common/sa1111.c
View File

@ -210,7 +210,7 @@ sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0);
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1);
@ -228,35 +228,35 @@ sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(i + sachip->irq_base);
/* For level-based interrupts */
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
#define SA1111_IRQMASK_LO(x) (1 << (x - sachip->irq_base))
#define SA1111_IRQMASK_HI(x) (1 << (x - sachip->irq_base - 32))
static void sa1111_ack_irq(unsigned int irq)
static void sa1111_ack_irq(struct irq_data *d)
{
}
static void sa1111_mask_lowirq(unsigned int irq)
static void sa1111_mask_lowirq(struct irq_data *d)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned long ie0;
ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
ie0 &= ~SA1111_IRQMASK_LO(irq);
ie0 &= ~SA1111_IRQMASK_LO(d->irq);
writel(ie0, mapbase + SA1111_INTEN0);
}
static void sa1111_unmask_lowirq(unsigned int irq)
static void sa1111_unmask_lowirq(struct irq_data *d)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned long ie0;
ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
ie0 |= SA1111_IRQMASK_LO(irq);
ie0 |= SA1111_IRQMASK_LO(d->irq);
sa1111_writel(ie0, mapbase + SA1111_INTEN0);
}
@ -267,11 +267,11 @@ static void sa1111_unmask_lowirq(unsigned int irq)
* be triggered. In fact, its very difficult, if not impossible to get
* INTSET to re-trigger the interrupt.
*/
static int sa1111_retrigger_lowirq(unsigned int irq)
static int sa1111_retrigger_lowirq(struct irq_data *d)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned int mask = SA1111_IRQMASK_LO(irq);
unsigned int mask = SA1111_IRQMASK_LO(d->irq);
unsigned long ip0;
int i;
@ -279,21 +279,21 @@ static int sa1111_retrigger_lowirq(unsigned int irq)
for (i = 0; i < 8; i++) {
sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0);
sa1111_writel(ip0, mapbase + SA1111_INTPOL0);
if (sa1111_readl(mapbase + SA1111_INTSTATCLR1) & mask)
if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask)
break;
}
if (i == 8)
printk(KERN_ERR "Danger Will Robinson: failed to "
"re-trigger IRQ%d\n", irq);
"re-trigger IRQ%d\n", d->irq);
return i == 8 ? -1 : 0;
}
static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
static int sa1111_type_lowirq(struct irq_data *d, unsigned int flags)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned int mask = SA1111_IRQMASK_LO(irq);
unsigned int mask = SA1111_IRQMASK_LO(d->irq);
unsigned long ip0;
if (flags == IRQ_TYPE_PROBE)
@ -313,11 +313,11 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
return 0;
}
static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
static int sa1111_wake_lowirq(struct irq_data *d, unsigned int on)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned int mask = SA1111_IRQMASK_LO(irq);
unsigned int mask = SA1111_IRQMASK_LO(d->irq);
unsigned long we0;
we0 = sa1111_readl(mapbase + SA1111_WAKEEN0);
@ -332,33 +332,33 @@ static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
static struct irq_chip sa1111_low_chip = {
.name = "SA1111-l",
.ack = sa1111_ack_irq,
.mask = sa1111_mask_lowirq,
.unmask = sa1111_unmask_lowirq,
.retrigger = sa1111_retrigger_lowirq,
.set_type = sa1111_type_lowirq,
.set_wake = sa1111_wake_lowirq,
.irq_ack = sa1111_ack_irq,
.irq_mask = sa1111_mask_lowirq,
.irq_unmask = sa1111_unmask_lowirq,
.irq_retrigger = sa1111_retrigger_lowirq,
.irq_set_type = sa1111_type_lowirq,
.irq_set_wake = sa1111_wake_lowirq,
};
static void sa1111_mask_highirq(unsigned int irq)
static void sa1111_mask_highirq(struct irq_data *d)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned long ie1;
ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
ie1 &= ~SA1111_IRQMASK_HI(irq);
ie1 &= ~SA1111_IRQMASK_HI(d->irq);
sa1111_writel(ie1, mapbase + SA1111_INTEN1);
}
static void sa1111_unmask_highirq(unsigned int irq)
static void sa1111_unmask_highirq(struct irq_data *d)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned long ie1;
ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
ie1 |= SA1111_IRQMASK_HI(irq);
ie1 |= SA1111_IRQMASK_HI(d->irq);
sa1111_writel(ie1, mapbase + SA1111_INTEN1);
}
@ -369,11 +369,11 @@ static void sa1111_unmask_highirq(unsigned int irq)
* be triggered. In fact, its very difficult, if not impossible to get
* INTSET to re-trigger the interrupt.
*/
static int sa1111_retrigger_highirq(unsigned int irq)
static int sa1111_retrigger_highirq(struct irq_data *d)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned int mask = SA1111_IRQMASK_HI(irq);
unsigned int mask = SA1111_IRQMASK_HI(d->irq);
unsigned long ip1;
int i;
@ -387,15 +387,15 @@ static int sa1111_retrigger_highirq(unsigned int irq)
if (i == 8)
printk(KERN_ERR "Danger Will Robinson: failed to "
"re-trigger IRQ%d\n", irq);
"re-trigger IRQ%d\n", d->irq);
return i == 8 ? -1 : 0;
}
static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
static int sa1111_type_highirq(struct irq_data *d, unsigned int flags)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned int mask = SA1111_IRQMASK_HI(irq);
unsigned int mask = SA1111_IRQMASK_HI(d->irq);
unsigned long ip1;
if (flags == IRQ_TYPE_PROBE)
@ -415,11 +415,11 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
return 0;
}
static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
static int sa1111_wake_highirq(struct irq_data *d, unsigned int on)
{
struct sa1111 *sachip = get_irq_chip_data(irq);
struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
void __iomem *mapbase = sachip->base + SA1111_INTC;
unsigned int mask = SA1111_IRQMASK_HI(irq);
unsigned int mask = SA1111_IRQMASK_HI(d->irq);
unsigned long we1;
we1 = sa1111_readl(mapbase + SA1111_WAKEEN1);
@ -434,12 +434,12 @@ static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
static struct irq_chip sa1111_high_chip = {
.name = "SA1111-h",
.ack = sa1111_ack_irq,
.mask = sa1111_mask_highirq,
.unmask = sa1111_unmask_highirq,
.retrigger = sa1111_retrigger_highirq,
.set_type = sa1111_type_highirq,
.set_wake = sa1111_wake_highirq,
.irq_ack = sa1111_ack_irq,
.irq_mask = sa1111_mask_highirq,
.irq_unmask = sa1111_unmask_highirq,
.irq_retrigger = sa1111_retrigger_highirq,
.irq_set_type = sa1111_type_highirq,
.irq_set_wake = sa1111_wake_highirq,
};
static void sa1111_setup_irq(struct sa1111 *sachip)

32
arch/arm/common/vic.c
View File

@ -204,26 +204,26 @@ static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 res
static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
#endif /* CONFIG_PM */
static void vic_ack_irq(unsigned int irq)
static void vic_ack_irq(struct irq_data *d)
{
void __iomem *base = get_irq_chip_data(irq);
irq &= 31;
void __iomem *base = irq_data_get_irq_chip_data(d);
unsigned int irq = d->irq & 31;
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
/* moreover, clear the soft-triggered, in case it was the reason */
writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
}
static void vic_mask_irq(unsigned int irq)
static void vic_mask_irq(struct irq_data *d)
{
void __iomem *base = get_irq_chip_data(irq);
irq &= 31;
void __iomem *base = irq_data_get_irq_chip_data(d);
unsigned int irq = d->irq & 31;
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
}
static void vic_unmask_irq(unsigned int irq)
static void vic_unmask_irq(struct irq_data *d)
{
void __iomem *base = get_irq_chip_data(irq);
irq &= 31;
void __iomem *base = irq_data_get_irq_chip_data(d);
unsigned int irq = d->irq & 31;
writel(1 << irq, base + VIC_INT_ENABLE);
}
@ -242,10 +242,10 @@ static struct vic_device *vic_from_irq(unsigned int irq)
return NULL;
}
static int vic_set_wake(unsigned int irq, unsigned int on)
static int vic_set_wake(struct irq_data *d, unsigned int on)
{
struct vic_device *v = vic_from_irq(irq);
unsigned int off = irq & 31;
struct vic_device *v = vic_from_irq(d->irq);
unsigned int off = d->irq & 31;
u32 bit = 1 << off;
if (!v)
@ -267,10 +267,10 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
static struct irq_chip vic_chip = {
.name = "VIC",
.ack = vic_ack_irq,
.mask = vic_mask_irq,
.unmask = vic_unmask_irq,
.set_wake = vic_set_wake,
.irq_ack = vic_ack_irq,
.irq_mask = vic_mask_irq,
.irq_unmask = vic_unmask_irq,
.irq_set_wake = vic_set_wake,
};
static void __init vic_disable(void __iomem *base)

28
arch/arm/kernel/ecard.c
View File

@ -443,40 +443,40 @@ static expansioncard_ops_t ecard_default_ops = {
*
* They are not meant to be called directly, but via enable/disable_irq.
*/
static void ecard_irq_unmask(unsigned int irqnr)
static void ecard_irq_unmask(struct irq_data *d)
{
ecard_t *ec = slot_to_ecard(irqnr - 32);
ecard_t *ec = slot_to_ecard(d->irq - 32);
if (ec) {
if (!ec->ops)
ec->ops = &ecard_default_ops;
if (ec->claimed && ec->ops->irqenable)
ec->ops->irqenable(ec, irqnr);
ec->ops->irqenable(ec, d->irq);
else
printk(KERN_ERR "ecard: rejecting request to "
"enable IRQs for %d\n", irqnr);
"enable IRQs for %d\n", d->irq);
}
}
static void ecard_irq_mask(unsigned int irqnr)
static void ecard_irq_mask(struct irq_data *d)
{
ecard_t *ec = slot_to_ecard(irqnr - 32);
ecard_t *ec = slot_to_ecard(d->irq - 32);
if (ec) {
if (!ec->ops)
ec->ops = &ecard_default_ops;
if (ec->ops && ec->ops->irqdisable)
ec->ops->irqdisable(ec, irqnr);
ec->ops->irqdisable(ec, d->irq);
}
}
static struct irq_chip ecard_chip = {
.name = "ECARD",
.ack = ecard_irq_mask,
.mask = ecard_irq_mask,
.unmask = ecard_irq_unmask,
.name = "ECARD",
.irq_ack = ecard_irq_mask,
.irq_mask = ecard_irq_mask,
.irq_unmask = ecard_irq_unmask,
};
void ecard_enablefiq(unsigned int fiqnr)
@ -551,7 +551,7 @@ static void ecard_check_lockup(struct irq_desc *desc)
printk(KERN_ERR "\nInterrupt lockup detected - "
"disabling all expansion card interrupts\n");
desc->chip->mask(IRQ_EXPANSIONCARD);
desc->irq_data.chip->irq_mask(&desc->irq_data);
ecard_dump_irq_state();
}
} else
@ -574,7 +574,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
ecard_t *ec;
int called = 0;
desc->chip->mask(irq);
desc->irq_data.chip->irq_mask(&desc->irq_data);
for (ec = cards; ec; ec = ec->next) {
int pending;
@ -591,7 +591,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
called ++;
}
}
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
if (called == 0)
ecard_check_lockup(desc);

17
arch/arm/kernel/irq.c
View File

@ -88,7 +88,7 @@ int show_interrupts(struct seq_file *p, void *v)
seq_printf(p, "%*d: ", prec, i);
for_each_present_cpu(cpu)
seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
seq_printf(p, " %10s", desc->chip->name ? : "-");
seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-");
seq_printf(p, " %s", action->name);
for (action = action->next; action; action = action->next)
seq_printf(p, ", %s", action->name);
@ -181,10 +181,11 @@ int __init arch_probe_nr_irqs(void)
static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
{
pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu);
pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->irq_data.node, cpu);
raw_spin_lock_irq(&desc->lock);
desc->chip->set_affinity(irq, cpumask_of(cpu));
desc->irq_data.chip->irq_set_affinity(&desc->irq_data,
cpumask_of(cpu), false);
raw_spin_unlock_irq(&desc->lock);
}
@ -199,16 +200,18 @@ void migrate_irqs(void)
struct irq_desc *desc;
for_each_irq_desc(i, desc) {
if (desc->node == cpu) {
unsigned int newcpu = cpumask_any_and(desc->affinity,
struct irq_data *d = &desc->irq_data;
if (d->node == cpu) {
unsigned int newcpu = cpumask_any_and(d->affinity,
cpu_online_mask);
if (newcpu >= nr_cpu_ids) {
if (printk_ratelimit())
printk(KERN_INFO "IRQ%u no longer affine to CPU%u\n",
i, cpu);
cpumask_setall(desc->affinity);
newcpu = cpumask_any_and(desc->affinity,
cpumask_setall(d->affinity);
newcpu = cpumask_any_and(d->affinity,
cpu_online_mask);
}

18
arch/arm/mach-aaec2000/core.c
View File

@ -68,25 +68,25 @@ void __init aaec2000_map_io(void)
/*
* Interrupt handling routines
*/
static void aaec2000_int_ack(unsigned int irq)
static void aaec2000_int_ack(struct irq_data *d)
{
IRQ_INTSR = 1 << irq;
IRQ_INTSR = 1 << d->irq;
}
static void aaec2000_int_mask(unsigned int irq)
static void aaec2000_int_mask(struct irq_data *d)
{
IRQ_INTENC |= (1 << irq);
IRQ_INTENC |= (1 << d->irq);
}
static void aaec2000_int_unmask(unsigned int irq)
static void aaec2000_int_unmask(struct irq_data *d)
{
IRQ_INTENS |= (1 << irq);
IRQ_INTENS |= (1 << d->irq);
}
static struct irq_chip aaec2000_irq_chip = {
.ack = aaec2000_int_ack,
.mask = aaec2000_int_mask,
.unmask = aaec2000_int_unmask,
.irq_ack = aaec2000_int_ack,
.irq_mask = aaec2000_int_mask,
.irq_unmask = aaec2000_int_unmask,
};
void __init aaec2000_init_irq(void)

13
arch/arm/mach-at91/Kconfig
View File

@ -362,6 +362,12 @@ config MACH_CPU9G20
Select this if you are using a Eukrea Electromatique's
CPU9G20 Board <http://www.eukrea.com/>
config MACH_ACMENETUSFOXG20
bool "Acme Systems srl FOX Board G20"
help
Select this if you are using Acme Systems
FOX Board G20 <http://www.acmesystems.it>
config MACH_PORTUXG20
bool "taskit PortuxG20"
help
@ -381,6 +387,13 @@ config MACH_PCONTROL_G20
Select this if you are using taskit's Stamp9G20 CPU module on this
carrier board, beeing the decentralized unit of a building automation
system; featuring nvram, eth-switch, iso-rs485, display, io
config MACH_GSIA18S
bool "GS_IA18_S board"
help
This enables support for the GS_IA18_S board
produced by GeoSIG Ltd company. This is an internet accelerograph.
<http://www.geosig.com>
endif
if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)

2
arch/arm/mach-at91/Makefile
View File

@ -63,9 +63,11 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
# AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
obj-$(CONFIG_MACH_ACMENETUSFOXG20) += board-foxg20.o
obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o
# AT91SAM9260/AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o

274
arch/arm/mach-at91/board-foxg20.c Normal file
View File

@ -0,0 +1,274 @@
/*
* Copyright (C) 2005 SAN People
* Copyright (C) 2008 Atmel
* Copyright (C) 2010 Lee McLoughlin - lee@lmmrtech.com
* Copyright (C) 2010 Sergio Tanzilli - tanzilli@acmesystems.it
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/at73c213.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/clk.h>
#include <linux/w1-gpio.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include "sam9_smc.h"
#include "generic.h"
/*
* The FOX Board G20 hardware comes as the "Netus G20" board with
* just the cpu, ram, dataflash and two header connectors.
* This is plugged into the FOX Board which provides the ethernet,
* usb, rtc, leds, switch, ...
*
* For more info visit: http://www.acmesystems.it/foxg20
*/
static void __init foxg20_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91SAM9260_ID_US0, 1,
ATMEL_UART_CTS
| ATMEL_UART_RTS
| ATMEL_UART_DTR
| ATMEL_UART_DSR
| ATMEL_UART_DCD
| ATMEL_UART_RI);
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
at91_register_uart(AT91SAM9260_ID_US1, 2,
ATMEL_UART_CTS
| ATMEL_UART_RTS);
/* USART2 on ttyS3. (Rx & Tx only) */
at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
/* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
at91_register_uart(AT91SAM9260_ID_US3, 4,
ATMEL_UART_CTS
| ATMEL_UART_RTS);
/* USART4 on ttyS5. (Rx & Tx only) */
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
/* USART5 on ttyS6. (Rx & Tx only) */
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
/* Set the internal pull-up resistor on DRXD */
at91_set_A_periph(AT91_PIN_PB14, 1);
}
static void __init foxg20_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
static struct at91_usbh_data __initdata foxg20_usbh_data = {
.ports = 2,
};
/*
* USB Device port
*/
static struct at91_udc_data __initdata foxg20_udc_data = {
.vbus_pin = AT91_PIN_PC6,
.pullup_pin = 0, /* pull-up driven by UDC */
};
/*
* SPI devices.
*/
static struct spi_board_info foxg20_spi_devices[] = {
#if !defined(CONFIG_MMC_AT91)
{
.modalias = "mtd_dataflash",
.chip_select = 1,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#endif
};
/*
* MACB Ethernet device
*/
static struct at91_eth_data __initdata foxg20_macb_data = {
.phy_irq_pin = AT91_PIN_PA7,
.is_rmii = 1,
};
/*
* MCI (SD/MMC)
* det_pin, wp_pin and vcc_pin are not connected
*/
static struct at91_mmc_data __initdata foxg20_mmc_data = {
.slot_b = 1,
.wire4 = 1,
};
/*
* LEDs
*/
static struct gpio_led foxg20_leds[] = {
{ /* user led, red */
.name = "user_led",
.gpio = AT91_PIN_PC7,
.active_low = 0,
.default_trigger = "heartbeat",
},
};
/*
* GPIO Buttons
*/
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
static struct gpio_keys_button foxg20_buttons[] = {
{
.gpio = AT91_PIN_PC4,
.code = BTN_1,
.desc = "Button 1",
.active_low = 1,
.wakeup = 1,
},
};
static struct gpio_keys_platform_data foxg20_button_data = {
.buttons = foxg20_buttons,
.nbuttons = ARRAY_SIZE(foxg20_buttons),
};
static struct platform_device foxg20_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &foxg20_button_data,
}
};
static void __init foxg20_add_device_buttons(void)
{
at91_set_gpio_input(AT91_PIN_PC4, 1); /* btn1 */
at91_set_deglitch(AT91_PIN_PC4, 1);
platform_device_register(&foxg20_button_device);
}
#else
static void __init foxg20_add_device_buttons(void) {}
#endif
#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
static struct w1_gpio_platform_data w1_gpio_pdata = {
/* If you choose to use a pin other than PB16 it needs to be 3.3V */
.pin = AT91_PIN_PB16,
.is_open_drain = 1,
};
static struct platform_device w1_device = {
.name = "w1-gpio",
.id = -1,
.dev.platform_data = &w1_gpio_pdata,
};
static void __init at91_add_device_w1(void)
{
at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
at91_set_multi_drive(w1_gpio_pdata.pin, 1);
platform_device_register(&w1_device);
}
#endif
static struct i2c_board_info __initdata foxg20_i2c_devices[] = {
{
I2C_BOARD_INFO("24c512", 0x50),
},
};
static void __init foxg20_board_init(void)
{
/* Serial */
at91_add_device_serial();
/* USB Host */
at91_add_device_usbh(&foxg20_usbh_data);
/* USB Device */
at91_add_device_udc(&foxg20_udc_data);
/* SPI */
at91_add_device_spi(foxg20_spi_devices, ARRAY_SIZE(foxg20_spi_devices));
/* Ethernet */
at91_add_device_eth(&foxg20_macb_data);
/* MMC */
at91_add_device_mmc(0, &foxg20_mmc_data);
/* I2C */
at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices));
/* LEDs */
at91_gpio_leds(foxg20_leds, ARRAY_SIZE(foxg20_leds));
/* Push Buttons */
foxg20_add_device_buttons();
#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
at91_add_device_w1();
#endif
}
MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
/* Maintainer: Sergio Tanzilli */
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = foxg20_map_io,
.init_irq = foxg20_init_irq,
.init_machine = foxg20_board_init,
MACHINE_END

584
arch/arm/mach-at91/board-gsia18s.c Normal file
View File

@ -0,0 +1,584 @@
/*
* Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de>
* taskit GmbH
* 2010 Igor Plyatov <plyatov@gmail.com>
* GeoSIG Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/w1-gpio.h>
#include <linux/i2c.h>
#include <linux/i2c/pcf857x.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <mach/gsia18s.h>
#include <mach/stamp9g20.h>
#include "sam9_smc.h"
#include "generic.h"
static void __init gsia18s_map_io(void)
{
stamp9g20_map_io();
/*
* USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
* Used for Internal Analog Modem.
*/
at91_register_uart(AT91SAM9260_ID_US0, 1,
ATMEL_UART_CTS | ATMEL_UART_RTS |
ATMEL_UART_DTR | ATMEL_UART_DSR |
ATMEL_UART_DCD | ATMEL_UART_RI);
/*
* USART1 on ttyS2 (Rx, Tx, CTS, RTS).
* Used for GPS or WiFi or Data stream.
*/
at91_register_uart(AT91SAM9260_ID_US1, 2,
ATMEL_UART_CTS | ATMEL_UART_RTS);
/*
* USART2 on ttyS3 (Rx, Tx, CTS, RTS).
* Used for External Modem.
*/
at91_register_uart(AT91SAM9260_ID_US2, 3,
ATMEL_UART_CTS | ATMEL_UART_RTS);
/*
* USART3 on ttyS4 (Rx, Tx, RTS).
* Used for RS-485.
*/
at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS);
/*
* USART4 on ttyS5 (Rx, Tx).
* Used for TRX433 Radio Module.
*/
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
}
static void __init init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* Two USB Host ports
*/
static struct at91_usbh_data __initdata usbh_data = {
.ports = 2,
};
/*
* USB Device port
*/
static struct at91_udc_data __initdata udc_data = {
.vbus_pin = AT91_PIN_PA22,
.pullup_pin = 0, /* pull-up driven by UDC */
};
/*
* MACB Ethernet device
*/
static struct at91_eth_data __initdata macb_data = {
.phy_irq_pin = AT91_PIN_PA28,
.is_rmii = 1,
};
/*
* LEDs and GPOs
*/
static struct gpio_led gpio_leds[] = {
{
.name = "gpo:spi1reset",
.gpio = AT91_PIN_PC1,
.active_low = 0,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{
.name = "gpo:trig_net_out",
.gpio = AT91_PIN_PB20,
.active_low = 0,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{
.name = "gpo:trig_net_dir",
.gpio = AT91_PIN_PB19,
.active_low = 0,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{
.name = "gpo:charge_dis",
.gpio = AT91_PIN_PC2,
.active_low = 0,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{
.name = "led:event",
.gpio = AT91_PIN_PB17,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{
.name = "led:lan",
.gpio = AT91_PIN_PB18,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{
.name = "led:error",
.gpio = AT91_PIN_PB16,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device leds = {
.name = "leds-gpio",
.id = 0,
.dev = {
.platform_data = &gpio_led_info,
}
};
static void __init gsia18s_leds_init(void)
{
platform_device_register(&leds);
}
/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
static struct gpio_led pcf_gpio_leds1[] = {
{ /* bit 0 */
.name = "gpo:hdc_power",
.gpio = PCF_GPIO_HDC_POWER,
.active_low = 0,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{ /* bit 1 */
.name = "gpo:wifi_setup",
.gpio = PCF_GPIO_WIFI_SETUP,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{ /* bit 2 */
.name = "gpo:wifi_enable",
.gpio = PCF_GPIO_WIFI_ENABLE,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{ /* bit 3 */
.name = "gpo:wifi_reset",
.gpio = PCF_GPIO_WIFI_RESET,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
/* bit 4 used as GPI */
{ /* bit 5 */
.name = "gpo:gps_setup",
.gpio = PCF_GPIO_GPS_SETUP,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{ /* bit 6 */
.name = "gpo:gps_standby",
.gpio = PCF_GPIO_GPS_STANDBY,
.active_low = 0,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{ /* bit 7 */
.name = "gpo:gps_power",
.gpio = PCF_GPIO_GPS_POWER,
.active_low = 0,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
}
};
static struct gpio_led_platform_data pcf_gpio_led_info1 = {
.leds = pcf_gpio_leds1,
.num_leds = ARRAY_SIZE(pcf_gpio_leds1),
};
static struct platform_device pcf_leds1 = {
.name = "leds-gpio", /* GS_IA18-CB_board */
.id = 1,
.dev = {
.platform_data = &pcf_gpio_led_info1,
}
};
/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
static struct gpio_led pcf_gpio_leds2[] = {
{ /* bit 0 */
.name = "gpo:alarm_1",
.gpio = PCF_GPIO_ALARM1,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{ /* bit 1 */
.name = "gpo:alarm_2",
.gpio = PCF_GPIO_ALARM2,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{ /* bit 2 */
.name = "gpo:alarm_3",
.gpio = PCF_GPIO_ALARM3,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{ /* bit 3 */
.name = "gpo:alarm_4",
.gpio = PCF_GPIO_ALARM4,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
/* bits 4, 5, 6 not used */
{ /* bit 7 */
.name = "gpo:alarm_v_relay_on",
.gpio = PCF_GPIO_ALARM_V_RELAY_ON,
.active_low = 0,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
};
static struct gpio_led_platform_data pcf_gpio_led_info2 = {
.leds = pcf_gpio_leds2,
.num_leds = ARRAY_SIZE(pcf_gpio_leds2),
};
static struct platform_device pcf_leds2 = {
.name = "leds-gpio",
.id = 2,
.dev = {
.platform_data = &pcf_gpio_led_info2,
}
};
/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
static struct gpio_led pcf_gpio_leds3[] = {
{ /* bit 0 */
.name = "gpo:modem_power",
.gpio = PCF_GPIO_MODEM_POWER,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
/* bits 1 and 2 not used */
{ /* bit 3 */
.name = "gpo:modem_reset",
.gpio = PCF_GPIO_MODEM_RESET,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
/* bits 4, 5 and 6 not used */
{ /* bit 7 */
.name = "gpo:trx_reset",
.gpio = PCF_GPIO_TRX_RESET,
.active_low = 1,
.default_trigger = "none",
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
static struct gpio_led_platform_data pcf_gpio_led_info3 = {
.leds = pcf_gpio_leds3,
.num_leds = ARRAY_SIZE(pcf_gpio_leds3),
};
static struct platform_device pcf_leds3 = {
.name = "leds-gpio",
.id = 3,
.dev = {
.platform_data = &pcf_gpio_led_info3,
}
};
static void __init gsia18s_pcf_leds_init(void)
{
platform_device_register(&pcf_leds1);
platform_device_register(&pcf_leds2);
platform_device_register(&pcf_leds3);
}
/*
* SPI busses.
*/
static struct spi_board_info gsia18s_spi_devices[] = {
{ /* User accessible spi0, cs0 used for communication with MSP RTC */
.modalias = "spidev",
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 580000,
.mode = SPI_MODE_1,
},
{ /* User accessible spi1, cs0 used for communication with int. DSP */
.modalias = "spidev",
.bus_num = 1,
.chip_select = 0,
.max_speed_hz = 5600000,
.mode = SPI_MODE_0,
},
{ /* User accessible spi1, cs1 used for communication with ext. DSP */
.modalias = "spidev",
.bus_num = 1,
.chip_select = 1,
.max_speed_hz = 5600000,
.mode = SPI_MODE_0,
},
{ /* User accessible spi1, cs2 used for communication with ext. DSP */
.modalias = "spidev",
.bus_num = 1,
.chip_select = 2,
.max_speed_hz = 5600000,
.mode = SPI_MODE_0,
},
{ /* User accessible spi1, cs3 used for communication with ext. DSP */
.modalias = "spidev",
.bus_num = 1,
.chip_select = 3,
.max_speed_hz = 5600000,
.mode = SPI_MODE_0,
}
};
/*
* GPI Buttons
*/
static struct gpio_keys_button buttons[] = {
{
.gpio = GPIO_TRIG_NET_IN,
.code = BTN_1,
.desc = "TRIG_NET_IN",
.type = EV_KEY,
.active_low = 0,
.wakeup = 1,
},
{ /* SW80 on the GS_IA18_S-MN board*/
.gpio = GPIO_CARD_UNMOUNT_0,
.code = BTN_2,
.desc = "Card umount 0",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
},
{ /* SW79 on the GS_IA18_S-MN board*/
.gpio = GPIO_CARD_UNMOUNT_1,
.code = BTN_3,
.desc = "Card umount 1",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
},
{ /* SW280 on the GS_IA18-CB board*/
.gpio = GPIO_KEY_POWER,
.code = KEY_POWER,
.desc = "Power Off Button",
.type = EV_KEY,
.active_low = 0,
.wakeup = 1,
}
};
static struct gpio_keys_platform_data button_data = {
.buttons = buttons,
.nbuttons = ARRAY_SIZE(buttons),
};
static struct platform_device button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &button_data,
}
};
static void __init gsia18s_add_device_buttons(void)
{
at91_set_gpio_input(GPIO_TRIG_NET_IN, 1);
at91_set_deglitch(GPIO_TRIG_NET_IN, 1);
at91_set_gpio_input(GPIO_CARD_UNMOUNT_0, 1);
at91_set_deglitch(GPIO_CARD_UNMOUNT_0, 1);
at91_set_gpio_input(GPIO_CARD_UNMOUNT_1, 1);
at91_set_deglitch(GPIO_CARD_UNMOUNT_1, 1);
at91_set_gpio_input(GPIO_KEY_POWER, 0);
at91_set_deglitch(GPIO_KEY_POWER, 1);
platform_device_register(&button_device);
}
/*
* I2C
*/
static int pcf8574x_0x20_setup(struct i2c_client *client, int gpio,
unsigned int ngpio, void *context)
{
int status;
status = gpio_request(gpio + PCF_GPIO_ETH_DETECT, "eth_det");
if (status < 0) {
pr_err("error: can't request GPIO%d\n",
gpio + PCF_GPIO_ETH_DETECT);
return status;
}
status = gpio_direction_input(gpio + PCF_GPIO_ETH_DETECT);
if (status < 0) {
pr_err("error: can't setup GPIO%d as input\n",
gpio + PCF_GPIO_ETH_DETECT);
return status;
}
status = gpio_export(gpio + PCF_GPIO_ETH_DETECT, false);
if (status < 0) {
pr_err("error: can't export GPIO%d\n",
gpio + PCF_GPIO_ETH_DETECT);
return status;
}
status = gpio_sysfs_set_active_low(gpio + PCF_GPIO_ETH_DETECT, 1);
if (status < 0) {
pr_err("error: gpio_sysfs_set active_low(GPIO%d, 1)\n",
gpio + PCF_GPIO_ETH_DETECT);
return status;
}
return 0;
}
static int pcf8574x_0x20_teardown(struct i2c_client *client, int gpio,
unsigned ngpio, void *context)
{
gpio_free(gpio + PCF_GPIO_ETH_DETECT);
return 0;
}
static struct pcf857x_platform_data pcf20_pdata = {
.gpio_base = GS_IA18_S_PCF_GPIO_BASE0,
.n_latch = (1 << 4),
.setup = pcf8574x_0x20_setup,
.teardown = pcf8574x_0x20_teardown,
};
static struct pcf857x_platform_data pcf22_pdata = {
.gpio_base = GS_IA18_S_PCF_GPIO_BASE1,
};
static struct pcf857x_platform_data pcf24_pdata = {
.gpio_base = GS_IA18_S_PCF_GPIO_BASE2,
};
static struct i2c_board_info __initdata gsia18s_i2c_devices[] = {
{ /* U1 on the GS_IA18-CB_V3 board */
I2C_BOARD_INFO("pcf8574", 0x20),
.platform_data = &pcf20_pdata,
},
{ /* U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
I2C_BOARD_INFO("pcf8574", 0x22),
.platform_data = &pcf22_pdata,
},
{ /* U1 on the GS_2G-OPT23-A_V0 board (Modem) */
I2C_BOARD_INFO("pcf8574", 0x24),
.platform_data = &pcf24_pdata,
},
{ /* U161 on the GS_IA18_S-MN board */
I2C_BOARD_INFO("24c1024", 0x50),
},
{ /* U162 on the GS_IA18_S-MN board */
I2C_BOARD_INFO("24c01", 0x53),
},
};
/*
* Compact Flash
*/
static struct at91_cf_data __initdata gsia18s_cf1_data = {
.irq_pin = AT91_PIN_PA27,
.det_pin = AT91_PIN_PB30,
.rst_pin = AT91_PIN_PB31,
.chipselect = 5,
.flags = AT91_CF_TRUE_IDE,
};
/* Power Off by RTC */
static void gsia18s_power_off(void)
{
pr_notice("Power supply will be switched off automatically now or after 60 seconds without ArmDAS.\n");
at91_set_gpio_output(AT91_PIN_PA25, 1);
/* Spin to death... */
while (1)
;
}
static int __init gsia18s_power_off_init(void)
{
pm_power_off = gsia18s_power_off;
return 0;
}
/* ---------------------------------------------------------------------------*/
static void __init gsia18s_board_init(void)
{
stamp9g20_board_init();
at91_add_device_usbh(&usbh_data);
at91_add_device_udc(&udc_data);
at91_add_device_eth(&macb_data);
gsia18s_leds_init();
gsia18s_pcf_leds_init();
gsia18s_add_device_buttons();
at91_add_device_i2c(gsia18s_i2c_devices,
ARRAY_SIZE(gsia18s_i2c_devices));
at91_add_device_cf(&gsia18s_cf1_data);
at91_add_device_spi(gsia18s_spi_devices,
ARRAY_SIZE(gsia18s_spi_devices));
gsia18s_power_off_init();
}
MACHINE_START(GSIA18S, "GS_IA18_S")
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = gsia18s_map_io,
.init_irq = init_irq,
.init_machine = gsia18s_board_init,
MACHINE_END

1
arch/arm/mach-at91/board-sam9m10g45ek.c
View File

@ -37,7 +37,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/board.h>
#include <mach/gpio.h>
#include <mach/at91sam9_smc.h>

34
arch/arm/mach-at91/gpio.c
View File

@ -274,10 +274,10 @@ EXPORT_SYMBOL(at91_get_gpio_value);
static u32 wakeups[MAX_GPIO_BANKS];
static u32 backups[MAX_GPIO_BANKS];
static int gpio_irq_set_wake(unsigned pin, unsigned state)
static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
{
unsigned mask = pin_to_mask(pin);
unsigned bank = (pin - PIN_BASE) / 32;
unsigned mask = pin_to_mask(d->irq);
unsigned bank = (d->irq - PIN_BASE) / 32;
if (unlikely(bank >= MAX_GPIO_BANKS))
return -EINVAL;
@ -344,25 +344,25 @@ void at91_gpio_resume(void)
* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
*/
static void gpio_irq_mask(unsigned pin)
static void gpio_irq_mask(struct irq_data *d)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
void __iomem *pio = pin_to_controller(d->irq);
unsigned mask = pin_to_mask(d->irq);
if (pio)
__raw_writel(mask, pio + PIO_IDR);
}
static void gpio_irq_unmask(unsigned pin)
static void gpio_irq_unmask(struct irq_data *d)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
void __iomem *pio = pin_to_controller(d->irq);
unsigned mask = pin_to_mask(d->irq);
if (pio)
__raw_writel(mask, pio + PIO_IER);
}
static int gpio_irq_type(unsigned pin, unsigned type)
static int gpio_irq_type(struct irq_data *d, unsigned type)
{
switch (type) {
case IRQ_TYPE_NONE:
@ -375,10 +375,10 @@ static int gpio_irq_type(unsigned pin, unsigned type)
static struct irq_chip gpio_irqchip = {
.name = "GPIO",
.mask = gpio_irq_mask,
.unmask = gpio_irq_unmask,
.set_type = gpio_irq_type,
.set_wake = gpio_irq_set_wake,
.irq_mask = gpio_irq_mask,
.irq_unmask = gpio_irq_unmask,
.irq_set_type = gpio_irq_type,
.irq_set_wake = gpio_irq_set_wake,
};
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
@ -393,7 +393,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
pio = at91_gpio->regbase;
/* temporarily mask (level sensitive) parent IRQ */
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
for (;;) {
/* Reading ISR acks pending (edge triggered) GPIO interrupts.
* When there none are pending, we're finished unless we need
@ -419,7 +419,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
* another IRQ must be generated before it actually gets
* here to be disabled on the GPIO controller.
*/
gpio_irq_mask(pin);
gpio_irq_mask(irq_get_irq_data(pin));
}
else
generic_handle_irq(pin);
@ -429,7 +429,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
isr >>= 1;
}
}
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
/* now it may re-trigger */
}

33
arch/arm/mach-at91/include/mach/gsia18s.h Normal file
View File

@ -0,0 +1,33 @@
/* Buttons */
#define GPIO_TRIG_NET_IN AT91_PIN_PB21
#define GPIO_CARD_UNMOUNT_0 AT91_PIN_PB13
#define GPIO_CARD_UNMOUNT_1 AT91_PIN_PB12
#define GPIO_KEY_POWER AT91_PIN_PA25
/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
#define GS_IA18_S_PCF_GPIO_BASE0 NR_BUILTIN_GPIO
#define PCF_GPIO_HDC_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 0)
#define PCF_GPIO_WIFI_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 1)
#define PCF_GPIO_WIFI_ENABLE (GS_IA18_S_PCF_GPIO_BASE0 + 2)
#define PCF_GPIO_WIFI_RESET (GS_IA18_S_PCF_GPIO_BASE0 + 3)
#define PCF_GPIO_ETH_DETECT 4 /* this is a GPI */
#define PCF_GPIO_GPS_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 5)
#define PCF_GPIO_GPS_STANDBY (GS_IA18_S_PCF_GPIO_BASE0 + 6)
#define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7)
/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
#define GS_IA18_S_PCF_GPIO_BASE1 (GS_IA18_S_PCF_GPIO_BASE0 + 8)
#define PCF_GPIO_ALARM1 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
#define PCF_GPIO_ALARM2 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
#define PCF_GPIO_ALARM3 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
#define PCF_GPIO_ALARM4 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
/* bits 4, 5, 6 not used */
#define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7)
/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
#define GS_IA18_S_PCF_GPIO_BASE2 (GS_IA18_S_PCF_GPIO_BASE1 + 8)
#define PCF_GPIO_MODEM_POWER (GS_IA18_S_PCF_GPIO_BASE2 + 0)
#define PCF_GPIO_MODEM_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 3)
/* bits 1, 2, 4, 5 not used */
#define PCF_GPIO_TRX_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 6)
/* bit 7 not used */

36
arch/arm/mach-at91/irq.c
View File

@ -34,23 +34,23 @@
#include <asm/mach/map.h>
static void at91_aic_mask_irq(unsigned int irq)
static void at91_aic_mask_irq(struct irq_data *d)
{
/* Disable interrupt on AIC */
at91_sys_write(AT91_AIC_IDCR, 1 << irq);
at91_sys_write(AT91_AIC_IDCR, 1 << d->irq);
}
static void at91_aic_unmask_irq(unsigned int irq)
static void at91_aic_unmask_irq(struct irq_data *d)
{
/* Enable interrupt on AIC */
at91_sys_write(AT91_AIC_IECR, 1 << irq);
at91_sys_write(AT91_AIC_IECR, 1 << d->irq);
}
unsigned int at91_extern_irq;
#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
static int at91_aic_set_type(unsigned irq, unsigned type)
static int at91_aic_set_type(struct irq_data *d, unsigned type)
{
unsigned int smr, srctype;
@ -62,13 +62,13 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
srctype = AT91_AIC_SRCTYPE_RISING;
break;
case IRQ_TYPE_LEVEL_LOW:
if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */
srctype = AT91_AIC_SRCTYPE_LOW;
else
return -EINVAL;
break;
case IRQ_TYPE_EDGE_FALLING:
if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */
srctype = AT91_AIC_SRCTYPE_FALLING;
else
return -EINVAL;
@ -77,8 +77,8 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
return -EINVAL;
}
smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
smr = at91_sys_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
at91_sys_write(AT91_AIC_SMR(d->irq), smr | srctype);
return 0;
}
@ -87,15 +87,15 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
static u32 wakeups;
static u32 backups;
static int at91_aic_set_wake(unsigned irq, unsigned value)
static int at91_aic_set_wake(struct irq_data *d, unsigned value)
{
if (unlikely(irq >= 32))
if (unlikely(d->irq >= 32))
return -EINVAL;
if (value)
wakeups |= (1 << irq);
wakeups |= (1 << d->irq);
else
wakeups &= ~(1 << irq);
wakeups &= ~(1 << d->irq);
return 0;
}
@ -119,11 +119,11 @@ void at91_irq_resume(void)
static struct irq_chip at91_aic_chip = {
.name = "AIC",
.ack = at91_aic_mask_irq,
.mask = at91_aic_mask_irq,
.unmask = at91_aic_unmask_irq,
.set_type = at91_aic_set_type,
.set_wake = at91_aic_set_wake,
.irq_ack = at91_aic_mask_irq,
.irq_mask = at91_aic_mask_irq,
.irq_unmask = at91_aic_unmask_irq,
.irq_set_type = at91_aic_set_type,
.irq_set_wake = at91_aic_set_wake,
};
/*

42
arch/arm/mach-bcmring/irq.c
View File

@ -30,61 +30,61 @@
#include <mach/csp/intcHw_reg.h>
#include <mach/csp/mm_io.h>
static void bcmring_mask_irq0(unsigned int irq)
static void bcmring_mask_irq0(struct irq_data *d)
{
writel(1 << (irq - IRQ_INTC0_START),
writel(1 << (d->irq - IRQ_INTC0_START),
MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
}
static void bcmring_unmask_irq0(unsigned int irq)
static void bcmring_unmask_irq0(struct irq_data *d)
{
writel(1 << (irq - IRQ_INTC0_START),
writel(1 << (d->irq - IRQ_INTC0_START),
MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
}
static void bcmring_mask_irq1(unsigned int irq)
static void bcmring_mask_irq1(struct irq_data *d)
{
writel(1 << (irq - IRQ_INTC1_START),
writel(1 << (d->irq - IRQ_INTC1_START),
MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
}
static void bcmring_unmask_irq1(unsigned int irq)
static void bcmring_unmask_irq1(struct irq_data *d)
{
writel(1 << (irq - IRQ_INTC1_START),
writel(1 << (d->irq - IRQ_INTC1_START),
MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
}
static void bcmring_mask_irq2(unsigned int irq)
static void bcmring_mask_irq2(struct irq_data *d)
{
writel(1 << (irq - IRQ_SINTC_START),
writel(1 << (d->irq - IRQ_SINTC_START),
MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
}
static void bcmring_unmask_irq2(unsigned int irq)
static void bcmring_unmask_irq2(struct irq_data *d)
{
writel(1 << (irq - IRQ_SINTC_START),
writel(1 << (d->irq - IRQ_SINTC_START),
MM_IO_BASE_SINTC + INTCHW_INTENABLE);
}
static struct irq_chip bcmring_irq0_chip = {
.name = "ARM-INTC0",
.ack = bcmring_mask_irq0,
.mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */
.unmask = bcmring_unmask_irq0, /* unmaks an interrupt */
.irq_ack = bcmring_mask_irq0,
.irq_mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */
.irq_unmask = bcmring_unmask_irq0, /* unmaks an interrupt */
};
static struct irq_chip bcmring_irq1_chip = {
.name = "ARM-INTC1",
.ack = bcmring_mask_irq1,
.mask = bcmring_mask_irq1,
.unmask = bcmring_unmask_irq1,
.irq_ack = bcmring_mask_irq1,
.irq_mask = bcmring_mask_irq1,
.irq_unmask = bcmring_unmask_irq1,
};
static struct irq_chip bcmring_irq2_chip = {
.name = "ARM-SINTC",
.ack = bcmring_mask_irq2,
.mask = bcmring_mask_irq2,
.unmask = bcmring_unmask_irq2,
.irq_ack = bcmring_mask_irq2,
.irq_mask = bcmring_mask_irq2,
.irq_unmask = bcmring_unmask_irq2,
};
static void vic_init(void __iomem *base, struct irq_chip *chip,

40
arch/arm/mach-clps711x/irq.c
View File

@ -27,24 +27,24 @@
#include <asm/hardware/clps7111.h>
static void int1_mask(unsigned int irq)
static void int1_mask(struct irq_data *d)
{
u32 intmr1;
intmr1 = clps_readl(INTMR1);
intmr1 &= ~(1 << irq);
intmr1 &= ~(1 << d->irq);
clps_writel(intmr1, INTMR1);
}
static void int1_ack(unsigned int irq)
static void int1_ack(struct irq_data *d)
{
u32 intmr1;
intmr1 = clps_readl(INTMR1);
intmr1 &= ~(1 << irq);
intmr1 &= ~(1 << d->irq);
clps_writel(intmr1, INTMR1);
switch (irq) {
switch (d->irq) {
case IRQ_CSINT: clps_writel(0, COEOI); break;
case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
@ -54,56 +54,56 @@ static void int1_ack(unsigned int irq)
}
}
static void int1_unmask(unsigned int irq)
static void int1_unmask(struct irq_data *d)
{
u32 intmr1;
intmr1 = clps_readl(INTMR1);
intmr1 |= 1 << irq;
intmr1 |= 1 << d->irq;
clps_writel(intmr1, INTMR1);
}
static struct irq_chip int1_chip = {
.ack = int1_ack,
.mask = int1_mask,
.unmask = int1_unmask,
.irq_ack = int1_ack,
.irq_mask = int1_mask,
.irq_unmask = int1_unmask,
};
static void int2_mask(unsigned int irq)
static void int2_mask(struct irq_data *d)
{
u32 intmr2;
intmr2 = clps_readl(INTMR2);
intmr2 &= ~(1 << (irq - 16));
intmr2 &= ~(1 << (d->irq - 16));
clps_writel(intmr2, INTMR2);
}
static void int2_ack(unsigned int irq)
static void int2_ack(struct irq_data *d)
{
u32 intmr2;
intmr2 = clps_readl(INTMR2);
intmr2 &= ~(1 << (irq - 16));
intmr2 &= ~(1 << (d->irq - 16));
clps_writel(intmr2, INTMR2);
switch (irq) {
switch (d->irq) {
case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
}
}
static void int2_unmask(unsigned int irq)
static void int2_unmask(struct irq_data *d)
{
u32 intmr2;
intmr2 = clps_readl(INTMR2);
intmr2 |= 1 << (irq - 16);
intmr2 |= 1 << (d->irq - 16);
clps_writel(intmr2, INTMR2);
}
static struct irq_chip int2_chip = {
.ack = int2_ack,
.mask = int2_mask,
.unmask = int2_unmask,
.irq_ack = int2_ack,
.irq_mask = int2_mask,
.irq_unmask = int2_unmask,
};
void __init clps711x_init_irq(void)

30
arch/arm/mach-davinci/cp_intc.c
View File

@ -26,30 +26,30 @@ static inline void cp_intc_write(unsigned long value, unsigned offset)
__raw_writel(value, davinci_intc_base + offset);
}
static void cp_intc_ack_irq(unsigned int irq)
static void cp_intc_ack_irq(struct irq_data *d)
{
cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR);
cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR);
}
/* Disable interrupt */
static void cp_intc_mask_irq(unsigned int irq)
static void cp_intc_mask_irq(struct irq_data *d)
{
/* XXX don't know why we need to disable nIRQ here... */
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR);
cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR);
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
}
/* Enable interrupt */
static void cp_intc_unmask_irq(unsigned int irq)
static void cp_intc_unmask_irq(struct irq_data *d)
{
cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET);
cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET);
}
static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
unsigned reg = BIT_WORD(irq);
unsigned mask = BIT_MASK(irq);
unsigned reg = BIT_WORD(d->irq);
unsigned mask = BIT_MASK(d->irq);
unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
@ -85,18 +85,18 @@ static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
* generic drivers which call {enable|disable}_irq_wake for
* wake up interrupt sources (eg RTC on DA850).
*/
static int cp_intc_set_wake(unsigned int irq, unsigned int on)
static int cp_intc_set_wake(struct irq_data *d, unsigned int on)
{
return 0;
}
static struct irq_chip cp_intc_irq_chip = {
.name = "cp_intc",
.ack = cp_intc_ack_irq,
.mask = cp_intc_mask_irq,
.unmask = cp_intc_unmask_irq,
.set_type = cp_intc_set_irq_type,
.set_wake = cp_intc_set_wake,
.irq_ack = cp_intc_ack_irq,
.irq_mask = cp_intc_mask_irq,
.irq_unmask = cp_intc_unmask_irq,
.irq_set_type = cp_intc_set_irq_type,
.irq_set_wake = cp_intc_set_wake,
};
void __init cp_intc_init(void)

46
arch/arm/mach-davinci/gpio.c
View File

@ -205,20 +205,20 @@ pure_initcall(davinci_gpio_setup);
* serve as EDMA event triggers.
*/
static void gpio_irq_disable(unsigned irq)
static void gpio_irq_disable(struct irq_data *d)
{
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
__raw_writel(mask, &g->clr_falling);
__raw_writel(mask, &g->clr_rising);
}
static void gpio_irq_enable(unsigned irq)
static void gpio_irq_enable(struct irq_data *d)
{
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
unsigned status = irq_desc[irq].status;
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
unsigned status = irq_desc[d->irq].status;
status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
if (!status)
@ -230,19 +230,19 @@ static void gpio_irq_enable(unsigned irq)
__raw_writel(mask, &g->set_rising);
}
static int gpio_irq_type(unsigned irq, unsigned trigger)
static int gpio_irq_type(struct irq_data *d, unsigned trigger)
{
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
irq_desc[irq].status |= trigger;
irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
irq_desc[d->irq].status |= trigger;
/* don't enable the IRQ if it's currently disabled */
if (irq_desc[irq].depth == 0) {
if (irq_desc[d->irq].depth == 0) {
__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
? &g->set_falling : &g->clr_falling);
__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
@ -253,9 +253,9 @@ static int gpio_irq_type(unsigned irq, unsigned trigger)
static struct irq_chip gpio_irqchip = {
.name = "GPIO",
.enable = gpio_irq_enable,
.disable = gpio_irq_disable,
.set_type = gpio_irq_type,
.irq_enable = gpio_irq_enable,
.irq_disable = gpio_irq_disable,
.irq_set_type = gpio_irq_type,
};
static void
@ -269,8 +269,8 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
mask <<= 16;
/* temporarily mask (level sensitive) parent IRQ */
desc->chip->mask(irq);
desc->chip->ack(irq);
desc->irq_data.chip->irq_mask(&desc->irq_data);
desc->irq_data.chip->irq_ack(&desc->irq_data);
while (1) {
u32 status;
int n;
@ -293,7 +293,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
status >>= res;
}
}
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
/* now it may re-trigger */
}
@ -320,10 +320,10 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
return -ENODEV;
}
static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
{
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
@ -397,7 +397,7 @@ static int __init davinci_gpio_irq_setup(void)
irq = bank_irq;
gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
gpio_irqchip_unbanked.name = "GPIO-AINTC";
gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
/* default trigger: both edges */
g = gpio2regs(0);

26
arch/arm/mach-davinci/irq.c
View File

@ -53,14 +53,14 @@ static inline void davinci_irq_writel(unsigned long value, int offset)
}
/* Disable interrupt */
static void davinci_mask_irq(unsigned int irq)
static void davinci_mask_irq(struct irq_data *d)
{
unsigned int mask;
u32 l;
mask = 1 << IRQ_BIT(irq);
mask = 1 << IRQ_BIT(d->irq);
if (irq > 31) {
if (d->irq > 31) {
l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
l &= ~mask;
davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
@ -72,14 +72,14 @@ static void davinci_mask_irq(unsigned int irq)
}
/* Enable interrupt */
static void davinci_unmask_irq(unsigned int irq)
static void davinci_unmask_irq(struct irq_data *d)
{
unsigned int mask;
u32 l;
mask = 1 << IRQ_BIT(irq);
mask = 1 << IRQ_BIT(d->irq);
if (irq > 31) {
if (d->irq > 31) {
l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
@ -91,23 +91,23 @@ static void davinci_unmask_irq(unsigned int irq)
}
/* EOI interrupt */
static void davinci_ack_irq(unsigned int irq)
static void davinci_ack_irq(struct irq_data *d)
{
unsigned int mask;
mask = 1 << IRQ_BIT(irq);
mask = 1 << IRQ_BIT(d->irq);
if (irq > 31)
if (d->irq > 31)
davinci_irq_writel(mask, IRQ_REG1_OFFSET);
else
davinci_irq_writel(mask, IRQ_REG0_OFFSET);
}
static struct irq_chip davinci_irq_chip_0 = {
.name = "AINTC",
.ack = davinci_ack_irq,
.mask = davinci_mask_irq,
.unmask = davinci_unmask_irq,
.name = "AINTC",
.irq_ack = davinci_ack_irq,
.irq_mask = davinci_mask_irq,
.irq_unmask = davinci_unmask_irq,
};
/* ARM Interrupt Controller Initialization */

18
arch/arm/mach-dove/irq.c
View File

@ -36,9 +36,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
}
}
static void pmu_irq_mask(unsigned int irq)
static void pmu_irq_mask(struct irq_data *d)
{
int pin = irq_to_pmu(irq);
int pin = irq_to_pmu(d->irq);
u32 u;
u = readl(PMU_INTERRUPT_MASK);
@ -46,9 +46,9 @@ static void pmu_irq_mask(unsigned int irq)
writel(u, PMU_INTERRUPT_MASK);
}
static void pmu_irq_unmask(unsigned int irq)
static void pmu_irq_unmask(struct irq_data *d)
{
int pin = irq_to_pmu(irq);
int pin = irq_to_pmu(d->irq);
u32 u;
u = readl(PMU_INTERRUPT_MASK);
@ -56,9 +56,9 @@ static void pmu_irq_unmask(unsigned int irq)
writel(u, PMU_INTERRUPT_MASK);
}
static void pmu_irq_ack(unsigned int irq)
static void pmu_irq_ack(struct irq_data *d)
{
int pin = irq_to_pmu(irq);
int pin = irq_to_pmu(d->irq);
u32 u;
u = ~(1 << (pin & 31));
@ -67,9 +67,9 @@ static void pmu_irq_ack(unsigned int irq)
static struct irq_chip pmu_irq_chip = {
.name = "pmu_irq",
.mask = pmu_irq_mask,
.unmask = pmu_irq_unmask,
.ack = pmu_irq_ack,
.irq_mask = pmu_irq_mask,
.irq_unmask = pmu_irq_unmask,
.irq_ack = pmu_irq_ack,
};
static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)

14
arch/arm/mach-ebsa110/core.c
View File

@ -35,20 +35,20 @@
#define IRQ_STAT 0xff000000 /* read */
#define IRQ_MCLR 0xff000000 /* write */
static void ebsa110_mask_irq(unsigned int irq)
static void ebsa110_mask_irq(struct irq_data *d)
{
__raw_writeb(1 << irq, IRQ_MCLR);
__raw_writeb(1 << d->irq, IRQ_MCLR);
}
static void ebsa110_unmask_irq(unsigned int irq)
static void ebsa110_unmask_irq(struct irq_data *d)
{
__raw_writeb(1 << irq, IRQ_MSET);
__raw_writeb(1 << d->irq, IRQ_MSET);
}
static struct irq_chip ebsa110_irq_chip = {
.ack = ebsa110_mask_irq,
.mask = ebsa110_mask_irq,
.unmask = ebsa110_unmask_irq,
.irq_ack = ebsa110_mask_irq,
.irq_mask = ebsa110_mask_irq,
.irq_unmask = ebsa110_unmask_irq,
};
static void __init ebsa110_init_irq(void)

36
arch/arm/mach-ep93xx/gpio.c
View File

@ -112,13 +112,13 @@ static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(gpio_irq);
}
static void ep93xx_gpio_irq_ack(unsigned int irq)
static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
int line = irq_to_gpio(irq);
int line = irq_to_gpio(d->irq);
int port = line >> 3;
int port_mask = 1 << (line & 7);
if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
ep93xx_gpio_update_int_params(port);
}
@ -126,13 +126,13 @@ static void ep93xx_gpio_irq_ack(unsigned int irq)
__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}
static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
int line = irq_to_gpio(irq);
int line = irq_to_gpio(d->irq);
int port = line >> 3;
int port_mask = 1 << (line & 7);
if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
gpio_int_unmasked[port] &= ~port_mask;
@ -141,18 +141,18 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}
static void ep93xx_gpio_irq_mask(unsigned int irq)
static void ep93xx_gpio_irq_mask(struct irq_data *d)
{
int line = irq_to_gpio(irq);
int line = irq_to_gpio(d->irq);
int port = line >> 3;
gpio_int_unmasked[port] &= ~(1 << (line & 7));
ep93xx_gpio_update_int_params(port);
}
static void ep93xx_gpio_irq_unmask(unsigned int irq)
static void ep93xx_gpio_irq_unmask(struct irq_data *d)
{
int line = irq_to_gpio(irq);
int line = irq_to_gpio(d->irq);
int port = line >> 3;
gpio_int_unmasked[port] |= 1 << (line & 7);
@ -164,10 +164,10 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq)
* edge (1) triggered, while gpio_int_type2 controls whether it
* triggers on low/falling (0) or high/rising (1).
*/
static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
{
struct irq_desc *desc = irq_desc + irq;
const int gpio = irq_to_gpio(irq);
struct irq_desc *desc = irq_desc + d->irq;
const int gpio = irq_to_gpio(d->irq);
const int port = gpio >> 3;
const int port_mask = 1 << (gpio & 7);
@ -220,11 +220,11 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
static struct irq_chip ep93xx_gpio_irq_chip = {
.name = "GPIO",
.ack = ep93xx_gpio_irq_ack,
.mask_ack = ep93xx_gpio_irq_mask_ack,
.mask = ep93xx_gpio_irq_mask,
.unmask = ep93xx_gpio_irq_unmask,
.set_type = ep93xx_gpio_irq_type,
.irq_ack = ep93xx_gpio_irq_ack,
.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
.irq_mask = ep93xx_gpio_irq_mask,
.irq_unmask = ep93xx_gpio_irq_unmask,
.irq_set_type = ep93xx_gpio_irq_type,
};
void __init ep93xx_gpio_init_irq(void)

14
arch/arm/mach-footbridge/common.c
View File

@ -75,20 +75,20 @@ static const int fb_irq_mask[] = {
IRQ_MASK_PCI_PERR, /* 19 */
};
static void fb_mask_irq(unsigned int irq)
static void fb_mask_irq(struct irq_data *d)
{
*CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(irq)];
*CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
}
static void fb_unmask_irq(unsigned int irq)
static void fb_unmask_irq(struct irq_data *d)
{
*CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
*CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
}
static struct irq_chip fb_chip = {
.ack = fb_mask_irq,
.mask = fb_mask_irq,
.unmask = fb_unmask_irq,
.irq_ack = fb_mask_irq,
.irq_mask = fb_mask_irq,
.irq_unmask = fb_unmask_irq,
};
static void __init __fb_init_irq(void)

36
arch/arm/mach-footbridge/isa-irq.c
View File

@ -30,61 +30,61 @@
#include "common.h"
static void isa_mask_pic_lo_irq(unsigned int irq)
static void isa_mask_pic_lo_irq(struct irq_data *d)
{
unsigned int mask = 1 << (irq & 7);
unsigned int mask = 1 << (d->irq & 7);
outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
}
static void isa_ack_pic_lo_irq(unsigned int irq)
static void isa_ack_pic_lo_irq(struct irq_data *d)
{
unsigned int mask = 1 << (irq & 7);
unsigned int mask = 1 << (d->irq & 7);
outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
outb(0x20, PIC_LO);
}
static void isa_unmask_pic_lo_irq(unsigned int irq)
static void isa_unmask_pic_lo_irq(struct irq_data *d)
{
unsigned int mask = 1 << (irq & 7);
unsigned int mask = 1 << (d->irq & 7);
outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
}
static struct irq_chip isa_lo_chip = {
.ack = isa_ack_pic_lo_irq,
.mask = isa_mask_pic_lo_irq,
.unmask = isa_unmask_pic_lo_irq,
.irq_ack = isa_ack_pic_lo_irq,
.irq_mask = isa_mask_pic_lo_irq,
.irq_unmask = isa_unmask_pic_lo_irq,
};
static void isa_mask_pic_hi_irq(unsigned int irq)
static void isa_mask_pic_hi_irq(struct irq_data *d)
{
unsigned int mask = 1 << (irq & 7);
unsigned int mask = 1 << (d->irq & 7);
outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
}
static void isa_ack_pic_hi_irq(unsigned int irq)
static void isa_ack_pic_hi_irq(struct irq_data *d)
{
unsigned int mask = 1 << (irq & 7);
unsigned int mask = 1 << (d->irq & 7);
outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
outb(0x62, PIC_LO);
outb(0x20, PIC_HI);
}
static void isa_unmask_pic_hi_irq(unsigned int irq)
static void isa_unmask_pic_hi_irq(struct irq_data *d)
{
unsigned int mask = 1 << (irq & 7);
unsigned int mask = 1 << (d->irq & 7);
outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
}
static struct irq_chip isa_hi_chip = {
.ack = isa_ack_pic_hi_irq,
.mask = isa_mask_pic_hi_irq,
.unmask = isa_unmask_pic_hi_irq,
.irq_ack = isa_ack_pic_hi_irq,
.irq_mask = isa_mask_pic_hi_irq,
.irq_unmask = isa_unmask_pic_hi_irq,
};
static void

26
arch/arm/mach-gemini/gpio.c
View File

@ -54,33 +54,33 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index,
__raw_writel(reg, base + GPIO_INT_EN);
}
static void gpio_ack_irq(unsigned int irq)
static void gpio_ack_irq(struct irq_data *d)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int base = GPIO_BASE(gpio / 32);
__raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
}
static void gpio_mask_irq(unsigned int irq)
static void gpio_mask_irq(struct irq_data *d)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 0);
}
static void gpio_unmask_irq(unsigned int irq)
static void gpio_unmask_irq(struct irq_data *d)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 1);
}
static int gpio_set_irq_type(unsigned int irq, unsigned int type)
static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int gpio_mask = 1 << (gpio % 32);
unsigned int base = GPIO_BASE(gpio / 32);
unsigned int reg_both, reg_level, reg_type;
@ -120,7 +120,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type)
__raw_writel(reg_level, base + GPIO_INT_LEVEL);
__raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
gpio_ack_irq(irq);
gpio_ack_irq(d->irq);
return 0;
}
@ -146,10 +146,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
static struct irq_chip gpio_irq_chip = {
.name = "GPIO",
.ack = gpio_ack_irq,
.mask = gpio_mask_irq,
.unmask = gpio_unmask_irq,
.set_type = gpio_set_irq_type,
.irq_ack = gpio_ack_irq,
.irq_mask = gpio_mask_irq,
.irq_unmask = gpio_unmask_irq,
.irq_set_type = gpio_set_irq_type,
};
static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,

20
arch/arm/mach-gemini/irq.c
View File

@ -32,34 +32,34 @@
#define FIQ_LEVEL(base_addr) (base_addr + 0x30)
#define FIQ_STATUS(base_addr) (base_addr + 0x34)
static void gemini_ack_irq(unsigned int irq)
static void gemini_ack_irq(struct irq_data *d)
{
__raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(1 << d->irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
}
static void gemini_mask_irq(unsigned int irq)
static void gemini_mask_irq(struct irq_data *d)
{
unsigned int mask;
mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
mask &= ~(1 << irq);
mask &= ~(1 << d->irq);
__raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
}
static void gemini_unmask_irq(unsigned int irq)
static void gemini_unmask_irq(struct irq_data *d)
{
unsigned int mask;
mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
mask |= (1 << irq);
mask |= (1 << d->irq);
__raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
}
static struct irq_chip gemini_irq_chip = {
.name = "INTC",
.ack = gemini_ack_irq,
.mask = gemini_mask_irq,
.unmask = gemini_unmask_irq,
.name = "INTC",
.irq_ack = gemini_ack_irq,
.irq_mask = gemini_mask_irq,
.irq_unmask = gemini_unmask_irq,
};
static struct resource irq_resource = {

38
arch/arm/mach-h720x/common.c
View File

@ -52,17 +52,17 @@ unsigned long h720x_gettimeoffset(void)
/*
* mask Global irq's
*/
static void mask_global_irq (unsigned int irq )
static void mask_global_irq(struct irq_data *d)
{
CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq);
}
/*
* unmask Global irq's
*/
static void unmask_global_irq (unsigned int irq )
static void unmask_global_irq(struct irq_data *d)
{
CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq);
}
@ -70,10 +70,10 @@ static void unmask_global_irq (unsigned int irq )
* ack GPIO irq's
* Ack only for edge triggered int's valid
*/
static void inline ack_gpio_irq(u32 irq)
static void inline ack_gpio_irq(struct irq_data *d)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
u32 bit = IRQ_TO_BIT(irq);
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
u32 bit = IRQ_TO_BIT(d->irq);
if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
CPU_REG (reg_base, GPIO_CLR) = bit;
}
@ -81,20 +81,20 @@ static void inline ack_gpio_irq(u32 irq)
/*
* mask GPIO irq's
*/
static void inline mask_gpio_irq(u32 irq)
static void inline mask_gpio_irq(struct irq_data *d)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
u32 bit = IRQ_TO_BIT(irq);
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
u32 bit = IRQ_TO_BIT(d->irq);
CPU_REG (reg_base, GPIO_MASK) &= ~bit;
}
/*
* unmask GPIO irq's
*/
static void inline unmask_gpio_irq(u32 irq)
static void inline unmask_gpio_irq(struct irq_data *d)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
u32 bit = IRQ_TO_BIT(irq);
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
u32 bit = IRQ_TO_BIT(d->irq);
CPU_REG (reg_base, GPIO_MASK) |= bit;
}
@ -170,15 +170,15 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
#endif
static struct irq_chip h720x_global_chip = {
.ack = mask_global_irq,
.mask = mask_global_irq,
.unmask = unmask_global_irq,
.irq_ack = mask_global_irq,
.irq_mask = mask_global_irq,
.irq_unmask = unmask_global_irq,
};
static struct irq_chip h720x_gpio_chip = {
.ack = ack_gpio_irq,
.mask = mask_gpio_irq,
.unmask = unmask_gpio_irq,
.irq_ack = ack_gpio_irq,
.irq_mask = mask_gpio_irq,
.irq_unmask = unmask_gpio_irq,
};
/*

14
arch/arm/mach-h720x/cpu-h7202.c
View File

@ -141,27 +141,27 @@ h7202_timer_interrupt(int irq, void *dev_id)
/*
* mask multiplexed timer IRQs
*/
static void inline mask_timerx_irq (u32 irq)
static void inline mask_timerx_irq(struct irq_data *d)
{
unsigned int bit;
bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
}
/*
* unmask multiplexed timer IRQs
*/
static void inline unmask_timerx_irq (u32 irq)
static void inline unmask_timerx_irq(struct irq_data *d)
{
unsigned int bit;
bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
}
static struct irq_chip h7202_timerx_chip = {
.ack = mask_timerx_irq,
.mask = mask_timerx_irq,
.unmask = unmask_timerx_irq,
.irq_ack = mask_timerx_irq,
.irq_mask = mask_timerx_irq,
.irq_unmask = unmask_timerx_irq,
};
static struct irqaction h7202_timer_irq = {

1
arch/arm/mach-imx/Kconfig
View File

@ -243,6 +243,7 @@ config MACH_MX27_3DS
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_DEBUG_BOARD
select MXC_ULPI if USB_ULPI
help
Include support for MX27PDK platform. This includes specific

10
arch/arm/mach-imx/mach-mx27_3ds.c
View File

@ -37,12 +37,15 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/ulpi.h>
#include <mach/irqs.h>
#include <mach/3ds_debugboard.h>
#include "devices-imx27.h"
#define SD1_EN_GPIO (GPIO_PORTB + 25)
#define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23)
#define SPI2_SS0 (GPIO_PORTD + 21)
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTC + 28)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
@ -215,10 +218,10 @@ static struct regulator_init_data vgen_init = {
static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
{
.id = MC13783_REGU_VMMC1,
.id = MC13783_REG_VMMC1,
.init_data = &vmmc1_init,
}, {
.id = MC13783_REGU_VGEN,
.id = MC13783_REG_VGEN,
.init_data = &vgen_init,
},
};
@ -276,6 +279,9 @@ static void __init mx27pdk_init(void)
imx27_add_spi_imx1(&spi2_pdata);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
}
static void __init mx27pdk_timer_init(void)

16
arch/arm/mach-integrator/integrator_ap.c
View File

@ -156,21 +156,21 @@ static void __init ap_map_io(void)
#define INTEGRATOR_SC_VALID_INT 0x003fffff
static void sc_mask_irq(unsigned int irq)
static void sc_mask_irq(struct irq_data *d)
{
writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
}
static void sc_unmask_irq(unsigned int irq)
static void sc_unmask_irq(struct irq_data *d)
{
writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_SET);
}
static struct irq_chip sc_chip = {
.name = "SC",
.ack = sc_mask_irq,
.mask = sc_mask_irq,
.unmask = sc_unmask_irq,
.name = "SC",
.irq_ack = sc_mask_irq,
.irq_mask = sc_mask_irq,
.irq_unmask = sc_unmask_irq,
};
static void __init ap_init_irq(void)

48
arch/arm/mach-integrator/integrator_cp.c
View File

@ -146,61 +146,61 @@ static void __init intcp_map_io(void)
#define sic_writel __raw_writel
#define sic_readl __raw_readl
static void cic_mask_irq(unsigned int irq)
static void cic_mask_irq(struct irq_data *d)
{
irq -= IRQ_CIC_START;
unsigned int irq = d->irq - IRQ_CIC_START;
cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
}
static void cic_unmask_irq(unsigned int irq)
static void cic_unmask_irq(struct irq_data *d)
{
irq -= IRQ_CIC_START;
unsigned int irq = d->irq - IRQ_CIC_START;
cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
}
static struct irq_chip cic_chip = {
.name = "CIC",
.ack = cic_mask_irq,
.mask = cic_mask_irq,
.unmask = cic_unmask_irq,
.name = "CIC",
.irq_ack = cic_mask_irq,
.irq_mask = cic_mask_irq,
.irq_unmask = cic_unmask_irq,
};
static void pic_mask_irq(unsigned int irq)
static void pic_mask_irq(struct irq_data *d)
{
irq -= IRQ_PIC_START;
unsigned int irq = d->irq - IRQ_PIC_START;
pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
}
static void pic_unmask_irq(unsigned int irq)
static void pic_unmask_irq(struct irq_data *d)
{
irq -= IRQ_PIC_START;
unsigned int irq = d->irq - IRQ_PIC_START;
pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
}
static struct irq_chip pic_chip = {
.name = "PIC",
.ack = pic_mask_irq,
.mask = pic_mask_irq,
.unmask = pic_unmask_irq,
.name = "PIC",
.irq_ack = pic_mask_irq,
.irq_mask = pic_mask_irq,
.irq_unmask = pic_unmask_irq,
};
static void sic_mask_irq(unsigned int irq)
static void sic_mask_irq(struct irq_data *d)
{
irq -= IRQ_SIC_START;
unsigned int irq = d->irq - IRQ_SIC_START;
sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
}
static void sic_unmask_irq(unsigned int irq)
static void sic_unmask_irq(struct irq_data *d)
{
irq -= IRQ_SIC_START;
unsigned int irq = d->irq - IRQ_SIC_START;
sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
}
static struct irq_chip sic_chip = {
.name = "SIC",
.ack = sic_mask_irq,
.mask = sic_mask_irq,
.unmask = sic_unmask_irq,
.name = "SIC",
.irq_ack = sic_mask_irq,
.irq_mask = sic_mask_irq,
.irq_unmask = sic_unmask_irq,
};
static void

64
arch/arm/mach-iop13xx/irq.c
View File

@ -123,79 +123,79 @@ static void write_intsize(u32 val)
/* 0 = Interrupt Masked and 1 = Interrupt not masked */
static void
iop13xx_irq_mask0 (unsigned int irq)
iop13xx_irq_mask0 (struct irq_data *d)
{
write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
write_intctl_0(read_intctl_0() & ~(1 << (d->irq - 0)));
}
static void
iop13xx_irq_mask1 (unsigned int irq)
iop13xx_irq_mask1 (struct irq_data *d)
{
write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
write_intctl_1(read_intctl_1() & ~(1 << (d->irq - 32)));
}
static void
iop13xx_irq_mask2 (unsigned int irq)
iop13xx_irq_mask2 (struct irq_data *d)
{
write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
write_intctl_2(read_intctl_2() & ~(1 << (d->irq - 64)));
}
static void
iop13xx_irq_mask3 (unsigned int irq)
iop13xx_irq_mask3 (struct irq_data *d)
{
write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
write_intctl_3(read_intctl_3() & ~(1 << (d->irq - 96)));
}
static void
iop13xx_irq_unmask0(unsigned int irq)
iop13xx_irq_unmask0(struct irq_data *d)
{
write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
write_intctl_0(read_intctl_0() | (1 << (d->irq - 0)));
}
static void
iop13xx_irq_unmask1(unsigned int irq)
iop13xx_irq_unmask1(struct irq_data *d)
{
write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
write_intctl_1(read_intctl_1() | (1 << (d->irq - 32)));
}
static void
iop13xx_irq_unmask2(unsigned int irq)
iop13xx_irq_unmask2(struct irq_data *d)
{
write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
write_intctl_2(read_intctl_2() | (1 << (d->irq - 64)));
}
static void
iop13xx_irq_unmask3(unsigned int irq)
iop13xx_irq_unmask3(struct irq_data *d)
{
write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
write_intctl_3(read_intctl_3() | (1 << (d->irq - 96)));
}
static struct irq_chip iop13xx_irqchip1 = {
.name = "IOP13xx-1",
.ack = iop13xx_irq_mask0,
.mask = iop13xx_irq_mask0,
.unmask = iop13xx_irq_unmask0,
.name = "IOP13xx-1",
.irq_ack = iop13xx_irq_mask0,
.irq_mask = iop13xx_irq_mask0,
.irq_unmask = iop13xx_irq_unmask0,
};
static struct irq_chip iop13xx_irqchip2 = {
.name = "IOP13xx-2",
.ack = iop13xx_irq_mask1,
.mask = iop13xx_irq_mask1,
.unmask = iop13xx_irq_unmask1,
.name = "IOP13xx-2",
.irq_ack = iop13xx_irq_mask1,
.irq_mask = iop13xx_irq_mask1,
.irq_unmask = iop13xx_irq_unmask1,
};
static struct irq_chip iop13xx_irqchip3 = {
.name = "IOP13xx-3",
.ack = iop13xx_irq_mask2,
.mask = iop13xx_irq_mask2,
.unmask = iop13xx_irq_unmask2,
.name = "IOP13xx-3",
.irq_ack = iop13xx_irq_mask2,
.irq_mask = iop13xx_irq_mask2,
.irq_unmask = iop13xx_irq_unmask2,
};
static struct irq_chip iop13xx_irqchip4 = {
.name = "IOP13xx-4",
.ack = iop13xx_irq_mask3,
.mask = iop13xx_irq_mask3,
.unmask = iop13xx_irq_unmask3,
.name = "IOP13xx-4",
.irq_ack = iop13xx_irq_mask3,
.irq_mask = iop13xx_irq_mask3,
.irq_unmask = iop13xx_irq_unmask3,
};
extern void iop_init_cp6_handler(void);

4
arch/arm/mach-iop13xx/msi.c
View File

@ -156,14 +156,14 @@ void arch_teardown_msi_irq(unsigned int irq)
destroy_irq(irq);
}
static void iop13xx_msi_nop(unsigned int irq)
static void iop13xx_msi_nop(struct irq_data *d)
{
return;
}
static struct irq_chip iop13xx_msi_chip = {
.name = "PCI-MSI",
.ack = iop13xx_msi_nop,
.irq_ack = iop13xx_msi_nop,
.irq_enable = unmask_msi_irq,
.irq_disable = mask_msi_irq,
.irq_mask = mask_msi_irq,

16
arch/arm/mach-iop32x/irq.c
View File

@ -32,24 +32,24 @@ static void intstr_write(u32 val)
}
static void
iop32x_irq_mask(unsigned int irq)
iop32x_irq_mask(struct irq_data *d)
{
iop32x_mask &= ~(1 << irq);
iop32x_mask &= ~(1 << d->irq);
intctl_write(iop32x_mask);
}
static void
iop32x_irq_unmask(unsigned int irq)
iop32x_irq_unmask(struct irq_data *d)
{
iop32x_mask |= 1 << irq;
iop32x_mask |= 1 << d->irq;
intctl_write(iop32x_mask);
}
struct irq_chip ext_chip = {
.name = "IOP32x",
.ack = iop32x_irq_mask,
.mask = iop32x_irq_mask,
.unmask = iop32x_irq_unmask,
.name = "IOP32x",
.irq_ack = iop32x_irq_mask,
.irq_mask = iop32x_irq_mask,
.irq_unmask = iop32x_irq_unmask,
};
void __init iop32x_init_irq(void)

32
arch/arm/mach-iop33x/irq.c
View File

@ -53,45 +53,45 @@ static void intsize_write(u32 val)
}
static void
iop33x_irq_mask1 (unsigned int irq)
iop33x_irq_mask1 (struct irq_data *d)
{
iop33x_mask0 &= ~(1 << irq);
iop33x_mask0 &= ~(1 << d->irq);
intctl0_write(iop33x_mask0);
}
static void
iop33x_irq_mask2 (unsigned int irq)
iop33x_irq_mask2 (struct irq_data *d)
{
iop33x_mask1 &= ~(1 << (irq - 32));
iop33x_mask1 &= ~(1 << (d->irq - 32));
intctl1_write(iop33x_mask1);
}
static void
iop33x_irq_unmask1(unsigned int irq)
iop33x_irq_unmask1(struct irq_data *d)
{
iop33x_mask0 |= 1 << irq;
iop33x_mask0 |= 1 << d->irq;
intctl0_write(iop33x_mask0);
}
static void
iop33x_irq_unmask2(unsigned int irq)
iop33x_irq_unmask2(struct irq_data *d)
{
iop33x_mask1 |= (1 << (irq - 32));
iop33x_mask1 |= (1 << (d->irq - 32));
intctl1_write(iop33x_mask1);
}
struct irq_chip iop33x_irqchip1 = {
.name = "IOP33x-1",
.ack = iop33x_irq_mask1,
.mask = iop33x_irq_mask1,
.unmask = iop33x_irq_unmask1,
.name = "IOP33x-1",
.irq_ack = iop33x_irq_mask1,
.irq_mask = iop33x_irq_mask1,
.irq_unmask = iop33x_irq_unmask1,
};
struct irq_chip iop33x_irqchip2 = {
.name = "IOP33x-2",
.ack = iop33x_irq_mask2,
.mask = iop33x_irq_mask2,
.unmask = iop33x_irq_unmask2,
.name = "IOP33x-2",
.irq_ack = iop33x_irq_mask2,
.irq_mask = iop33x_irq_mask2,
.irq_unmask = iop33x_irq_unmask2,
};
void __init iop33x_init_irq(void)

70
arch/arm/mach-ixp2000/core.c
View File

@ -309,9 +309,9 @@ static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
}
}
static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
{
int line = irq - IRQ_IXP2000_GPIO0;
int line = d->irq - IRQ_IXP2000_GPIO0;
/*
* First, configure this GPIO line as an input.
@ -342,8 +342,10 @@ static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
return 0;
}
static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
@ -351,38 +353,42 @@ static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
}
static void ixp2000_GPIO_irq_mask(unsigned int irq)
static void ixp2000_GPIO_irq_mask(struct irq_data *d)
{
unsigned int irq = d->irq;
ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}
static void ixp2000_GPIO_irq_unmask(unsigned int irq)
static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq;
ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}
static struct irq_chip ixp2000_GPIO_irq_chip = {
.ack = ixp2000_GPIO_irq_mask_ack,
.mask = ixp2000_GPIO_irq_mask,
.unmask = ixp2000_GPIO_irq_unmask,
.set_type = ixp2000_GPIO_irq_type,
.irq_ack = ixp2000_GPIO_irq_mask_ack,
.irq_mask = ixp2000_GPIO_irq_mask,
.irq_unmask = ixp2000_GPIO_irq_unmask,
.irq_set_type = ixp2000_GPIO_irq_type,
};
static void ixp2000_pci_irq_mask(unsigned int irq)
static void ixp2000_pci_irq_mask(struct irq_data *d)
{
unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
if (irq == IRQ_IXP2000_PCIA)
if (d->irq == IRQ_IXP2000_PCIA)
ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
else if (irq == IRQ_IXP2000_PCIB)
else if (d->irq == IRQ_IXP2000_PCIB)
ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
}
static void ixp2000_pci_irq_unmask(unsigned int irq)
static void ixp2000_pci_irq_unmask(struct irq_data *d)
{
unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
if (irq == IRQ_IXP2000_PCIA)
if (d->irq == IRQ_IXP2000_PCIA)
ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
else if (irq == IRQ_IXP2000_PCIB)
else if (d->irq == IRQ_IXP2000_PCIB)
ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
}
@ -401,44 +407,44 @@ static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
}
}
static void ixp2000_err_irq_mask(unsigned int irq)
static void ixp2000_err_irq_mask(struct irq_data *d)
{
ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}
static void ixp2000_err_irq_unmask(unsigned int irq)
static void ixp2000_err_irq_unmask(struct irq_data *d)
{
ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}
static struct irq_chip ixp2000_err_irq_chip = {
.ack = ixp2000_err_irq_mask,
.mask = ixp2000_err_irq_mask,
.unmask = ixp2000_err_irq_unmask
.irq_ack = ixp2000_err_irq_mask,
.irq_mask = ixp2000_err_irq_mask,
.irq_unmask = ixp2000_err_irq_unmask
};
static struct irq_chip ixp2000_pci_irq_chip = {
.ack = ixp2000_pci_irq_mask,
.mask = ixp2000_pci_irq_mask,
.unmask = ixp2000_pci_irq_unmask
.irq_ack = ixp2000_pci_irq_mask,
.irq_mask = ixp2000_pci_irq_mask,
.irq_unmask = ixp2000_pci_irq_unmask
};
static void ixp2000_irq_mask(unsigned int irq)
static void ixp2000_irq_mask(struct irq_data *d)
{
ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
}
static void ixp2000_irq_unmask(unsigned int irq)
static void ixp2000_irq_unmask(struct irq_data *d)
{
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
}
static struct irq_chip ixp2000_irq_chip = {
.ack = ixp2000_irq_mask,
.mask = ixp2000_irq_mask,
.unmask = ixp2000_irq_unmask
.irq_ack = ixp2000_irq_mask,
.irq_mask = ixp2000_irq_mask,
.irq_unmask = ixp2000_irq_unmask
};
void __init ixp2000_init_irq(void)

18
arch/arm/mach-ixp2000/ixdp2x00.c
View File

@ -63,7 +63,7 @@ static struct slowport_cfg slowport_cpld_cfg = {
};
#endif
static void ixdp2x00_irq_mask(unsigned int irq)
static void ixdp2x00_irq_mask(struct irq_data *d)
{
unsigned long dummy;
static struct slowport_cfg old_cfg;
@ -78,7 +78,7 @@ static void ixdp2x00_irq_mask(unsigned int irq)
#endif
dummy = *board_irq_mask;
dummy |= IXP2000_BOARD_IRQ_MASK(irq);
dummy |= IXP2000_BOARD_IRQ_MASK(d->irq);
ixp2000_reg_wrb(board_irq_mask, dummy);
#ifdef CONFIG_ARCH_IXDP2400
@ -87,7 +87,7 @@ static void ixdp2x00_irq_mask(unsigned int irq)
#endif
}
static void ixdp2x00_irq_unmask(unsigned int irq)
static void ixdp2x00_irq_unmask(struct irq_data *d)
{
unsigned long dummy;
static struct slowport_cfg old_cfg;
@ -98,7 +98,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
#endif
dummy = *board_irq_mask;
dummy &= ~IXP2000_BOARD_IRQ_MASK(irq);
dummy &= ~IXP2000_BOARD_IRQ_MASK(d->irq);
ixp2000_reg_wrb(board_irq_mask, dummy);
if (machine_is_ixdp2400())
@ -111,7 +111,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
static struct slowport_cfg old_cfg;
int i;
desc->chip->mask(irq);
desc->irq_data.chip->irq_mask(&desc->irq_data);
#ifdef CONFIG_ARCH_IXDP2400
if (machine_is_ixdp2400())
@ -133,13 +133,13 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
}
}
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
static struct irq_chip ixdp2x00_cpld_irq_chip = {
.ack = ixdp2x00_irq_mask,
.mask = ixdp2x00_irq_mask,
.unmask = ixdp2x00_irq_unmask
.irq_ack = ixdp2x00_irq_mask,
.irq_mask = ixdp2x00_irq_mask,
.irq_unmask = ixdp2x00_irq_unmask
};
void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs)

18
arch/arm/mach-ixp2000/ixdp2x01.c
View File

@ -48,16 +48,16 @@
/*************************************************************************
* IXDP2x01 IRQ Handling
*************************************************************************/
static void ixdp2x01_irq_mask(unsigned int irq)
static void ixdp2x01_irq_mask(struct irq_data *d)
{
ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
IXP2000_BOARD_IRQ_MASK(irq));
IXP2000_BOARD_IRQ_MASK(d->irq));
}
static void ixdp2x01_irq_unmask(unsigned int irq)
static void ixdp2x01_irq_unmask(struct irq_data *d)
{
ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
IXP2000_BOARD_IRQ_MASK(irq));
IXP2000_BOARD_IRQ_MASK(d->irq));
}
static u32 valid_irq_mask;
@ -67,7 +67,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
u32 ex_interrupt;
int i;
desc->chip->mask(irq);
desc->irq_data.chip->irq_mask(&desc->irq_data);
ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
@ -83,13 +83,13 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
}
}
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
static struct irq_chip ixdp2x01_irq_chip = {
.mask = ixdp2x01_irq_mask,
.ack = ixdp2x01_irq_mask,
.unmask = ixdp2x01_irq_unmask
.irq_mask = ixdp2x01_irq_mask,
.irq_ack = ixdp2x01_irq_mask,
.irq_unmask = ixdp2x01_irq_unmask
};
/*

55
arch/arm/mach-ixp23xx/core.c
View File

@ -111,9 +111,9 @@ enum ixp23xx_irq_type {
static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
static int ixp23xx_irq_set_type(struct irq_data *d, unsigned int type)
{
int line = irq - IRQ_IXP23XX_GPIO6 + 6;
int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
u32 int_style;
enum ixp23xx_irq_type irq_type;
volatile u32 *int_reg;
@ -149,7 +149,7 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
return -EINVAL;
}
ixp23xx_config_irq(irq, irq_type);
ixp23xx_config_irq(d->irq, irq_type);
if (line >= 8) { /* pins 8-15 */
line -= 8;
@ -173,9 +173,10 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
return 0;
}
static void ixp23xx_irq_mask(unsigned int irq)
static void ixp23xx_irq_mask(struct irq_data *d)
{
volatile unsigned long *intr_reg;
unsigned int irq = d->irq;
if (irq >= 56)
irq += 8;
@ -184,9 +185,9 @@ static void ixp23xx_irq_mask(unsigned int irq)
*intr_reg &= ~(1 << (irq % 32));
}
static void ixp23xx_irq_ack(unsigned int irq)
static void ixp23xx_irq_ack(struct irq_data *d)
{
int line = irq - IRQ_IXP23XX_GPIO6 + 6;
int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
if ((line < 6) || (line > 15))
return;
@ -198,11 +199,12 @@ static void ixp23xx_irq_ack(unsigned int irq)
* Level triggered interrupts on GPIO lines can only be cleared when the
* interrupt condition disappears.
*/
static void ixp23xx_irq_level_unmask(unsigned int irq)
static void ixp23xx_irq_level_unmask(struct irq_data *d)
{
volatile unsigned long *intr_reg;
unsigned int irq = d->irq;
ixp23xx_irq_ack(irq);
ixp23xx_irq_ack(d);
if (irq >= 56)
irq += 8;
@ -211,9 +213,10 @@ static void ixp23xx_irq_level_unmask(unsigned int irq)
*intr_reg |= (1 << (irq % 32));
}
static void ixp23xx_irq_edge_unmask(unsigned int irq)
static void ixp23xx_irq_edge_unmask(struct irq_data *d)
{
volatile unsigned long *intr_reg;
unsigned int irq = d->irq;
if (irq >= 56)
irq += 8;
@ -223,26 +226,30 @@ static void ixp23xx_irq_edge_unmask(unsigned int irq)
}
static struct irq_chip ixp23xx_irq_level_chip = {
.ack = ixp23xx_irq_mask,
.mask = ixp23xx_irq_mask,
.unmask = ixp23xx_irq_level_unmask,
.set_type = ixp23xx_irq_set_type
.irq_ack = ixp23xx_irq_mask,
.irq_mask = ixp23xx_irq_mask,
.irq_unmask = ixp23xx_irq_level_unmask,
.irq_set_type = ixp23xx_irq_set_type
};
static struct irq_chip ixp23xx_irq_edge_chip = {
.ack = ixp23xx_irq_ack,
.mask = ixp23xx_irq_mask,
.unmask = ixp23xx_irq_edge_unmask,
.set_type = ixp23xx_irq_set_type
.irq_ack = ixp23xx_irq_ack,
.irq_mask = ixp23xx_irq_mask,
.irq_unmask = ixp23xx_irq_edge_unmask,
.irq_set_type = ixp23xx_irq_set_type
};
static void ixp23xx_pci_irq_mask(unsigned int irq)
static void ixp23xx_pci_irq_mask(struct irq_data *d)
{
unsigned int irq = d->irq;
*IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
}
static void ixp23xx_pci_irq_unmask(unsigned int irq)
static void ixp23xx_pci_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq;
*IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
}
@ -256,7 +263,7 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc)
pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
/* See which PCI_INTA, or PCI_INTB interrupted */
if (pci_interrupt & (1 << 26)) {
@ -269,13 +276,13 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(irqno);
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
static struct irq_chip ixp23xx_pci_irq_chip = {
.ack = ixp23xx_pci_irq_mask,
.mask = ixp23xx_pci_irq_mask,
.unmask = ixp23xx_pci_irq_unmask
.irq_ack = ixp23xx_pci_irq_mask,
.irq_mask = ixp23xx_pci_irq_mask,
.irq_unmask = ixp23xx_pci_irq_unmask
};
static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)

36
arch/arm/mach-ixp23xx/ixdp2351.c
View File

@ -48,14 +48,14 @@
/*
* IXDP2351 Interrupt Handling
*/
static void ixdp2351_inta_mask(unsigned int irq)
static void ixdp2351_inta_mask(struct irq_data *d)
{
*IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
*IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
}
static void ixdp2351_inta_unmask(unsigned int irq)
static void ixdp2351_inta_unmask(struct irq_data *d)
{
*IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
*IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
}
static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
@ -64,7 +64,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
*IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
int i;
desc->chip->mask(irq);
desc->irq_data.chip->irq_mask(&desc->irq_data);
for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
if (ex_interrupt & (1 << i)) {
@ -74,23 +74,23 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
}
}
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
static struct irq_chip ixdp2351_inta_chip = {
.ack = ixdp2351_inta_mask,
.mask = ixdp2351_inta_mask,
.unmask = ixdp2351_inta_unmask
.irq_ack = ixdp2351_inta_mask,
.irq_mask = ixdp2351_inta_mask,
.irq_unmask = ixdp2351_inta_unmask
};
static void ixdp2351_intb_mask(unsigned int irq)
static void ixdp2351_intb_mask(struct irq_data *d)
{
*IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
*IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
}
static void ixdp2351_intb_unmask(unsigned int irq)
static void ixdp2351_intb_unmask(struct irq_data *d)
{
*IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
*IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
}
static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
@ -99,7 +99,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
*IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
int i;
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
if (ex_interrupt & (1 << i)) {
@ -109,13 +109,13 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
}
}
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
static struct irq_chip ixdp2351_intb_chip = {
.ack = ixdp2351_intb_mask,
.mask = ixdp2351_intb_mask,
.unmask = ixdp2351_intb_unmask
.irq_ack = ixdp2351_intb_mask,
.irq_mask = ixdp2351_intb_mask,
.irq_unmask = ixdp2351_intb_unmask
};
void __init ixdp2351_init_irq(void)

42
arch/arm/mach-ixp4xx/common.c
View File

@ -128,9 +128,9 @@ int irq_to_gpio(unsigned int irq)
}
EXPORT_SYMBOL(irq_to_gpio);
static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
{
int line = irq2gpio[irq];
int line = irq2gpio[d->irq];
u32 int_style;
enum ixp4xx_irq_type irq_type;
volatile u32 *int_reg;
@ -167,9 +167,9 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
}
if (irq_type == IXP4XX_IRQ_EDGE)
ixp4xx_irq_edge |= (1 << irq);
ixp4xx_irq_edge |= (1 << d->irq);
else
ixp4xx_irq_edge &= ~(1 << irq);
ixp4xx_irq_edge &= ~(1 << d->irq);
if (line >= 8) { /* pins 8-15 */
line -= 8;
@ -188,22 +188,22 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
/* Configure the line as an input */
gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN);
gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
return 0;
}
static void ixp4xx_irq_mask(unsigned int irq)
static void ixp4xx_irq_mask(struct irq_data *d)
{
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
*IXP4XX_ICMR2 &= ~(1 << (irq - 32));
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
*IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
else
*IXP4XX_ICMR &= ~(1 << irq);
*IXP4XX_ICMR &= ~(1 << d->irq);
}
static void ixp4xx_irq_ack(unsigned int irq)
static void ixp4xx_irq_ack(struct irq_data *d)
{
int line = (irq < 32) ? irq2gpio[irq] : -1;
int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
if (line >= 0)
*IXP4XX_GPIO_GPISR = (1 << line);
@ -213,23 +213,23 @@ static void ixp4xx_irq_ack(unsigned int irq)
* Level triggered interrupts on GPIO lines can only be cleared when the
* interrupt condition disappears.
*/
static void ixp4xx_irq_unmask(unsigned int irq)
static void ixp4xx_irq_unmask(struct irq_data *d)
{
if (!(ixp4xx_irq_edge & (1 << irq)))
ixp4xx_irq_ack(irq);
if (!(ixp4xx_irq_edge & (1 << d->irq)))
ixp4xx_irq_ack(d);
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
*IXP4XX_ICMR2 |= (1 << (irq - 32));
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
*IXP4XX_ICMR2 |= (1 << (d->irq - 32));
else
*IXP4XX_ICMR |= (1 << irq);
*IXP4XX_ICMR |= (1 << d->irq);
}
static struct irq_chip ixp4xx_irq_chip = {
.name = "IXP4xx",
.ack = ixp4xx_irq_ack,
.mask = ixp4xx_irq_mask,
.unmask = ixp4xx_irq_unmask,
.set_type = ixp4xx_set_irq_type,
.irq_ack = ixp4xx_irq_ack,
.irq_mask = ixp4xx_irq_mask,
.irq_unmask = ixp4xx_irq_unmask,
.irq_set_type = ixp4xx_set_irq_type,
};
void __init ixp4xx_init_irq(void)

43
arch/arm/mach-ks8695/irq.c
View File

@ -34,29 +34,29 @@
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
static void ks8695_irq_mask(unsigned int irqno)
static void ks8695_irq_mask(struct irq_data *d)
{
unsigned long inten;
inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
inten &= ~(1 << irqno);
inten &= ~(1 << d->irq);
__raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
}
static void ks8695_irq_unmask(unsigned int irqno)
static void ks8695_irq_unmask(struct irq_data *d)
{
unsigned long inten;
inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
inten |= (1 << irqno);
inten |= (1 << d->irq);
__raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
}
static void ks8695_irq_ack(unsigned int irqno)
static void ks8695_irq_ack(struct irq_data *d)
{
__raw_writel((1 << irqno), KS8695_IRQ_VA + KS8695_INTST);
__raw_writel((1 << d->irq), KS8695_IRQ_VA + KS8695_INTST);
}
@ -64,7 +64,7 @@ static struct irq_chip ks8695_irq_level_chip;
static struct irq_chip ks8695_irq_edge_chip;
static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned long ctrl, mode;
unsigned short level_triggered = 0;
@ -93,7 +93,7 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
return -EINVAL;
}
switch (irqno) {
switch (d->irq) {
case KS8695_IRQ_EXTERN0:
ctrl &= ~IOPC_IOEINT0TM;
ctrl |= IOPC_IOEINT0_MODE(mode);
@ -115,12 +115,12 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
}
if (level_triggered) {
set_irq_chip(irqno, &ks8695_irq_level_chip);
set_irq_handler(irqno, handle_level_irq);
set_irq_chip(d->irq, &ks8695_irq_level_chip);
set_irq_handler(d->irq, handle_level_irq);
}
else {
set_irq_chip(irqno, &ks8695_irq_edge_chip);
set_irq_handler(irqno, handle_edge_irq);
set_irq_chip(d->irq, &ks8695_irq_edge_chip);
set_irq_handler(d->irq, handle_edge_irq);
}
__raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
@ -128,17 +128,17 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
}
static struct irq_chip ks8695_irq_level_chip = {
.ack = ks8695_irq_mask,
.mask = ks8695_irq_mask,
.unmask = ks8695_irq_unmask,
.set_type = ks8695_irq_set_type,
.irq_ack = ks8695_irq_mask,
.irq_mask = ks8695_irq_mask,
.irq_unmask = ks8695_irq_unmask,
.irq_set_type = ks8695_irq_set_type,
};
static struct irq_chip ks8695_irq_edge_chip = {
.ack = ks8695_irq_ack,
.mask = ks8695_irq_mask,
.unmask = ks8695_irq_unmask,
.set_type = ks8695_irq_set_type,
.irq_ack = ks8695_irq_ack,
.irq_mask = ks8695_irq_mask,
.irq_unmask = ks8695_irq_unmask,
.irq_set_type = ks8695_irq_set_type,
};
void __init ks8695_init_irq(void)
@ -164,7 +164,8 @@ void __init ks8695_init_irq(void)
/* Edge-triggered interrupts */
default:
ks8695_irq_ack(irq); /* clear pending bit */
/* clear pending bit */
ks8695_irq_ack(irq_get_irq_data(irq));
set_irq_chip(irq, &ks8695_irq_edge_chip);
set_irq_handler(irq, handle_edge_irq);
}

20
arch/arm/mach-lh7a40x/arch-kev7a400.c
View File

@ -46,28 +46,28 @@ void __init kev7a400_map_io(void)
static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */
static void kev7a400_ack_cpld_irq (u32 irq)
static void kev7a400_ack_cpld_irq(struct irq_data *d)
{
CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD);
CPLD_CL_INT = 1 << (d->irq - IRQ_KEV7A400_CPLD);
}
static void kev7a400_mask_cpld_irq (u32 irq)
static void kev7a400_mask_cpld_irq(struct irq_data *d)
{
CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD));
CPLD_IRQ_mask &= ~(1 << (d->irq - IRQ_KEV7A400_CPLD));
CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
}
static void kev7a400_unmask_cpld_irq (u32 irq)
static void kev7a400_unmask_cpld_irq(struct irq_data *d)
{
CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD);
CPLD_IRQ_mask |= 1 << (d->irq - IRQ_KEV7A400_CPLD);
CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
}
static struct irq_chip kev7a400_cpld_chip = {
.name = "CPLD",
.ack = kev7a400_ack_cpld_irq,
.mask = kev7a400_mask_cpld_irq,
.unmask = kev7a400_unmask_cpld_irq,
.name = "CPLD",
.irq_ack = kev7a400_ack_cpld_irq,
.irq_mask = kev7a400_mask_cpld_irq,
.irq_unmask = kev7a400_unmask_cpld_irq,
};

25
arch/arm/mach-lh7a40x/arch-lpd7a40x.c
View File

@ -159,7 +159,7 @@ static void __init lpd7a40x_init (void)
#endif
}
static void lh7a40x_ack_cpld_irq (u32 irq)
static void lh7a40x_ack_cpld_irq(struct irq_data *d)
{
/* CPLD doesn't have ack capability, but some devices may */
@ -167,14 +167,14 @@ static void lh7a40x_ack_cpld_irq (u32 irq)
/* The touch control *must* mask the interrupt because the
* interrupt bit is read by the driver to determine if the pen
* is still down. */
if (irq == IRQ_TOUCH)
if (d->irq == IRQ_TOUCH)
CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
#endif
}
static void lh7a40x_mask_cpld_irq (u32 irq)
static void lh7a40x_mask_cpld_irq(struct irq_data *d)
{
switch (irq) {
switch (d->irq) {
case IRQ_LPD7A40X_ETH_INT:
CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET;
break;
@ -186,9 +186,9 @@ static void lh7a40x_mask_cpld_irq (u32 irq)
}
}
static void lh7a40x_unmask_cpld_irq (u32 irq)
static void lh7a40x_unmask_cpld_irq(struct irq_data *d)
{
switch (irq) {
switch (d->irq) {
case IRQ_LPD7A40X_ETH_INT:
CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
break;
@ -201,17 +201,17 @@ static void lh7a40x_unmask_cpld_irq (u32 irq)
}
static struct irq_chip lpd7a40x_cpld_chip = {
.name = "CPLD",
.ack = lh7a40x_ack_cpld_irq,
.mask = lh7a40x_mask_cpld_irq,
.unmask = lh7a40x_unmask_cpld_irq,
.name = "CPLD",
.irq_ack = lh7a40x_ack_cpld_irq,
.irq_mask = lh7a40x_mask_cpld_irq,
.irq_unmask = lh7a40x_unmask_cpld_irq,
};
static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
{
unsigned int mask = CPLD_INTERRUPTS;
desc->chip->ack (irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
if ((mask & (1<<0)) == 0) /* WLAN */
generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
@ -221,7 +221,8 @@ static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
generic_handle_irq(IRQ_TOUCH);
#endif
desc->chip->unmask (irq); /* Level-triggered need this */
/* Level-triggered need this */
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}

30
arch/arm/mach-lh7a40x/irq-lh7a400.c
View File

@ -21,34 +21,34 @@
/* CPU IRQ handling */
static void lh7a400_mask_irq (u32 irq)
static void lh7a400_mask_irq(struct irq_data *d)
{
INTC_INTENC = (1 << irq);
INTC_INTENC = (1 << d->irq);
}
static void lh7a400_unmask_irq (u32 irq)
static void lh7a400_unmask_irq(struct irq_data *d)
{
INTC_INTENS = (1 << irq);
INTC_INTENS = (1 << d->irq);
}
static void lh7a400_ack_gpio_irq (u32 irq)
static void lh7a400_ack_gpio_irq(struct irq_data *d)
{
GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
INTC_INTENC = (1 << irq);
GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
INTC_INTENC = (1 << d->irq);
}
static struct irq_chip lh7a400_internal_chip = {
.name = "MPU",
.ack = lh7a400_mask_irq, /* Level triggering -> mask is ack */
.mask = lh7a400_mask_irq,
.unmask = lh7a400_unmask_irq,
.name = "MPU",
.irq_ack = lh7a400_mask_irq, /* Level triggering -> mask is ack */
.irq_mask = lh7a400_mask_irq,
.irq_unmask = lh7a400_unmask_irq,
};
static struct irq_chip lh7a400_gpio_chip = {
.name = "GPIO",
.ack = lh7a400_ack_gpio_irq,
.mask = lh7a400_mask_irq,
.unmask = lh7a400_unmask_irq,
.name = "GPIO",
.irq_ack = lh7a400_ack_gpio_irq,
.irq_mask = lh7a400_mask_irq,
.irq_unmask = lh7a400_unmask_irq,
};

60
arch/arm/mach-lh7a40x/irq-lh7a404.c
View File

@ -43,64 +43,64 @@ static unsigned char irq_pri_vic2[] = {
/* CPU IRQ handling */
static void lh7a404_vic1_mask_irq (u32 irq)
static void lh7a404_vic1_mask_irq(struct irq_data *d)
{
VIC1_INTENCLR = (1 << irq);
VIC1_INTENCLR = (1 << d->irq);
}
static void lh7a404_vic1_unmask_irq (u32 irq)
static void lh7a404_vic1_unmask_irq(struct irq_data *d)
{
VIC1_INTEN = (1 << irq);
VIC1_INTEN = (1 << d->irq);
}
static void lh7a404_vic2_mask_irq (u32 irq)
static void lh7a404_vic2_mask_irq(struct irq_data *d)
{
VIC2_INTENCLR = (1 << (irq - 32));
VIC2_INTENCLR = (1 << (d->irq - 32));
}
static void lh7a404_vic2_unmask_irq (u32 irq)
static void lh7a404_vic2_unmask_irq(struct irq_data *d)
{
VIC2_INTEN = (1 << (irq - 32));
VIC2_INTEN = (1 << (d->irq - 32));
}
static void lh7a404_vic1_ack_gpio_irq (u32 irq)
static void lh7a404_vic1_ack_gpio_irq(struct irq_data *d)
{
GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
VIC1_INTENCLR = (1 << irq);
GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
VIC1_INTENCLR = (1 << d->irq);
}
static void lh7a404_vic2_ack_gpio_irq (u32 irq)
static void lh7a404_vic2_ack_gpio_irq(struct irq_data *d)
{
GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
VIC2_INTENCLR = (1 << irq);
GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
VIC2_INTENCLR = (1 << d->irq);
}
static struct irq_chip lh7a404_vic1_chip = {
.name = "VIC1",
.ack = lh7a404_vic1_mask_irq, /* Because level-triggered */
.mask = lh7a404_vic1_mask_irq,
.unmask = lh7a404_vic1_unmask_irq,
.name = "VIC1",
.irq_ack = lh7a404_vic1_mask_irq, /* Because level-triggered */
.irq_mask = lh7a404_vic1_mask_irq,
.irq_unmask = lh7a404_vic1_unmask_irq,
};
static struct irq_chip lh7a404_vic2_chip = {
.name = "VIC2",
.ack = lh7a404_vic2_mask_irq, /* Because level-triggered */
.mask = lh7a404_vic2_mask_irq,
.unmask = lh7a404_vic2_unmask_irq,
.name = "VIC2",
.irq_ack = lh7a404_vic2_mask_irq, /* Because level-triggered */
.irq_mask = lh7a404_vic2_mask_irq,
.irq_unmask = lh7a404_vic2_unmask_irq,
};
static struct irq_chip lh7a404_gpio_vic1_chip = {
.name = "GPIO-VIC1",
.ack = lh7a404_vic1_ack_gpio_irq,
.mask = lh7a404_vic1_mask_irq,
.unmask = lh7a404_vic1_unmask_irq,
.name = "GPIO-VIC1",
.irq_ack = lh7a404_vic1_ack_gpio_irq,
.irq_mask = lh7a404_vic1_mask_irq,
.irq_unmask = lh7a404_vic1_unmask_irq,
};
static struct irq_chip lh7a404_gpio_vic2_chip = {
.name = "GPIO-VIC2",
.ack = lh7a404_vic2_ack_gpio_irq,
.mask = lh7a404_vic2_mask_irq,
.unmask = lh7a404_vic2_unmask_irq,
.name = "GPIO-VIC2",
.irq_ack = lh7a404_vic2_ack_gpio_irq,
.irq_mask = lh7a404_vic2_mask_irq,
.irq_unmask = lh7a404_vic2_unmask_irq,
};
/* IRQ initialization */

22
arch/arm/mach-lh7a40x/irq-lpd7a40x.c
View File

@ -20,14 +20,14 @@
#include "common.h"
static void lh7a40x_ack_cpld_irq (u32 irq)
static void lh7a40x_ack_cpld_irq(struct irq_data *d)
{
/* CPLD doesn't have ack capability */
}
static void lh7a40x_mask_cpld_irq (u32 irq)
static void lh7a40x_mask_cpld_irq(struct irq_data *d)
{
switch (irq) {
switch (d->irq) {
case IRQ_LPD7A40X_ETH_INT:
CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4;
break;
@ -37,9 +37,9 @@ static void lh7a40x_mask_cpld_irq (u32 irq)
}
}
static void lh7a40x_unmask_cpld_irq (u32 irq)
static void lh7a40x_unmask_cpld_irq(struct irq_data *d)
{
switch (irq) {
switch (d->irq) {
case IRQ_LPD7A40X_ETH_INT:
CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4;
break;
@ -50,17 +50,17 @@ static void lh7a40x_unmask_cpld_irq (u32 irq)
}
static struct irq_chip lh7a40x_cpld_chip = {
.name = "CPLD",
.ack = lh7a40x_ack_cpld_irq,
.mask = lh7a40x_mask_cpld_irq,
.unmask = lh7a40x_unmask_cpld_irq,
.name = "CPLD",
.irq_ack = lh7a40x_ack_cpld_irq,
.irq_mask = lh7a40x_mask_cpld_irq,
.irq_unmask = lh7a40x_unmask_cpld_irq,
};
static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
{
unsigned int mask = CPLD_INTERRUPTS;
desc->chip->ack (irq);
desc->irq_data.chip->ack (irq);
if ((mask & 0x1) == 0) /* WLAN */
generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
@ -68,7 +68,7 @@ static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
if ((mask & 0x2) == 0) /* Touch */
generic_handle_irq(IRQ_LPD7A400_TS);
desc->chip->unmask (irq); /* Level-triggered need this */
desc->irq_data.chip->unmask (irq); /* Level-triggered need this */
}

56
arch/arm/mach-lpc32xx/irq.c
View File

@ -191,38 +191,38 @@ static void get_controller(unsigned int irq, unsigned int *base,
}
}
static void lpc32xx_mask_irq(unsigned int irq)
static void lpc32xx_mask_irq(struct irq_data *d)
{
unsigned int reg, ctrl, mask;
get_controller(irq, &ctrl, &mask);
get_controller(d->irq, &ctrl, &mask);
reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
__raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
}
static void lpc32xx_unmask_irq(unsigned int irq)
static void lpc32xx_unmask_irq(struct irq_data *d)
{
unsigned int reg, ctrl, mask;
get_controller(irq, &ctrl, &mask);
get_controller(d->irq, &ctrl, &mask);
reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
__raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
}
static void lpc32xx_ack_irq(unsigned int irq)
static void lpc32xx_ack_irq(struct irq_data *d)
{
unsigned int ctrl, mask;
get_controller(irq, &ctrl, &mask);
get_controller(d->irq, &ctrl, &mask);
__raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
/* Also need to clear pending wake event */
if (lpc32xx_events[irq].mask != 0)
__raw_writel(lpc32xx_events[irq].mask,
lpc32xx_events[irq].event_group->rawstat_reg);
if (lpc32xx_events[d->irq].mask != 0)
__raw_writel(lpc32xx_events[d->irq].mask,
lpc32xx_events[d->irq].event_group->rawstat_reg);
}
static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
@ -261,27 +261,27 @@ static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
}
}
static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
{
switch (type) {
case IRQ_TYPE_EDGE_RISING:
/* Rising edge sensitive */
__lpc32xx_set_irq_type(irq, 1, 1);
__lpc32xx_set_irq_type(d->irq, 1, 1);
break;
case IRQ_TYPE_EDGE_FALLING:
/* Falling edge sensitive */
__lpc32xx_set_irq_type(irq, 0, 1);
__lpc32xx_set_irq_type(d->irq, 0, 1);
break;
case IRQ_TYPE_LEVEL_LOW:
/* Low level sensitive */
__lpc32xx_set_irq_type(irq, 0, 0);
__lpc32xx_set_irq_type(d->irq, 0, 0);
break;
case IRQ_TYPE_LEVEL_HIGH:
/* High level sensitive */
__lpc32xx_set_irq_type(irq, 1, 0);
__lpc32xx_set_irq_type(d->irq, 1, 0);
break;
/* Other modes are not supported */
@ -290,33 +290,33 @@ static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
}
/* Ok to use the level handler for all types */
set_irq_handler(irq, handle_level_irq);
set_irq_handler(d->irq, handle_level_irq);
return 0;
}
static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
{
unsigned long eventreg;
if (lpc32xx_events[irqno].mask != 0) {
eventreg = __raw_readl(lpc32xx_events[irqno].
if (lpc32xx_events[d->irq].mask != 0) {
eventreg = __raw_readl(lpc32xx_events[d->irq].
event_group->enab_reg);
if (state)
eventreg |= lpc32xx_events[irqno].mask;
eventreg |= lpc32xx_events[d->irq].mask;
else
eventreg &= ~lpc32xx_events[irqno].mask;
eventreg &= ~lpc32xx_events[d->irq].mask;
__raw_writel(eventreg,
lpc32xx_events[irqno].event_group->enab_reg);
lpc32xx_events[d->irq].event_group->enab_reg);
return 0;
}
/* Clear event */
__raw_writel(lpc32xx_events[irqno].mask,
lpc32xx_events[irqno].event_group->rawstat_reg);
__raw_writel(lpc32xx_events[d->irq].mask,
lpc32xx_events[d->irq].event_group->rawstat_reg);
return -ENODEV;
}
@ -336,11 +336,11 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr,
}
static struct irq_chip lpc32xx_irq_chip = {
.ack = lpc32xx_ack_irq,
.mask = lpc32xx_mask_irq,
.unmask = lpc32xx_unmask_irq,
.set_type = lpc32xx_set_irq_type,
.set_wake = lpc32xx_irq_wake
.irq_ack = lpc32xx_ack_irq,
.irq_mask = lpc32xx_mask_irq,
.irq_unmask = lpc32xx_unmask_irq,
.irq_set_type = lpc32xx_set_irq_type,
.irq_set_wake = lpc32xx_irq_wake
};
static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)

2
arch/arm/mach-mmp/include/mach/mfp-mmp2.h
View File

@ -6,7 +6,7 @@
#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
#define MFP_DRIVE_SLOW (0x2 << 13)
#define MFP_DRIVE_MEDIUM (0x4 << 13)
#define MFP_DRIVE_FAST (0x8 << 13)
#define MFP_DRIVE_FAST (0x6 << 13)
/* GPIO */
#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)

2
arch/arm/mach-mmp/include/mach/mfp-pxa910.h
View File

@ -6,7 +6,7 @@
#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
#define MFP_DRIVE_SLOW (0x2 << 13)
#define MFP_DRIVE_MEDIUM (0x4 << 13)
#define MFP_DRIVE_FAST (0x8 << 13)
#define MFP_DRIVE_FAST (0x6 << 13)
/* UART2 */
#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6)

46
arch/arm/mach-mmp/irq-mmp2.c
View File

@ -20,48 +20,48 @@
#include "common.h"
static void icu_mask_irq(unsigned int irq)
static void icu_mask_irq(struct irq_data *d)
{
uint32_t r = __raw_readl(ICU_INT_CONF(irq));
uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
r &= ~ICU_INT_ROUTE_PJ4_IRQ;
__raw_writel(r, ICU_INT_CONF(irq));
__raw_writel(r, ICU_INT_CONF(d->irq));
}
static void icu_unmask_irq(unsigned int irq)
static void icu_unmask_irq(struct irq_data *d)
{
uint32_t r = __raw_readl(ICU_INT_CONF(irq));
uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
r |= ICU_INT_ROUTE_PJ4_IRQ;
__raw_writel(r, ICU_INT_CONF(irq));
__raw_writel(r, ICU_INT_CONF(d->irq));
}
static struct irq_chip icu_irq_chip = {
.name = "icu_irq",
.mask = icu_mask_irq,
.mask_ack = icu_mask_irq,
.unmask = icu_unmask_irq,
.irq_mask = icu_mask_irq,
.irq_mask_ack = icu_mask_irq,
.irq_unmask = icu_unmask_irq,
};
static void pmic_irq_ack(unsigned int irq)
static void pmic_irq_ack(struct irq_data *d)
{
if (irq == IRQ_MMP2_PMIC)
if (d->irq == IRQ_MMP2_PMIC)
mmp2_clear_pmic_int();
}
#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
static void _name_##_mask_irq(unsigned int irq) \
static void _name_##_mask_irq(struct irq_data *d) \
{ \
uint32_t r; \
r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \
r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \
__raw_writel(r, prefix##_MASK); \
}
#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
static void _name_##_unmask_irq(unsigned int irq) \
static void _name_##_unmask_irq(struct irq_data *d) \
{ \
uint32_t r; \
r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \
r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \
__raw_writel(r, prefix##_MASK); \
}
@ -88,8 +88,8 @@ SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
static struct irq_chip _name_##_irq_chip = { \
.name = #_name_, \
.mask = _name_##_mask_irq, \
.unmask = _name_##_unmask_irq, \
.irq_mask = _name_##_mask_irq, \
.irq_unmask = _name_##_unmask_irq, \
}
SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
@ -103,10 +103,12 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
int irq;
for (irq = start; num > 0; irq++, num--) {
struct irq_data *d = irq_get_irq_data(irq);
/* mask and clear the IRQ */
chip->mask(irq);
if (chip->ack)
chip->ack(irq);
chip->irq_mask(d);
if (chip->irq_ack)
chip->irq_ack(d);
set_irq_chip(irq, chip);
set_irq_flags(irq, IRQF_VALID);
@ -119,7 +121,7 @@ void __init mmp2_init_icu(void)
int irq;
for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
icu_mask_irq(irq);
icu_mask_irq(irq_get_irq_data(irq));
set_irq_chip(irq, &icu_irq_chip);
set_irq_flags(irq, IRQF_VALID);
@ -139,7 +141,7 @@ void __init mmp2_init_icu(void)
/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
* to be written to clear the interrupt
*/
pmic_irq_chip.ack = pmic_irq_ack;
pmic_irq_chip.irq_ack = pmic_irq_ack;
init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);

18
arch/arm/mach-mmp/irq-pxa168.c
View File

@ -25,21 +25,21 @@
#define PRIORITY_DEFAULT 0x1
#define PRIORITY_NONE 0x0 /* means IRQ disabled */
static void icu_mask_irq(unsigned int irq)
static void icu_mask_irq(struct irq_data *d)
{
__raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq));
__raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
}
static void icu_unmask_irq(unsigned int irq)
static void icu_unmask_irq(struct irq_data *d)
{
__raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq));
__raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
}
static struct irq_chip icu_irq_chip = {
.name = "icu_irq",
.ack = icu_mask_irq,
.mask = icu_mask_irq,
.unmask = icu_unmask_irq,
.name = "icu_irq",
.irq_ack = icu_mask_irq,
.irq_mask = icu_mask_irq,
.irq_unmask = icu_unmask_irq,
};
void __init icu_init_irq(void)
@ -47,7 +47,7 @@ void __init icu_init_irq(void)
int irq;
for (irq = 0; irq < 64; irq++) {
icu_mask_irq(irq);
icu_mask_irq(irq_get_irq_data(irq));
set_irq_chip(irq, &icu_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);

42
arch/arm/mach-msm/board-trout-gpio.c
View File

@ -113,52 +113,52 @@ static struct msm_gpio_chip msm_gpio_banks[] = {
TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
};
static void trout_gpio_irq_ack(unsigned int irq)
static void trout_gpio_irq_ack(struct irq_data *d)
{
int bank = TROUT_INT_TO_BANK(irq);
uint8_t mask = TROUT_INT_TO_MASK(irq);
int bank = TROUT_INT_TO_BANK(d->irq);
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
int reg = TROUT_BANK_TO_STAT_REG(bank);
/*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", irq);*/
/*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", d->irq);*/
writeb(mask, TROUT_CPLD_BASE + reg);
}
static void trout_gpio_irq_mask(unsigned int irq)
static void trout_gpio_irq_mask(struct irq_data *d)
{
unsigned long flags;
uint8_t reg_val;
int bank = TROUT_INT_TO_BANK(irq);
uint8_t mask = TROUT_INT_TO_MASK(irq);
int bank = TROUT_INT_TO_BANK(d->irq);
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
int reg = TROUT_BANK_TO_MASK_REG(bank);
local_irq_save(flags);
reg_val = trout_int_mask[bank] |= mask;
/*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n",
irq, bank, reg_val);*/
d->irq, bank, reg_val);*/
writeb(reg_val, TROUT_CPLD_BASE + reg);
local_irq_restore(flags);
}
static void trout_gpio_irq_unmask(unsigned int irq)
static void trout_gpio_irq_unmask(struct irq_data *d)
{
unsigned long flags;
uint8_t reg_val;
int bank = TROUT_INT_TO_BANK(irq);
uint8_t mask = TROUT_INT_TO_MASK(irq);
int bank = TROUT_INT_TO_BANK(d->irq);
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
int reg = TROUT_BANK_TO_MASK_REG(bank);
local_irq_save(flags);
reg_val = trout_int_mask[bank] &= ~mask;
/*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n",
irq, bank, reg_val);*/
d->irq, bank, reg_val);*/
writeb(reg_val, TROUT_CPLD_BASE + reg);
local_irq_restore(flags);
}
int trout_gpio_irq_set_wake(unsigned int irq, unsigned int on)
int trout_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned long flags;
int bank = TROUT_INT_TO_BANK(irq);
uint8_t mask = TROUT_INT_TO_MASK(irq);
int bank = TROUT_INT_TO_BANK(d->irq);
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
local_irq_save(flags);
if(on)
@ -198,15 +198,15 @@ static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
}
int_base += TROUT_INT_BANK0_COUNT;
}
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
}
static struct irq_chip trout_gpio_irq_chip = {
.name = "troutgpio",
.ack = trout_gpio_irq_ack,
.mask = trout_gpio_irq_mask,
.unmask = trout_gpio_irq_unmask,
.set_wake = trout_gpio_irq_set_wake,
.name = "troutgpio",
.irq_ack = trout_gpio_irq_ack,
.irq_mask = trout_gpio_irq_mask,
.irq_unmask = trout_gpio_irq_unmask,
.irq_set_wake = trout_gpio_irq_set_wake,
};
/*

48
arch/arm/mach-msm/gpio.c
View File

@ -225,21 +225,21 @@ struct msm_gpio_chip msm_gpio_chips[] = {
#endif
};
static void msm_gpio_irq_ack(unsigned int irq)
static void msm_gpio_irq_ack(struct irq_data *d)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
msm_gpio_clear_detect_status(msm_chip,
irq - gpio_to_irq(msm_chip->chip.base));
d->irq - gpio_to_irq(msm_chip->chip.base));
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
}
static void msm_gpio_irq_mask(unsigned int irq)
static void msm_gpio_irq_mask(struct irq_data *d)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
/* level triggered interrupts are also latched */
@ -250,11 +250,11 @@ static void msm_gpio_irq_mask(unsigned int irq)
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
}
static void msm_gpio_irq_unmask(unsigned int irq)
static void msm_gpio_irq_unmask(struct irq_data *d)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
/* level triggered interrupts are also latched */
@ -265,11 +265,11 @@ static void msm_gpio_irq_unmask(unsigned int irq)
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
}
static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
@ -282,21 +282,21 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
return 0;
}
static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
unsigned val, mask = BIT(offset);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
val = readl(msm_chip->regs.int_edge);
if (flow_type & IRQ_TYPE_EDGE_BOTH) {
writel(val | mask, msm_chip->regs.int_edge);
irq_desc[irq].handle_irq = handle_edge_irq;
irq_desc[d->irq].handle_irq = handle_edge_irq;
} else {
writel(val & ~mask, msm_chip->regs.int_edge);
irq_desc[irq].handle_irq = handle_level_irq;
irq_desc[d->irq].handle_irq = handle_level_irq;
}
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
msm_chip->both_edge_detect |= mask;
@ -333,16 +333,16 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
msm_chip->chip.base + j);
}
}
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
}
static struct irq_chip msm_gpio_irq_chip = {
.name = "msmgpio",
.ack = msm_gpio_irq_ack,
.mask = msm_gpio_irq_mask,
.unmask = msm_gpio_irq_unmask,
.set_wake = msm_gpio_irq_set_wake,
.set_type = msm_gpio_irq_set_type,
.name = "msmgpio",
.irq_ack = msm_gpio_irq_ack,
.irq_mask = msm_gpio_irq_mask,
.irq_unmask = msm_gpio_irq_unmask,
.irq_set_wake = msm_gpio_irq_set_wake,
.irq_set_type = msm_gpio_irq_set_type,
};
static int __init msm_init_gpio(void)

65
arch/arm/mach-msm/irq-vic.c
View File

@ -226,19 +226,18 @@ static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
writel(val, base + (i * 4));
}
static void msm_irq_ack(unsigned int irq)
static void msm_irq_ack(struct irq_data *d)
{
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq);
irq = 1 << (irq & 31);
writel(irq, reg);
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, d->irq);
writel(1 << (d->irq & 31), reg);
}
static void msm_irq_mask(unsigned int irq)
static void msm_irq_mask(struct irq_data *d)
{
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq);
unsigned index = VIC_INT_TO_REG_INDEX(irq);
uint32_t mask = 1UL << (irq & 31);
int smsm_irq = msm_irq_to_smsm[irq];
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, d->irq);
unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
uint32_t mask = 1UL << (d->irq & 31);
int smsm_irq = msm_irq_to_smsm[d->irq];
msm_irq_shadow_reg[index].int_en[0] &= ~mask;
writel(mask, reg);
@ -250,12 +249,12 @@ static void msm_irq_mask(unsigned int irq)
}
}
static void msm_irq_unmask(unsigned int irq)
static void msm_irq_unmask(struct irq_data *d)
{
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq);
unsigned index = VIC_INT_TO_REG_INDEX(irq);
uint32_t mask = 1UL << (irq & 31);
int smsm_irq = msm_irq_to_smsm[irq];
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, d->irq);
unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
uint32_t mask = 1UL << (d->irq & 31);
int smsm_irq = msm_irq_to_smsm[d->irq];
msm_irq_shadow_reg[index].int_en[0] |= mask;
writel(mask, reg);
@ -268,14 +267,14 @@ static void msm_irq_unmask(unsigned int irq)
}
}
static int msm_irq_set_wake(unsigned int irq, unsigned int on)
static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned index = VIC_INT_TO_REG_INDEX(irq);
uint32_t mask = 1UL << (irq & 31);
int smsm_irq = msm_irq_to_smsm[irq];
unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
uint32_t mask = 1UL << (d->irq & 31);
int smsm_irq = msm_irq_to_smsm[d->irq];
if (smsm_irq == 0) {
printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq);
printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", d->irq);
return -EINVAL;
}
if (on)
@ -294,12 +293,12 @@ static int msm_irq_set_wake(unsigned int irq, unsigned int on)
return 0;
}
static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq);
void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq);
unsigned index = VIC_INT_TO_REG_INDEX(irq);
int b = 1 << (irq & 31);
void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, d->irq);
void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, d->irq);
unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
int b = 1 << (d->irq & 31);
uint32_t polarity;
uint32_t type;
@ -314,11 +313,11 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
type = msm_irq_shadow_reg[index].int_type;
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
type |= b;
irq_desc[irq].handle_irq = handle_edge_irq;
irq_desc[d->irq].handle_irq = handle_edge_irq;
}
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
type &= ~b;
irq_desc[irq].handle_irq = handle_level_irq;
irq_desc[d->irq].handle_irq = handle_level_irq;
}
writel(type, treg);
msm_irq_shadow_reg[index].int_type = type;
@ -326,13 +325,13 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
}
static struct irq_chip msm_irq_chip = {
.name = "msm",
.disable = msm_irq_mask,
.ack = msm_irq_ack,
.mask = msm_irq_mask,
.unmask = msm_irq_unmask,
.set_wake = msm_irq_set_wake,
.set_type = msm_irq_set_type,
.name = "msm",
.irq_disable = msm_irq_mask,
.irq_ack = msm_irq_ack,
.irq_mask = msm_irq_mask,
.irq_unmask = msm_irq_unmask,
.irq_set_wake = msm_irq_set_wake,
.irq_set_type = msm_irq_set_type,
};
void __init msm_init_irq(void)

45
arch/arm/mach-msm/irq.c
View File

@ -64,35 +64,34 @@
#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
static void msm_irq_ack(unsigned int irq)
static void msm_irq_ack(struct irq_data *d)
{
void __iomem *reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
irq = 1 << (irq & 31);
writel(irq, reg);
void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0);
writel(1 << (d->irq & 31), reg);
}
static void msm_irq_mask(unsigned int irq)
static void msm_irq_mask(struct irq_data *d)
{
void __iomem *reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
writel(1 << (irq & 31), reg);
void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0);
writel(1 << (d->irq & 31), reg);
}
static void msm_irq_unmask(unsigned int irq)
static void msm_irq_unmask(struct irq_data *d)
{
void __iomem *reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
writel(1 << (irq & 31), reg);
void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0);
writel(1 << (d->irq & 31), reg);
}
static int msm_irq_set_wake(unsigned int irq, unsigned int on)
static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
{
return -EINVAL;
}
static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
void __iomem *treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
void __iomem *preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
int b = 1 << (irq & 31);
void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0);
void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0);
int b = 1 << (d->irq & 31);
if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
writel(readl(preg) | b, preg);
@ -101,22 +100,22 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
writel(readl(treg) | b, treg);
irq_desc[irq].handle_irq = handle_edge_irq;
irq_desc[d->irq].handle_irq = handle_edge_irq;
}
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
writel(readl(treg) & (~b), treg);
irq_desc[irq].handle_irq = handle_level_irq;
irq_desc[d->irq].handle_irq = handle_level_irq;
}
return 0;
}
static struct irq_chip msm_irq_chip = {
.name = "msm",
.ack = msm_irq_ack,
.mask = msm_irq_mask,
.unmask = msm_irq_unmask,
.set_wake = msm_irq_set_wake,
.set_type = msm_irq_set_type,
.name = "msm",
.irq_ack = msm_irq_ack,
.irq_mask = msm_irq_mask,
.irq_unmask = msm_irq_unmask,
.irq_set_wake = msm_irq_set_wake,
.irq_set_type = msm_irq_set_type,
};
void __init msm_init_irq(void)

39
arch/arm/mach-msm/sirc.c
View File

@ -42,12 +42,11 @@ static struct sirc_cascade_regs sirc_reg_table[] = {
/* Mask off the given interrupt. Keep the int_enable mask in sync with
the enable reg, so it can be restored after power collapse. */
static void sirc_irq_mask(unsigned int irq)
static void sirc_irq_mask(struct irq_data *d)
{
unsigned int mask;
mask = 1 << (irq - FIRST_SIRC_IRQ);
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_enable_clear);
int_enable &= ~mask;
return;
@ -55,31 +54,31 @@ static void sirc_irq_mask(unsigned int irq)
/* Unmask the given interrupt. Keep the int_enable mask in sync with
the enable reg, so it can be restored after power collapse. */
static void sirc_irq_unmask(unsigned int irq)
static void sirc_irq_unmask(struct irq_data *d)
{
unsigned int mask;
mask = 1 << (irq - FIRST_SIRC_IRQ);
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_enable_set);
int_enable |= mask;
return;
}
static void sirc_irq_ack(unsigned int irq)
static void sirc_irq_ack(struct irq_data *d)
{
unsigned int mask;
mask = 1 << (irq - FIRST_SIRC_IRQ);
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_clear);
return;
}
static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned int mask;
/* Used to set the interrupt enable mask during power collapse. */
mask = 1 << (irq - FIRST_SIRC_IRQ);
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
if (on)
wake_enable |= mask;
else
@ -88,12 +87,12 @@ static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
return 0;
}
static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
unsigned int mask;
unsigned int val;
mask = 1 << (irq - FIRST_SIRC_IRQ);
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
val = readl(sirc_regs.int_polarity);
if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
@ -106,10 +105,10 @@ static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
val = readl(sirc_regs.int_type);
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
val |= mask;
irq_desc[irq].handle_irq = handle_edge_irq;
irq_desc[d->irq].handle_irq = handle_edge_irq;
} else {
val &= ~mask;
irq_desc[irq].handle_irq = handle_level_irq;
irq_desc[d->irq].handle_irq = handle_level_irq;
}
writel(val, sirc_regs.int_type);
@ -139,16 +138,16 @@ static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
;
generic_handle_irq(sirq+FIRST_SIRC_IRQ);
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
}
static struct irq_chip sirc_irq_chip = {
.name = "sirc",
.ack = sirc_irq_ack,
.mask = sirc_irq_mask,
.unmask = sirc_irq_unmask,
.set_wake = sirc_irq_set_wake,
.set_type = sirc_irq_set_type,
.name = "sirc",
.irq_ack = sirc_irq_ack,
.irq_mask = sirc_irq_mask,
.irq_unmask = sirc_irq_unmask,
.irq_set_wake = sirc_irq_set_wake,
.irq_set_type = sirc_irq_set_type,
};
void __init msm_init_sirc(void)

4
arch/arm/mach-mx3/mach-mx31_3ds.c
View File

@ -147,10 +147,10 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
.init_data = &pwgtx_init,
}, {
.id = MC13783_REGU_GPO1, /* Turn on 1.8V */
.id = MC13783_REG_GPO1, /* Turn on 1.8V */
.init_data = &gpo_init,
}, {
.id = MC13783_REGU_GPO3, /* Turn on 3.3V */
.id = MC13783_REG_GPO3, /* Turn on 3.3V */
.init_data = &gpo_init,
},
};

18
arch/arm/mach-mx3/mach-mx31ads.c
View File

@ -162,9 +162,9 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
* Disable an expio pin's interrupt by setting the bit in the imr.
* @param irq an expio virtual irq number
*/
static void expio_mask_irq(u32 irq)
static void expio_mask_irq(struct irq_data *d)
{
u32 expio = MXC_IRQ_TO_EXPIO(irq);
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
/* mask the interrupt */
__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
__raw_readw(PBC_INTMASK_CLEAR_REG);
@ -174,9 +174,9 @@ static void expio_mask_irq(u32 irq)
* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
* @param irq an expanded io virtual irq number
*/
static void expio_ack_irq(u32 irq)
static void expio_ack_irq(struct irq_data *d)
{
u32 expio = MXC_IRQ_TO_EXPIO(irq);
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
/* clear the interrupt status */
__raw_writew(1 << expio, PBC_INTSTATUS_REG);
}
@ -185,18 +185,18 @@ static void expio_ack_irq(u32 irq)
* Enable a expio pin's interrupt by clearing the bit in the imr.
* @param irq a expio virtual irq number
*/
static void expio_unmask_irq(u32 irq)
static void expio_unmask_irq(struct irq_data *d)
{
u32 expio = MXC_IRQ_TO_EXPIO(irq);
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
/* unmask the interrupt */
__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
}
static struct irq_chip expio_irq_chip = {
.name = "EXPIO(CPLD)",
.ack = expio_ack_irq,
.mask = expio_mask_irq,
.unmask = expio_unmask_irq,
.irq_ack = expio_ack_irq,
.irq_mask = expio_mask_irq,
.irq_unmask = expio_unmask_irq,
};
static void __init mx31ads_init_expio(void)

20
arch/arm/mach-mx5/Kconfig
View File

@ -50,6 +50,7 @@ config MACH_MX51_BABBAGE
config MACH_MX51_3DS
bool "Support MX51PDK (3DS)"
select SOC_IMX51
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
@ -77,6 +78,7 @@ choice
config MACH_EUKREA_MBIMX51_BASEBOARD
prompt "Eukrea MBIMX51 development board"
bool
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
This adds board specific devices that can be found on Eukrea's
@ -124,10 +126,28 @@ config MACH_MX53_EVK
bool "Support MX53 EVK platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX53 EVK platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX53_SMD
bool "Support MX53 SMD platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for MX53 SMD platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX53_LOCO
bool "Support MX53 LOCO platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX50_RDP
bool "Support MX50 reference design platform"

2
arch/arm/mach-mx5/Makefile
View File

@ -10,6 +10,8 @@ obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o

5
arch/arm/mach-mx5/board-mx51_3ds.c
View File

@ -12,7 +12,6 @@
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <asm/mach-types.h>
@ -120,14 +119,14 @@ static int mx51_3ds_board_keymap[] = {
KEY(3, 5, KEY_BACK)
};
static struct matrix_keymap_data mx51_3ds_map_data = {
static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
.keymap = mx51_3ds_board_keymap,
.keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
};
static void mxc_init_keypad(void)
{
mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
imx51_add_imx_keypad(&mx51_3ds_map_data);
}
#else
static inline void mxc_init_keypad(void)

74
arch/arm/mach-mx5/board-mx53_evk.c
View File

@ -21,6 +21,11 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -29,6 +34,10 @@
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
#include "crm_regs.h"
#include "devices-imx53.h"
@ -47,6 +56,14 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
MX53_PAD_ATA_CS_1__UART3_RXD,
MX53_PAD_ATA_DA_1__UART3_CTS,
MX53_PAD_ATA_DA_2__UART3_RTS,
MX53_PAD_EIM_D16__CSPI1_SCLK,
MX53_PAD_EIM_D17__CSPI1_MISO,
MX53_PAD_EIM_D18__CSPI1_MOSI,
/* ecspi chip select lines */
MX53_PAD_EIM_EB2__GPIO_2_30,
MX53_PAD_EIM_D19__GPIO_3_19,
};
static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@ -60,11 +77,68 @@ static inline void mx53_evk_init_uart(void)
imx53_add_imx_uart(2, &mx53_evk_uart_pdata);
}
static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
.bitrate = 100000,
};
static inline void mx53_evk_fec_reset(void)
{
int ret;
/* reset FEC PHY */
ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
if (ret) {
printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
return;
}
gpio_direction_output(SMD_FEC_PHY_RST, 0);
gpio_set_value(SMD_FEC_PHY_RST, 0);
msleep(1);
gpio_set_value(SMD_FEC_PHY_RST, 1);
}
static struct fec_platform_data mx53_evk_fec_pdata = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
{
.modalias = "mtd_dataflash",
.max_speed_hz = 25000000,
.bus_num = 0,
.chip_select = 1,
.mode = SPI_MODE_0,
.platform_data = NULL,
},
};
static int mx53_evk_spi_cs[] = {
EVK_ECSPI1_CS0,
EVK_ECSPI1_CS1,
};
static const struct spi_imx_master mx53_evk_spi_data __initconst = {
.chipselect = mx53_evk_spi_cs,
.num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
};
static void __init mx53_evk_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
ARRAY_SIZE(mx53_evk_pads));
mx53_evk_init_uart();
mx53_evk_fec_reset();
imx53_add_fec(&mx53_evk_fec_pdata);
imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
imx53_add_sdhci_esdhc_imx(0, NULL);
imx53_add_sdhci_esdhc_imx(1, NULL);
spi_register_board_info(mx53_evk_spi_board_info,
ARRAY_SIZE(mx53_evk_spi_board_info));
imx53_add_ecspi(0, &mx53_evk_spi_data);
}
static void __init mx53_evk_timer_init(void)

111
arch/arm/mach-mx5/board-mx53_loco.c Normal file
View File

@ -0,0 +1,111 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "crm_regs.h"
#include "devices-imx53.h"
#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
static iomux_v3_cfg_t mx53_loco_pads[] = {
MX53_PAD_CSI0_D10__UART1_TXD,
MX53_PAD_CSI0_D11__UART1_RXD,
MX53_PAD_ATA_DIOW__UART1_TXD,
MX53_PAD_ATA_DMACK__UART1_RXD,
MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
MX53_PAD_ATA_DMARQ__UART2_TXD,
MX53_PAD_ATA_DIOR__UART2_RTS,
MX53_PAD_ATA_INTRQ__UART2_CTS,
MX53_PAD_ATA_CS_0__UART3_TXD,
MX53_PAD_ATA_CS_1__UART3_RXD,
MX53_PAD_ATA_DA_1__UART3_CTS,
MX53_PAD_ATA_DA_2__UART3_RTS,
};
static const struct imxuart_platform_data mx53_loco_uart_data __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static inline void mx53_loco_init_uart(void)
{
imx53_add_imx_uart(0, &mx53_loco_uart_data);
imx53_add_imx_uart(1, &mx53_loco_uart_data);
imx53_add_imx_uart(2, &mx53_loco_uart_data);
}
static inline void mx53_loco_fec_reset(void)
{
int ret;
/* reset FEC PHY */
ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
if (ret) {
printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
return;
}
gpio_direction_output(LOCO_FEC_PHY_RST, 0);
msleep(1);
gpio_set_value(LOCO_FEC_PHY_RST, 1);
}
static struct fec_platform_data mx53_loco_fec_data = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static void __init mx53_loco_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
ARRAY_SIZE(mx53_loco_pads));
mx53_loco_init_uart();
mx53_loco_fec_reset();
imx53_add_fec(&mx53_loco_fec_data);
}
static void __init mx53_loco_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 0, 0);
}
static struct sys_timer mx53_loco_timer = {
.init = mx53_loco_timer_init,
};
MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
.map_io = mx53_map_io,
.init_irq = mx53_init_irq,
.init_machine = mx53_loco_board_init,
.timer = &mx53_loco_timer,
MACHINE_END

111
arch/arm/mach-mx5/board-mx53_smd.c Normal file
View File

@ -0,0 +1,111 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "crm_regs.h"
#include "devices-imx53.h"
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
static iomux_v3_cfg_t mx53_smd_pads[] = {
MX53_PAD_CSI0_D10__UART1_TXD,
MX53_PAD_CSI0_D11__UART1_RXD,
MX53_PAD_ATA_DIOW__UART1_TXD,
MX53_PAD_ATA_DMACK__UART1_RXD,
MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
MX53_PAD_ATA_DMARQ__UART2_TXD,
MX53_PAD_ATA_DIOR__UART2_RTS,
MX53_PAD_ATA_INTRQ__UART2_CTS,
MX53_PAD_ATA_CS_0__UART3_TXD,
MX53_PAD_ATA_CS_1__UART3_RXD,
MX53_PAD_ATA_DA_1__UART3_CTS,
MX53_PAD_ATA_DA_2__UART3_RTS,
};
static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static inline void mx53_smd_init_uart(void)
{
imx53_add_imx_uart(0, &mx53_smd_uart_data);
imx53_add_imx_uart(1, &mx53_smd_uart_data);
imx53_add_imx_uart(2, &mx53_smd_uart_data);
}
static inline void mx53_smd_fec_reset(void)
{
int ret;
/* reset FEC PHY */
ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
if (ret) {
printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
return;
}
gpio_direction_output(SMD_FEC_PHY_RST, 0);
msleep(1);
gpio_set_value(SMD_FEC_PHY_RST, 1);
}
static struct fec_platform_data mx53_smd_fec_data = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static void __init mx53_smd_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
ARRAY_SIZE(mx53_smd_pads));
mx53_smd_init_uart();
mx53_smd_fec_reset();
imx53_add_fec(&mx53_smd_fec_data);
}
static void __init mx53_smd_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mx53_smd_timer = {
.init = mx53_smd_timer_init,
};
MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
.map_io = mx53_map_io,
.init_irq = mx53_init_irq,
.init_machine = mx53_smd_board_init,
.timer = &mx53_smd_timer,
MACHINE_END

18
arch/arm/mach-mx5/clock-mx51-mx53.c
View File

@ -1191,6 +1191,11 @@ DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
NULL, NULL, &ipg_clk, &gpt_ipg_clk);
DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
NULL, NULL, &ipg_clk, NULL);
DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
NULL, NULL, &ipg_clk, NULL);
/* I2C */
DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
NULL, NULL, &ipg_clk, NULL);
@ -1283,6 +1288,8 @@ static struct clk_lookup mx51_lookups[] = {
_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
_REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
_REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
@ -1295,7 +1302,7 @@ static struct clk_lookup mx51_lookups[] = {
_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
_REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
_REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
@ -1326,6 +1333,13 @@ static struct clk_lookup mx53_lookups[] = {
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
_REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
_REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
_REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
};
static void clk_tree_init(void)
@ -1363,7 +1377,6 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
clk_tree_init();
clk_set_parent(&uart_root_clk, &pll3_sw_clk);
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
@ -1406,6 +1419,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
clk_tree_init();
clk_set_parent(&uart_root_clk, &pll3_sw_clk);
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);

8
arch/arm/mach-mx5/devices-imx51.h
View File

@ -47,3 +47,11 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst;
#define imx51_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst;
#define imx51_add_mxc_pwm(id) \
imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
extern const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst;
#define imx51_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)

18
arch/arm/mach-mx5/devices-imx53.h
View File

@ -8,6 +8,24 @@
#include <mach/mx53.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx53_fec_data __initconst;
#define imx53_add_fec(pdata) \
imx_add_fec(&imx53_fec_data, pdata)
extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst;
#define imx53_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
extern const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst;
#define imx53_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx53_sdhci_esdhc_imx_data[] __initconst;
#define imx53_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
#define imx53_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx53_ecspi_data[id], pdata)

19
arch/arm/mach-mx5/devices.c
View File

@ -120,25 +120,6 @@ struct platform_device mxc_usbh2_device = {
},
};
static struct resource mxc_kpp_resources[] = {
{
.start = MX51_MXC_INT_KPP,
.end = MX51_MXC_INT_KPP,
.flags = IORESOURCE_IRQ,
} , {
.start = MX51_KPP_BASE_ADDR,
.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_keypad_device = {
.name = "imx-keypad",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_kpp_resources),
.resource = mxc_kpp_resources,
};
static struct mxc_gpio_port mxc_gpio_ports[] = {
{
.chip.label = "gpio-0",

1
arch/arm/mach-mx5/devices.h
View File

@ -3,4 +3,3 @@ extern struct platform_device mxc_usbh1_device;
extern struct platform_device mxc_usbh2_device;
extern struct platform_device mxc_usbdr_udc_device;
extern struct platform_device mxc_hsi2c_device;
extern struct platform_device mxc_keypad_device;

5
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View File

@ -21,7 +21,6 @@
#include <linux/fsl_devices.h>
#include <linux/i2c/tsc2007.h>
#include <linux/leds.h>
#include <linux/input/matrix_keypad.h>
#include <mach/common.h>
#include <mach/hardware.h>
@ -157,7 +156,7 @@ static int mbimx51_keymap[] = {
KEY(3, 3, KEY_ENTER),
};
static struct matrix_keymap_data mbimx51_map_data = {
static const struct matrix_keymap_data mbimx51_map_data __initconst = {
.keymap = mbimx51_keymap,
.keymap_size = ARRAY_SIZE(mbimx51_keymap),
};
@ -209,7 +208,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
mxc_register_device(&mxc_keypad_device, &mbimx51_map_data);
imx51_add_imx_keypad(&mbimx51_map_data);
gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
gpio_direction_input(MBIMX51_TSC2007_GPIO);

4
arch/arm/mach-mxs/Kconfig
View File

@ -15,7 +15,7 @@ comment "MXS platforms:"
config MACH_MX23EVK
bool "Support MX23EVK Platform"
select SOC_IMX23
select MXS_HAVE_PLATFORM_DUART
select MXS_HAVE_AMBA_DUART
default y
help
Include support for MX23EVK platform. This includes specific
@ -24,7 +24,7 @@ config MACH_MX23EVK
config MACH_MX28EVK
bool "Support MX28EVK Platform"
select SOC_IMX28
select MXS_HAVE_PLATFORM_DUART
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_FEC
default y
help

13
arch/arm/mach-mxs/clock-mx23.c
View File

@ -21,6 +21,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/clkdev.h>
#include <asm/clkdev.h>
#include <asm/div64.h>
@ -437,10 +438,12 @@ _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
/* for amba bus driver */
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
/* for amba-pl011 driver */
_REGISTER_CLOCK("duart", NULL, uart_clk)
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK(NULL, "hclk", hbus_clk)
_REGISTER_CLOCK(NULL, "xclk", xbus_clk)
_REGISTER_CLOCK(NULL, "usb", usb_clk)
_REGISTER_CLOCK(NULL, "audio", audio_clk)
_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
@ -518,6 +521,12 @@ int __init mx23_clocks_init(void)
{
clk_misc_init();
clk_enable(&cpu_clk);
clk_enable(&hbus_clk);
clk_enable(&xbus_clk);
clk_enable(&emi_clk);
clk_enable(&uart_clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);

14
arch/arm/mach-mxs/clock-mx28.c
View File

@ -21,6 +21,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/clkdev.h>
#include <asm/clkdev.h>
#include <asm/div64.h>
@ -602,7 +603,12 @@ _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
/* for amba bus driver */
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
/* for amba-pl011 driver */
_REGISTER_CLOCK("duart", NULL, uart_clk)
_REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK("pll2", NULL, pll2_clk)
@ -726,6 +732,12 @@ int __init mx28_clocks_init(void)
{
clk_misc_init();
clk_enable(&cpu_clk);
clk_enable(&hbus_clk);
clk_enable(&xbus_clk);
clk_enable(&emi_clk);
clk_enable(&uart_clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);

4
arch/arm/mach-mxs/devices-mx23.h
View File

@ -11,6 +11,6 @@
#include <mach/mx23.h>
#include <mach/devices-common.h>
extern const struct mxs_duart_data mx23_duart_data __initconst;
extern const struct amba_device mx23_duart_device __initconst;
#define mx23_add_duart() \
mxs_add_duart(&mx23_duart_data)
mxs_add_duart(&mx23_duart_device)

4
arch/arm/mach-mxs/devices-mx28.h
View File

@ -11,9 +11,9 @@
#include <mach/mx28.h>
#include <mach/devices-common.h>
extern const struct mxs_duart_data mx28_duart_data __initconst;
extern const struct amba_device mx28_duart_device __initconst;
#define mx28_add_duart() \
mxs_add_duart(&mx28_duart_data)
mxs_add_duart(&mx28_duart_device)
extern const struct mxs_fec_data mx28_fec_data[] __initconst;
#define mx28_add_fec(id, pdata) \

17
arch/arm/mach-mxs/devices.c
View File

@ -19,9 +19,8 @@
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <mach/common.h>
#include <linux/amba/bus.h>
struct platform_device *__init mxs_add_platform_device_dmamask(
const char *name, int id,
@ -73,3 +72,17 @@ err:
return pdev;
}
int __init mxs_add_amba_device(const struct amba_device *dev)
{
struct amba_device *adev = kmalloc(sizeof(*adev), GFP_KERNEL);
if (!adev) {
pr_err("%s: failed to allocate memory", __func__);
return -ENOMEM;
}
*adev = *dev;
return amba_device_register(adev, &iomem_resource);
}

3
arch/arm/mach-mxs/devices/Kconfig
View File

@ -1,5 +1,6 @@
config MXS_HAVE_PLATFORM_DUART
config MXS_HAVE_AMBA_DUART
bool
select ARM_AMBA
config MXS_HAVE_PLATFORM_FEC
bool

2
arch/arm/mach-mxs/devices/Makefile
View File

@ -1,2 +1,2 @@
obj-$(CONFIG_MXS_HAVE_PLATFORM_DUART) += platform-duart.o
obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o

40
arch/arm/mach-mxs/devices/amba-duart.c Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright (C) 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <asm/irq.h>
#include <mach/mx23.h>
#include <mach/mx28.h>
#include <mach/devices-common.h>
#define MXS_AMBA_DUART_DEVICE(name, soc) \
const struct amba_device name##_device __initconst = { \
.dev = { \
.init_name = "duart", \
}, \
.res = { \
.start = soc ## _DUART_BASE_ADDR, \
.end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \
.flags = IORESOURCE_MEM, \
}, \
.irq = {soc ## _INT_DUART, NO_IRQ}, \
}
#ifdef CONFIG_SOC_IMX23
MXS_AMBA_DUART_DEVICE(mx23_duart, MX23);
#endif
#ifdef CONFIG_SOC_IMX28
MXS_AMBA_DUART_DEVICE(mx28_duart, MX28);
#endif
int __init mxs_add_duart(const struct amba_device *dev)
{
return mxs_add_amba_device(dev);
}

48
arch/arm/mach-mxs/devices/platform-duart.c
View File

@ -1,48 +0,0 @@
/*
* Copyright (C) 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx23.h>
#include <mach/mx28.h>
#include <mach/devices-common.h>
#define mxs_duart_data_entry(soc) \
{ \
.iobase = soc ## _DUART_BASE_ADDR, \
.irq = soc ## _INT_DUART, \
}
#ifdef CONFIG_SOC_IMX23
const struct mxs_duart_data mx23_duart_data __initconst =
mxs_duart_data_entry(MX23);
#endif
#ifdef CONFIG_SOC_IMX28
const struct mxs_duart_data mx28_duart_data __initconst =
mxs_duart_data_entry(MX28);
#endif
struct platform_device *__init mxs_add_duart(
const struct mxs_duart_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_8K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return mxs_add_platform_device("mxs-duart", 0, res, ARRAY_SIZE(res),
NULL, 0);
}

2
arch/arm/mach-mxs/devices/platform-fec.c
View File

@ -45,6 +45,6 @@ struct platform_device *__init mxs_add_fec(
},
};
return mxs_add_platform_device("fec", data->id,
return mxs_add_platform_device("imx28-fec", data->id,
res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
}

11
arch/arm/mach-mxs/include/mach/devices-common.h
View File

@ -9,6 +9,7 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/amba/bus.h>
struct platform_device *mxs_add_platform_device_dmamask(
const char *name, int id,
@ -24,14 +25,10 @@ static inline struct platform_device *mxs_add_platform_device(
name, id, res, num_resources, data, size_data, 0);
}
int __init mxs_add_amba_device(const struct amba_device *dev);
/* duart */
struct mxs_duart_data {
resource_size_t iobase;
resource_size_t iosize;
resource_size_t irq;
};
struct platform_device *__init mxs_add_duart(
const struct mxs_duart_data *data);
int __init mxs_add_duart(const struct amba_device *dev);
/* fec */
#include <linux/fec.h>

26
arch/arm/mach-mxs/mach-mx28evk.c
View File

@ -57,6 +57,19 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_ENET_CLK__CLKCTRL_ENET |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
/* fec1 */
MX28_PAD_ENET0_CRS__ENET1_RX_EN |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_ENET0_RXD2__ENET1_RXD0 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_ENET0_RXD3__ENET1_RXD1 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_ENET0_COL__ENET1_TX_EN |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_ENET0_TXD2__ENET1_TXD0 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_ENET0_TXD3__ENET1_TXD1 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
/* phy power line */
MX28_PAD_SSP1_DATA3__GPIO_2_15 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
@ -106,8 +119,14 @@ static void __init mx28evk_fec_reset(void)
gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
}
static const struct fec_platform_data mx28_fec_pdata __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
static struct fec_platform_data mx28_fec_pdata[] = {
{
/* fec0 */
.phy = PHY_INTERFACE_MODE_RMII,
}, {
/* fec1 */
.phy = PHY_INTERFACE_MODE_RMII,
},
};
static void __init mx28evk_init(void)
@ -117,7 +136,8 @@ static void __init mx28evk_init(void)
mx28_add_duart();
mx28evk_fec_reset();
mx28_add_fec(0, &mx28_fec_pdata);
mx28_add_fec(0, &mx28_fec_pdata[0]);
mx28_add_fec(1, &mx28_fec_pdata[1]);
}
static void __init mx28evk_timer_init(void)

30
arch/arm/mach-netx/generic.c
View File

@ -88,13 +88,13 @@ netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
}
static int
netx_hif_irq_type(unsigned int _irq, unsigned int type)
netx_hif_irq_type(struct irq_data *d, unsigned int type)
{
unsigned int val, irq;
val = readl(NETX_DPMAS_IF_CONF1);
irq = _irq - NETX_IRQ_HIF_CHAINED(0);
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
if (type & IRQ_TYPE_EDGE_RISING) {
DEBUG_IRQ("rising edges\n");
@ -119,49 +119,49 @@ netx_hif_irq_type(unsigned int _irq, unsigned int type)
}
static void
netx_hif_ack_irq(unsigned int _irq)
netx_hif_ack_irq(struct irq_data *d)
{
unsigned int val, irq;
irq = _irq - NETX_IRQ_HIF_CHAINED(0);
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
writel((1 << 24) << irq, NETX_DPMAS_INT_STAT);
val = readl(NETX_DPMAS_INT_EN);
val &= ~((1 << 24) << irq);
writel(val, NETX_DPMAS_INT_EN);
DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
}
static void
netx_hif_mask_irq(unsigned int _irq)
netx_hif_mask_irq(struct irq_data *d)
{
unsigned int val, irq;
irq = _irq - NETX_IRQ_HIF_CHAINED(0);
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
val = readl(NETX_DPMAS_INT_EN);
val &= ~((1 << 24) << irq);
writel(val, NETX_DPMAS_INT_EN);
DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
}
static void
netx_hif_unmask_irq(unsigned int _irq)
netx_hif_unmask_irq(struct irq_data *d)
{
unsigned int val, irq;
irq = _irq - NETX_IRQ_HIF_CHAINED(0);
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
val = readl(NETX_DPMAS_INT_EN);
val |= (1 << 24) << irq;
writel(val, NETX_DPMAS_INT_EN);
DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
}
static struct irq_chip netx_hif_chip = {
.ack = netx_hif_ack_irq,
.mask = netx_hif_mask_irq,
.unmask = netx_hif_unmask_irq,
.set_type = netx_hif_irq_type,
.irq_ack = netx_hif_ack_irq,
.irq_mask = netx_hif_mask_irq,
.irq_unmask = netx_hif_unmask_irq,
.irq_set_type = netx_hif_irq_type,
};
void __init netx_init_irq(void)

28
arch/arm/mach-ns9xxx/board-a9m9750dev.c
View File

@ -37,44 +37,44 @@ void __init board_a9m9750dev_map_io(void)
ARRAY_SIZE(board_a9m9750dev_io_desc));
}
static void a9m9750dev_fpga_ack_irq(unsigned int irq)
static void a9m9750dev_fpga_ack_irq(struct irq_data *d)
{
/* nothing */
}
static void a9m9750dev_fpga_mask_irq(unsigned int irq)
static void a9m9750dev_fpga_mask_irq(struct irq_data *d)
{
u8 ier;
ier = __raw_readb(FPGA_IER);
ier &= ~(1 << (irq - FPGA_IRQ(0)));
ier &= ~(1 << (d->irq - FPGA_IRQ(0)));
__raw_writeb(ier, FPGA_IER);
}
static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
static void a9m9750dev_fpga_maskack_irq(struct irq_data *d)
{
a9m9750dev_fpga_mask_irq(irq);
a9m9750dev_fpga_ack_irq(irq);
a9m9750dev_fpga_mask_irq(d);
a9m9750dev_fpga_ack_irq(d);
}
static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
static void a9m9750dev_fpga_unmask_irq(struct irq_data *d)
{
u8 ier;
ier = __raw_readb(FPGA_IER);
ier |= 1 << (irq - FPGA_IRQ(0));
ier |= 1 << (d->irq - FPGA_IRQ(0));
__raw_writeb(ier, FPGA_IER);
}
static struct irq_chip a9m9750dev_fpga_chip = {
.ack = a9m9750dev_fpga_ack_irq,
.mask = a9m9750dev_fpga_mask_irq,
.mask_ack = a9m9750dev_fpga_maskack_irq,
.unmask = a9m9750dev_fpga_unmask_irq,
.irq_ack = a9m9750dev_fpga_ack_irq,
.irq_mask = a9m9750dev_fpga_mask_irq,
.irq_mask_ack = a9m9750dev_fpga_maskack_irq,
.irq_unmask = a9m9750dev_fpga_unmask_irq,
};
static void a9m9750dev_fpga_demux_handler(unsigned int irq,
@ -82,7 +82,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
{
u8 stat = __raw_readb(FPGA_ISR);
desc->chip->mask_ack(irq);
desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
while (stat != 0) {
int irqno = fls(stat) - 1;
@ -92,7 +92,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
generic_handle_irq(FPGA_IRQ(irqno));
}
desc->chip->unmask(irq);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
void __init board_a9m9750dev_init_irq(void)

28
arch/arm/mach-ns9xxx/irq.c
View File

@ -22,40 +22,40 @@
#define irq2prio(i) (i)
#define prio2irq(p) (p)
static void ns9xxx_mask_irq(unsigned int irq)
static void ns9xxx_mask_irq(struct irq_data *d)
{
/* XXX: better use cpp symbols */
int prio = irq2prio(irq);
int prio = irq2prio(d->irq);
u32 ic = __raw_readl(SYS_IC(prio / 4));
ic &= ~(1 << (7 + 8 * (3 - (prio & 3))));
__raw_writel(ic, SYS_IC(prio / 4));
}
static void ns9xxx_ack_irq(unsigned int irq)
static void ns9xxx_ack_irq(struct irq_data *d)
{
__raw_writel(0, SYS_ISRADDR);
}
static void ns9xxx_maskack_irq(unsigned int irq)
static void ns9xxx_maskack_irq(struct irq_data *d)
{
ns9xxx_mask_irq(irq);
ns9xxx_ack_irq(irq);
ns9xxx_mask_irq(d);
ns9xxx_ack_irq(d);
}
static void ns9xxx_unmask_irq(unsigned int irq)
static void ns9xxx_unmask_irq(struct irq_data *d)
{
/* XXX: better use cpp symbols */
int prio = irq2prio(irq);
int prio = irq2prio(d->irq);
u32 ic = __raw_readl(SYS_IC(prio / 4));
ic |= 1 << (7 + 8 * (3 - (prio & 3)));
__raw_writel(ic, SYS_IC(prio / 4));
}
static struct irq_chip ns9xxx_chip = {
.ack = ns9xxx_ack_irq,
.mask = ns9xxx_mask_irq,
.mask_ack = ns9xxx_maskack_irq,
.unmask = ns9xxx_unmask_irq,
.irq_ack = ns9xxx_ack_irq,
.irq_mask = ns9xxx_mask_irq,
.irq_mask_ack = ns9xxx_maskack_irq,
.irq_unmask = ns9xxx_unmask_irq,
};
#if 0
@ -92,10 +92,10 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
if (desc->status & IRQ_DISABLED)
out_mask:
desc->chip->mask(irq);
desc->irq_data.chip->irq_mask(&desc->irq_data);
/* ack unconditionally to unmask lower prio irqs */
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
raw_spin_unlock(&desc->lock);
}

16
arch/arm/mach-nuc93x/irq.c
View File

@ -25,9 +25,9 @@
#include <mach/hardware.h>
#include <mach/regs-irq.h>
static void nuc93x_irq_mask(unsigned int irq)
static void nuc93x_irq_mask(struct irq_data *d)
{
__raw_writel(1 << irq, REG_AIC_MDCR);
__raw_writel(1 << d->irq, REG_AIC_MDCR);
}
/*
@ -35,21 +35,21 @@ static void nuc93x_irq_mask(unsigned int irq)
* to REG_AIC_EOSCR for ACK
*/
static void nuc93x_irq_ack(unsigned int irq)
static void nuc93x_irq_ack(struct irq_data *d)
{
__raw_writel(0x01, REG_AIC_EOSCR);
}
static void nuc93x_irq_unmask(unsigned int irq)
static void nuc93x_irq_unmask(struct irq_data *d)
{
__raw_writel(1 << irq, REG_AIC_MECR);
__raw_writel(1 << d->irq, REG_AIC_MECR);
}
static struct irq_chip nuc93x_irq_chip = {
.ack = nuc93x_irq_ack,
.mask = nuc93x_irq_mask,
.unmask = nuc93x_irq_unmask,
.irq_ack = nuc93x_irq_ack,
.irq_mask = nuc93x_irq_mask,
.irq_unmask = nuc93x_irq_unmask,
};
void __init nuc93x_init_irq(void)

8
arch/arm/mach-omap1/ams-delta-fiq.c
View File

@ -49,7 +49,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
irq_desc = irq_to_desc(IH_GPIO_BASE);
if (irq_desc)
irq_chip = irq_desc->chip;
irq_chip = irq_desc->irq_data.chip;
/*
* For each handled GPIO interrupt, keep calling its interrupt handler
@ -62,13 +62,15 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
while (irq_counter[gpio] < fiq_count) {
if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
struct irq_data *d = irq_get_irq_data(irq_num);
/*
* It looks like handle_edge_irq() that
* OMAP GPIO edge interrupts default to,
* expects interrupt already unmasked.
*/
if (irq_chip && irq_chip->unmask)
irq_chip->unmask(irq_num);
if (irq_chip && irq_chip->irq_unmask)
irq_chip->irq_unmask(d);
}
generic_handle_irq(irq_num);

28
arch/arm/mach-omap1/fpga.c
View File

@ -30,9 +30,9 @@
#include <plat/fpga.h>
#include <mach/gpio.h>
static void fpga_mask_irq(unsigned int irq)
static void fpga_mask_irq(struct irq_data *d)
{
irq -= OMAP_FPGA_IRQ_BASE;
unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE;
if (irq < 8)
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
@ -58,14 +58,14 @@ static inline u32 get_fpga_unmasked_irqs(void)
}
static void fpga_ack_irq(unsigned int irq)
static void fpga_ack_irq(struct irq_data *d)
{
/* Don't need to explicitly ACK FPGA interrupts */
}
static void fpga_unmask_irq(unsigned int irq)
static void fpga_unmask_irq(struct irq_data *d)
{
irq -= OMAP_FPGA_IRQ_BASE;
unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE;
if (irq < 8)
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
@ -78,10 +78,10 @@ static void fpga_unmask_irq(unsigned int irq)
| (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
}
static void fpga_mask_ack_irq(unsigned int irq)
static void fpga_mask_ack_irq(struct irq_data *d)
{
fpga_mask_irq(irq);
fpga_ack_irq(irq);
fpga_mask_irq(d);
fpga_ack_irq(d);
}
void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
@ -105,17 +105,17 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
static struct irq_chip omap_fpga_irq_ack = {
.name = "FPGA-ack",
.ack = fpga_mask_ack_irq,
.mask = fpga_mask_irq,
.unmask = fpga_unmask_irq,
.irq_ack = fpga_mask_ack_irq,
.irq_mask = fpga_mask_irq,
.irq_unmask = fpga_unmask_irq,
};
static struct irq_chip omap_fpga_irq = {
.name = "FPGA",
.ack = fpga_ack_irq,
.mask = fpga_mask_irq,
.unmask = fpga_unmask_irq,
.irq_ack = fpga_ack_irq,
.irq_mask = fpga_mask_irq,
.irq_unmask = fpga_unmask_irq,
};
/*

44
arch/arm/mach-omap1/irq.c
View File

@ -70,48 +70,48 @@ static inline void irq_bank_writel(unsigned long value, int bank, int offset)
omap_writel(value, irq_banks[bank].base_reg + offset);
}
static void omap_ack_irq(unsigned int irq)
static void omap_ack_irq(struct irq_data *d)
{
if (irq > 31)
if (d->irq > 31)
omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
}
static void omap_mask_irq(unsigned int irq)
static void omap_mask_irq(struct irq_data *d)
{
int bank = IRQ_BANK(irq);
int bank = IRQ_BANK(d->irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l |= 1 << IRQ_BIT(irq);
l |= 1 << IRQ_BIT(d->irq);
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
static void omap_unmask_irq(unsigned int irq)
static void omap_unmask_irq(struct irq_data *d)
{
int bank = IRQ_BANK(irq);
int bank = IRQ_BANK(d->irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l &= ~(1 << IRQ_BIT(irq));
l &= ~(1 << IRQ_BIT(d->irq));
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
static void omap_mask_ack_irq(unsigned int irq)
static void omap_mask_ack_irq(struct irq_data *d)
{
omap_mask_irq(irq);
omap_ack_irq(irq);
omap_mask_irq(d);
omap_ack_irq(d);
}
static int omap_wake_irq(unsigned int irq, unsigned int enable)
static int omap_wake_irq(struct irq_data *d, unsigned int enable)
{
int bank = IRQ_BANK(irq);
int bank = IRQ_BANK(d->irq);
if (enable)
irq_banks[bank].wake_enable |= IRQ_BIT(irq);
irq_banks[bank].wake_enable |= IRQ_BIT(d->irq);
else
irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq);
return 0;
}
@ -168,10 +168,10 @@ static struct omap_irq_bank omap1610_irq_banks[] = {
static struct irq_chip omap_irq_chip = {
.name = "MPU",
.ack = omap_mask_ack_irq,
.mask = omap_mask_irq,
.unmask = omap_unmask_irq,
.set_wake = omap_wake_irq,
.irq_ack = omap_mask_ack_irq,
.irq_mask = omap_mask_irq,
.irq_unmask = omap_unmask_irq,
.irq_set_wake = omap_wake_irq,
};
void __init omap_init_irq(void)
@ -239,9 +239,9 @@ void __init omap_init_irq(void)
/* Unmask level 2 handler */
if (cpu_is_omap7xx())
omap_unmask_irq(INT_7XX_IH2_IRQ);
omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ));
else if (cpu_is_omap15xx())
omap_unmask_irq(INT_1510_IH2_IRQ);
omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ));
else if (cpu_is_omap16xx())
omap_unmask_irq(INT_1610_IH2_IRQ);
omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ));
}

22
arch/arm/mach-omap2/irq.c
View File

@ -100,13 +100,14 @@ static int omap_check_spurious(unsigned int irq)
}
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(unsigned int irq)
static void omap_ack_irq(struct irq_data *d)
{
intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}
static void omap_mask_irq(unsigned int irq)
static void omap_mask_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
if (cpu_is_omap34xx()) {
@ -128,8 +129,9 @@ static void omap_mask_irq(unsigned int irq)
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
}
static void omap_unmask_irq(unsigned int irq)
static void omap_unmask_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
irq &= (IRQ_BITS_PER_REG - 1);
@ -137,17 +139,17 @@ static void omap_unmask_irq(unsigned int irq)
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
}
static void omap_mask_ack_irq(unsigned int irq)
static void omap_mask_ack_irq(struct irq_data *d)
{
omap_mask_irq(irq);
omap_ack_irq(irq);
omap_mask_irq(d);
omap_ack_irq(d);
}
static struct irq_chip omap_irq_chip = {
.name = "INTC",
.ack = omap_mask_ack_irq,
.mask = omap_mask_irq,
.unmask = omap_unmask_irq,
.name = "INTC",
.irq_ack = omap_mask_ack_irq,
.irq_mask = omap_mask_irq,
.irq_unmask = omap_unmask_irq,
};
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)

62
arch/arm/mach-pnx4008/irq.c
View File

@ -36,44 +36,44 @@
static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
static void pnx4008_mask_irq(unsigned int irq)
static void pnx4008_mask_irq(struct irq_data *d)
{
__raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
__raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */
}
static void pnx4008_unmask_irq(unsigned int irq)
static void pnx4008_unmask_irq(struct irq_data *d)
{
__raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq)); /* unmask interrupt */
__raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */
}
static void pnx4008_mask_ack_irq(unsigned int irq)
static void pnx4008_mask_ack_irq(struct irq_data *d)
{
__raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
__raw_writel(INTC_BIT(irq), INTC_SR(irq)); /* clear interrupt status */
__raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */
__raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */
}
static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
{
switch (type) {
case IRQ_TYPE_EDGE_RISING:
__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
set_irq_handler(irq, handle_edge_irq);
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
set_irq_handler(d->irq, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
set_irq_handler(irq, handle_edge_irq);
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
set_irq_handler(d->irq, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
set_irq_handler(irq, handle_level_irq);
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
set_irq_handler(d->irq, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
set_irq_handler(irq, handle_level_irq);
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
set_irq_handler(d->irq, handle_level_irq);
break;
/* IRQ_TYPE_EDGE_BOTH is not supported */
@ -85,10 +85,10 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
}
static struct irq_chip pnx4008_irq_chip = {
.ack = pnx4008_mask_ack_irq,
.mask = pnx4008_mask_irq,
.unmask = pnx4008_unmask_irq,
.set_type = pnx4008_set_irq_type,
.irq_ack = pnx4008_mask_ack_irq,
.irq_mask = pnx4008_mask_irq,
.irq_unmask = pnx4008_unmask_irq,
.irq_set_type = pnx4008_set_irq_type,
};
void __init pnx4008_init_irq(void)
@ -99,14 +99,18 @@ void __init pnx4008_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
set_irq_flags(i, IRQF_VALID);
set_irq_chip(i, &pnx4008_irq_chip);
pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
}
/* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
pnx4008_irq_type[SUB1_IRQ_N]);
pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
pnx4008_irq_type[SUB2_IRQ_N]);
pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
pnx4008_irq_type[SUB1_FIQ_N]);
pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
pnx4008_irq_type[SUB2_FIQ_N]);
/* mask all others */
__raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |

23
arch/arm/mach-pxa/balloon3.c
View File

@ -477,25 +477,25 @@ static inline void balloon3_leds_init(void) {}
/******************************************************************************
* FPGA IRQ
******************************************************************************/
static void balloon3_mask_irq(unsigned int irq)
static void balloon3_mask_irq(struct irq_data *d)
{
int balloon3_irq = (irq - BALLOON3_IRQ(0));
int balloon3_irq = (d->irq - BALLOON3_IRQ(0));
balloon3_irq_enabled &= ~(1 << balloon3_irq);
__raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
}
static void balloon3_unmask_irq(unsigned int irq)
static void balloon3_unmask_irq(struct irq_data *d)
{
int balloon3_irq = (irq - BALLOON3_IRQ(0));
int balloon3_irq = (d->irq - BALLOON3_IRQ(0));
balloon3_irq_enabled |= (1 << balloon3_irq);
__raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
}
static struct irq_chip balloon3_irq_chip = {
.name = "FPGA",
.ack = balloon3_mask_irq,
.mask = balloon3_mask_irq,
.unmask = balloon3_unmask_irq,
.irq_ack = balloon3_mask_irq,
.irq_mask = balloon3_mask_irq,
.irq_unmask = balloon3_unmask_irq,
};
static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc)
@ -504,8 +504,13 @@ static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc)
balloon3_irq_enabled;
do {
/* clear useless edge notification */
if (desc->chip->ack)
desc->chip->ack(BALLOON3_AUX_NIRQ);
if (desc->irq_data.chip->irq_ack) {
struct irq_data *d;
d = irq_get_irq_data(BALLOON3_AUX_NIRQ);
desc->irq_data.chip->irq_ack(d);
}
while (pending) {
irq = BALLOON3_IRQ(0) + __ffs(pending);
generic_handle_irq(irq);

1
arch/arm/mach-pxa/clock-pxa3xx.c
View File

@ -115,7 +115,6 @@ static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
{
unsigned long acsr = ACSR;
unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
unsigned int smcfs = (acsr >> 23) & 0x7;
return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
df_clkdiv[(memclkcfg >> 16) & 0x3];

2
arch/arm/mach-pxa/cm-x2xx-pci.c
View File

@ -59,7 +59,7 @@ void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
{
/* clear our parent irq */
desc->chip->ack(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
it8152_irq_demux(irq, desc);
}

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