leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

platform-drivers-x86 for v5.10-1

Browse Source 
Rather calm cycle for PDx86, all these have been in for-next for
 a couple of days with no bot complaints.
 
 Highlights:
 - PMC TigerLake fixes and new RocketLake support
 - Various small fixes / updates in other drivers/tools
 
 The following is an automated git shortlog grouped by driver:
 
 MAINTAINERS:
  -  update X86 PLATFORM DRIVERS entry with new kernel.org git repo
  -  Update maintainers for pmc_core driver
 
 hp-wmi:
  -  add support for thermal policy
 
 intel_pmc_core:
  -  fix: Replace dev_dbg macro with dev_info()
  -  Add Intel RocketLake (RKL) support
  -  Clean up: Remove the duplicate comments and reorganize
  -  Fix the slp_s0 counter displayed value
  -  Fix TigerLake power gating status map
 
 mlx-platform:
  -  Add capability field to platform FAN description
  -  Remove PSU EEPROM configuration
 
 platform_data/mlxreg:
  -  Extend core platform structure
  -  Update module license
 
 pmc_core:
  -  Use descriptive names for LPM registers
 
 tools/power/x86/intel-speed-select:
  -  Update version for v5.10
  -  Fix missing base-freq core IDs
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCAAyFiEEuvA7XScYQRpenhd+kuxHeUQDJ9wFAl+FmAsUHGhkZWdvZWRl
 QHJlZGhhdC5jb20ACgkQkuxHeUQDJ9x5awf/VWn0gcSw1i+y+Q/KPw/RCMXrEQQm
 Bqyt++IDSonvjBUmxE7QYtPvHK7lecPLXUzLkcfSoUmEZSPGoqe4F5Hj+814lj8x
 fveScf2DwUQyEfj26y4rmza1K4h7VohjJ7rQm0+t15KamrcogLiwqDpvel4v90lp
 YVvJUxDBOJxCrMs5fAziZAP7FxD42d8j664DFCPONH3EsY/vZMfOnsDRKhjahtFp
 LTtWXY5LyFf5HARKhubv/gmDddR7FzZB8/xc/G1CXpOmUBTcSgHgXH1OE/ypBXIe
 LOdchGqL2WRTq71IUKsvEXYbLSOHOMbIfBr7eCwZRKfmQLjQ8HXqI7xl9A==
 =luk4
 -----END PGP SIGNATURE-----

Merge tag 'platform-drivers-x86-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86

Pull x86 platform driver updates from Hans de Goede:
 "Rather calm cycle for x86 platform drivers, all these have been in
  for-next for a couple of days with no bot complaints.

  Highlights:

   - PMC TigerLake fixes and new RocketLake support

   - various small fixes / updates in other drivers/tools"

* tag 'platform-drivers-x86-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86:
  MAINTAINERS: update X86 PLATFORM DRIVERS entry with new kernel.org git repo
  platform/x86: mlx-platform: Add capability field to platform FAN description
  platform_data/mlxreg: Extend core platform structure
  platform_data/mlxreg: Update module license
  platform/x86: mlx-platform: Remove PSU EEPROM configuration
  MAINTAINERS: Update maintainers for pmc_core driver
  platform/x86: intel_pmc_core: fix: Replace dev_dbg macro with dev_info()
  platform/x86: intel_pmc_core: Add Intel RocketLake (RKL) support
  platform/x86: intel_pmc_core: Clean up: Remove the duplicate comments and reorganize
  platform/x86: intel_pmc_core: Fix the slp_s0 counter displayed value
  platform/x86: intel_pmc_core: Fix TigerLake power gating status map
  platform/x86: pmc_core: Use descriptive names for LPM registers
  tools/power/x86/intel-speed-select: Update version for v5.10
  tools/power/x86/intel-speed-select: Fix missing base-freq core IDs
  platform/x86: hp-wmi: add support for thermal policy
This commit is contained in:
Linus Torvalds 2020-10-14 10:43:24 -07:00
commit 15cb5469fc
9 changed files with 122 additions and 116 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -8940,8 +8940,8 @@ F: arch/x86/include/asm/intel_punit_ipc.h
F: drivers/platform/x86/intel_punit_ipc.c F: drivers/platform/x86/intel_punit_ipc.c
INTEL PMC CORE DRIVER INTEL PMC CORE DRIVER
M: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> M: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
M: Vishwanath Somayaji <vishwanath.somayaji@intel.com> M: David E Box <david.e.box@intel.com>
L: platform-driver-x86@vger.kernel.org L: platform-driver-x86@vger.kernel.org
S: Maintained S: Maintained
F: drivers/platform/x86/intel_pmc_core* F: drivers/platform/x86/intel_pmc_core*
@ -18921,7 +18921,7 @@ M: Hans de Goede <hdegoede@redhat.com>
M: Mark Gross <mgross@linux.intel.com> M: Mark Gross <mgross@linux.intel.com>
L: platform-driver-x86@vger.kernel.org L: platform-driver-x86@vger.kernel.org
S: Maintained S: Maintained
T: git git://git.infradead.org/linux-platform-drivers-x86.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git
F: drivers/platform/olpc/ F: drivers/platform/olpc/
F: drivers/platform/x86/ F: drivers/platform/x86/

23
drivers/platform/x86/hp-wmi.c
View File

@ -81,6 +81,7 @@ enum hp_wmi_commandtype {
HPWMI_FEATURE2_QUERY = 0x0d, HPWMI_FEATURE2_QUERY = 0x0d,
HPWMI_WIRELESS2_QUERY = 0x1b, HPWMI_WIRELESS2_QUERY = 0x1b,
HPWMI_POSTCODEERROR_QUERY = 0x2a, HPWMI_POSTCODEERROR_QUERY = 0x2a,
HPWMI_THERMAL_POLICY_QUERY = 0x4c,
}; };
enum hp_wmi_command { enum hp_wmi_command {
@ -861,6 +862,26 @@ fail:
return err; return err;
} }
static int thermal_policy_setup(struct platform_device *device)
{
int err, tp;
tp = hp_wmi_read_int(HPWMI_THERMAL_POLICY_QUERY);
if (tp < 0)
return tp;
/*
* call thermal policy write command to ensure that the firmware correctly
* sets the OEM variables for the DPTF
*/
err = hp_wmi_perform_query(HPWMI_THERMAL_POLICY_QUERY, HPWMI_WRITE, &tp,
sizeof(tp), 0);
if (err)
return err;
return 0;
}
static int __init hp_wmi_bios_setup(struct platform_device *device) static int __init hp_wmi_bios_setup(struct platform_device *device)
{ {
/* clear detected rfkill devices */ /* clear detected rfkill devices */
@ -872,6 +893,8 @@ static int __init hp_wmi_bios_setup(struct platform_device *device)
if (hp_wmi_rfkill_setup(device)) if (hp_wmi_rfkill_setup(device))
hp_wmi_rfkill2_setup(device); hp_wmi_rfkill2_setup(device);
thermal_policy_setup(device);
return 0; return 0;
} }

121
drivers/platform/x86/intel_pmc_core.c
View File

@ -118,6 +118,10 @@ static const struct pmc_bit_map spt_pfear_map[] = {
}; };
static const struct pmc_bit_map *ext_spt_pfear_map[] = { static const struct pmc_bit_map *ext_spt_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of spt_reg_map for
* a list of core SoCs using this.
*/
spt_pfear_map, spt_pfear_map,
NULL NULL
}; };
@ -154,6 +158,7 @@ static const struct pmc_reg_map spt_reg_map = {
.ltr_show_sts = spt_ltr_show_map, .ltr_show_sts = spt_ltr_show_map,
.msr_sts = msr_map, .msr_sts = msr_map,
.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET, .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
.regmap_length = SPT_PMC_MMIO_REG_LEN, .regmap_length = SPT_PMC_MMIO_REG_LEN,
.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A, .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
@ -166,7 +171,6 @@ static const struct pmc_reg_map spt_reg_map = {
/* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */ /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
static const struct pmc_bit_map cnp_pfear_map[] = { static const struct pmc_bit_map cnp_pfear_map[] = {
/* Reserved for Cannon Lake but valid for Comet Lake */
{"PMC", BIT(0)}, {"PMC", BIT(0)},
{"OPI-DMI", BIT(1)}, {"OPI-DMI", BIT(1)},
{"SPI/eSPI", BIT(2)}, {"SPI/eSPI", BIT(2)},
@ -192,10 +196,6 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
{"SDX", BIT(4)}, {"SDX", BIT(4)},
{"SPE", BIT(5)}, {"SPE", BIT(5)},
{"Fuse", BIT(6)}, {"Fuse", BIT(6)},
/*
* Reserved for Cannon Lake but valid for Ice Lake, Comet Lake,
* Tiger Lake, Elkhart Lake and Jasper Lake.
*/
{"SBR8", BIT(7)}, {"SBR8", BIT(7)},
{"CSME_FSC", BIT(0)}, {"CSME_FSC", BIT(0)},
@ -239,10 +239,6 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
{"HDA_PGD4", BIT(2)}, {"HDA_PGD4", BIT(2)},
{"HDA_PGD5", BIT(3)}, {"HDA_PGD5", BIT(3)},
{"HDA_PGD6", BIT(4)}, {"HDA_PGD6", BIT(4)},
/*
* Reserved for Cannon Lake but valid for Ice Lake, Comet Lake,
* Tiger Lake, ELkhart Lake and Jasper Lake.
*/
{"PSF6", BIT(5)}, {"PSF6", BIT(5)},
{"PSF7", BIT(6)}, {"PSF7", BIT(6)},
{"PSF8", BIT(7)}, {"PSF8", BIT(7)},
@ -250,12 +246,15 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
}; };
static const struct pmc_bit_map *ext_cnp_pfear_map[] = { static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
cnp_pfear_map, cnp_pfear_map,
NULL NULL
}; };
static const struct pmc_bit_map icl_pfear_map[] = { static const struct pmc_bit_map icl_pfear_map[] = {
/* Ice Lake and Jasper Lake generation onwards only */
{"RES_65", BIT(0)}, {"RES_65", BIT(0)},
{"RES_66", BIT(1)}, {"RES_66", BIT(1)},
{"RES_67", BIT(2)}, {"RES_67", BIT(2)},
@ -268,13 +267,16 @@ static const struct pmc_bit_map icl_pfear_map[] = {
}; };
static const struct pmc_bit_map *ext_icl_pfear_map[] = { static const struct pmc_bit_map *ext_icl_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of icl_reg_map for
* a list of core SoCs using this.
*/
cnp_pfear_map, cnp_pfear_map,
icl_pfear_map, icl_pfear_map,
NULL NULL
}; };
static const struct pmc_bit_map tgl_pfear_map[] = { static const struct pmc_bit_map tgl_pfear_map[] = {
/* Tiger Lake and Elkhart Lake generation onwards only */
{"PSF9", BIT(0)}, {"PSF9", BIT(0)},
{"RES_66", BIT(1)}, {"RES_66", BIT(1)},
{"RES_67", BIT(2)}, {"RES_67", BIT(2)},
@ -286,6 +288,10 @@ static const struct pmc_bit_map tgl_pfear_map[] = {
}; };
static const struct pmc_bit_map *ext_tgl_pfear_map[] = { static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of tgl_reg_map for
* a list of core SoCs using this.
*/
cnp_pfear_map, cnp_pfear_map,
tgl_pfear_map, tgl_pfear_map,
NULL NULL
@ -369,7 +375,10 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
{"ISH", CNP_PMC_LTR_ISH}, {"ISH", CNP_PMC_LTR_ISH},
{"UFSX2", CNP_PMC_LTR_UFSX2}, {"UFSX2", CNP_PMC_LTR_UFSX2},
{"EMMC", CNP_PMC_LTR_EMMC}, {"EMMC", CNP_PMC_LTR_EMMC},
/* Reserved for Cannon Lake but valid for Ice Lake */ /*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
{"WIGIG", ICL_PMC_LTR_WIGIG}, {"WIGIG", ICL_PMC_LTR_WIGIG},
/* Below two cannot be used for LTR_IGNORE */ /* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
@ -380,6 +389,7 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
static const struct pmc_reg_map cnp_reg_map = { static const struct pmc_reg_map cnp_reg_map = {
.pfear_sts = ext_cnp_pfear_map, .pfear_sts = ext_cnp_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
.slps0_dbg_maps = cnp_slps0_dbg_maps, .slps0_dbg_maps = cnp_slps0_dbg_maps,
.ltr_show_sts = cnp_ltr_show_map, .ltr_show_sts = cnp_ltr_show_map,
.msr_sts = msr_map, .msr_sts = msr_map,
@ -396,6 +406,7 @@ static const struct pmc_reg_map cnp_reg_map = {
static const struct pmc_reg_map icl_reg_map = { static const struct pmc_reg_map icl_reg_map = {
.pfear_sts = ext_icl_pfear_map, .pfear_sts = ext_icl_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
.slps0_dbg_maps = cnp_slps0_dbg_maps, .slps0_dbg_maps = cnp_slps0_dbg_maps,
.ltr_show_sts = cnp_ltr_show_map, .ltr_show_sts = cnp_ltr_show_map,
.msr_sts = msr_map, .msr_sts = msr_map,
@ -409,7 +420,7 @@ static const struct pmc_reg_map icl_reg_map = {
.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED, .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
}; };
static const struct pmc_bit_map tgl_lpm0_map[] = { static const struct pmc_bit_map tgl_clocksource_status_map[] = {
{"USB2PLL_OFF_STS", BIT(18)}, {"USB2PLL_OFF_STS", BIT(18)},
{"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)}, {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
{"PCIe_Gen3PLL_OFF_STS", BIT(20)}, {"PCIe_Gen3PLL_OFF_STS", BIT(20)},
@ -425,35 +436,35 @@ static const struct pmc_bit_map tgl_lpm0_map[] = {
{} {}
}; };
static const struct pmc_bit_map tgl_lpm1_map[] = { static const struct pmc_bit_map tgl_power_gating_status_map[] = {
{"SPI_PG_STS", BIT(2)}, {"CSME_PG_STS", BIT(0)},
{"xHCI_PG_STS", BIT(3)}, {"SATA_PG_STS", BIT(1)},
{"PCIe_Ctrller_A_PG_STS", BIT(4)}, {"xHCI_PG_STS", BIT(2)},
{"PCIe_Ctrller_B_PG_STS", BIT(5)}, {"UFSX2_PG_STS", BIT(3)},
{"PCIe_Ctrller_C_PG_STS", BIT(6)}, {"OTG_PG_STS", BIT(5)},
{"GBE_PG_STS", BIT(7)}, {"SPA_PG_STS", BIT(6)},
{"SATA_PG_STS", BIT(8)}, {"SPB_PG_STS", BIT(7)},
{"HDA0_PG_STS", BIT(9)}, {"SPC_PG_STS", BIT(8)},
{"HDA1_PG_STS", BIT(10)}, {"SPD_PG_STS", BIT(9)},
{"HDA2_PG_STS", BIT(11)}, {"SPE_PG_STS", BIT(10)},
{"HDA3_PG_STS", BIT(12)}, {"SPF_PG_STS", BIT(11)},
{"PCIe_Ctrller_D_PG_STS", BIT(13)}, {"LSX_PG_STS", BIT(13)},
{"ISIO_PG_STS", BIT(14)}, {"P2SB_PG_STS", BIT(14)},
{"SMB_PG_STS", BIT(16)}, {"PSF_PG_STS", BIT(15)},
{"ISH_PG_STS", BIT(17)}, {"SBR_PG_STS", BIT(16)},
{"ITH_PG_STS", BIT(19)}, {"OPIDMI_PG_STS", BIT(17)},
{"SDX_PG_STS", BIT(20)}, {"THC0_PG_STS", BIT(18)},
{"xDCI_PG_STS", BIT(25)}, {"THC1_PG_STS", BIT(19)},
{"DCI_PG_STS", BIT(26)}, {"GBETSN_PG_STS", BIT(20)},
{"CSME0_PG_STS", BIT(27)}, {"GBE_PG_STS", BIT(21)},
{"CSME_KVM_PG_STS", BIT(28)}, {"LPSS_PG_STS", BIT(22)},
{"CSME1_PG_STS", BIT(29)}, {"MMP_UFSX2_PG_STS", BIT(23)},
{"CSME_CLINK_PG_STS", BIT(30)}, {"MMP_UFSX2B_PG_STS", BIT(24)},
{"CSME2_PG_STS", BIT(31)}, {"FIA_PG_STS", BIT(25)},
{} {}
}; };
static const struct pmc_bit_map tgl_lpm2_map[] = { static const struct pmc_bit_map tgl_d3_status_map[] = {
{"ADSP_D3_STS", BIT(0)}, {"ADSP_D3_STS", BIT(0)},
{"SATA_D3_STS", BIT(1)}, {"SATA_D3_STS", BIT(1)},
{"xHCI0_D3_STS", BIT(2)}, {"xHCI0_D3_STS", BIT(2)},
@ -468,7 +479,7 @@ static const struct pmc_bit_map tgl_lpm2_map[] = {
{} {}
}; };
static const struct pmc_bit_map tgl_lpm3_map[] = { static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
{"GPIO_COM0_VNN_REQ_STS", BIT(1)}, {"GPIO_COM0_VNN_REQ_STS", BIT(1)},
{"GPIO_COM1_VNN_REQ_STS", BIT(2)}, {"GPIO_COM1_VNN_REQ_STS", BIT(2)},
{"GPIO_COM2_VNN_REQ_STS", BIT(3)}, {"GPIO_COM2_VNN_REQ_STS", BIT(3)},
@ -493,7 +504,7 @@ static const struct pmc_bit_map tgl_lpm3_map[] = {
{} {}
}; };
static const struct pmc_bit_map tgl_lpm4_map[] = { static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
{"CPU_C10_REQ_STS_0", BIT(0)}, {"CPU_C10_REQ_STS_0", BIT(0)},
{"PCIe_LPM_En_REQ_STS_3", BIT(3)}, {"PCIe_LPM_En_REQ_STS_3", BIT(3)},
{"ITH_REQ_STS_5", BIT(5)}, {"ITH_REQ_STS_5", BIT(5)},
@ -509,7 +520,7 @@ static const struct pmc_bit_map tgl_lpm4_map[] = {
{} {}
}; };
static const struct pmc_bit_map tgl_lpm5_map[] = { static const struct pmc_bit_map tgl_signal_status_map[] = {
{"LSX_Wake0_En_STS", BIT(0)}, {"LSX_Wake0_En_STS", BIT(0)},
{"LSX_Wake0_Pol_STS", BIT(1)}, {"LSX_Wake0_Pol_STS", BIT(1)},
{"LSX_Wake1_En_STS", BIT(2)}, {"LSX_Wake1_En_STS", BIT(2)},
@ -546,18 +557,19 @@ static const struct pmc_bit_map tgl_lpm5_map[] = {
}; };
static const struct pmc_bit_map *tgl_lpm_maps[] = { static const struct pmc_bit_map *tgl_lpm_maps[] = {
tgl_lpm0_map, tgl_clocksource_status_map,
tgl_lpm1_map, tgl_power_gating_status_map,
tgl_lpm2_map, tgl_d3_status_map,
tgl_lpm3_map, tgl_vnn_req_status_map,
tgl_lpm4_map, tgl_vnn_misc_status_map,
tgl_lpm5_map, tgl_signal_status_map,
NULL NULL
}; };
static const struct pmc_reg_map tgl_reg_map = { static const struct pmc_reg_map tgl_reg_map = {
.pfear_sts = ext_tgl_pfear_map, .pfear_sts = ext_tgl_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_show_sts = cnp_ltr_show_map, .ltr_show_sts = cnp_ltr_show_map,
.msr_sts = msr_map, .msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
@ -586,9 +598,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
writel(val, pmcdev->regbase + reg_offset); writel(val, pmcdev->regbase + reg_offset);
} }
static inline u64 pmc_core_adjust_slp_s0_step(u32 value) static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
{ {
return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP; return (u64)value * pmcdev->map->slp_s0_res_counter_step;
} }
static int pmc_core_dev_state_get(void *data, u64 *val) static int pmc_core_dev_state_get(void *data, u64 *val)
@ -598,7 +610,7 @@ static int pmc_core_dev_state_get(void *data, u64 *val)
u32 value; u32 value;
value = pmc_core_reg_read(pmcdev, map->slp_s0_offset); value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
*val = pmc_core_adjust_slp_s0_step(value); *val = pmc_core_adjust_slp_s0_step(pmcdev, value);
return 0; return 0;
} }
@ -628,7 +640,7 @@ static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev,
offset += 4; offset += 4;
while (map->name) { while (map->name) {
if (dev) if (dev)
dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n", dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
map->name, map->name,
data & map->bit_mask ? "Yes" : "No"); data & map->bit_mask ? "Yes" : "No");
if (s) if (s)
@ -671,7 +683,7 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
for (idx = 0; idx < arr_size; idx++) { for (idx = 0; idx < arr_size; idx++) {
if (dev) if (dev)
dev_dbg(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx, dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
lpm_regs[idx]); lpm_regs[idx]);
if (s) if (s)
seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx, seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx,
@ -679,7 +691,7 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
for (index = 0; maps[idx][index].name && index < len; index++) { for (index = 0; maps[idx][index].name && index < len; index++) {
bit_mask = maps[idx][index].bit_mask; bit_mask = maps[idx][index].bit_mask;
if (dev) if (dev)
dev_dbg(dev, "%-30s %-30d\n", dev_info(dev, "%-30s %-30d\n",
maps[idx][index].name, maps[idx][index].name,
lpm_regs[idx] & bit_mask ? 1 : 0); lpm_regs[idx] & bit_mask ? 1 : 0);
if (s) if (s)
@ -1147,6 +1159,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map), X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map),
{} {}
}; };

5
drivers/platform/x86/intel_pmc_core.h
View File

@ -30,7 +30,7 @@
#define SPT_PMC_MPHY_CORE_STS_1 0x1142 #define SPT_PMC_MPHY_CORE_STS_1 0x1142
#define SPT_PMC_MPHY_COM_STS_0 0x1155 #define SPT_PMC_MPHY_COM_STS_0 0x1155
#define SPT_PMC_MMIO_REG_LEN 0x1000 #define SPT_PMC_MMIO_REG_LEN 0x1000
#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68
#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
#define MTPMC_MASK 0xffff0000 #define MTPMC_MASK 0xffff0000
#define PPFEAR_MAX_NUM_ENTRIES 12 #define PPFEAR_MAX_NUM_ENTRIES 12
@ -185,8 +185,10 @@ enum ppfear_regs {
#define ICL_PPFEAR_NUM_ENTRIES 9 #define ICL_PPFEAR_NUM_ENTRIES 9
#define ICL_NUM_IP_IGN_ALLOWED 20 #define ICL_NUM_IP_IGN_ALLOWED 20
#define ICL_PMC_LTR_WIGIG 0x1BFC #define ICL_PMC_LTR_WIGIG 0x1BFC
#define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64
#define TGL_NUM_IP_IGN_ALLOWED 22 #define TGL_NUM_IP_IGN_ALLOWED 22
#define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A
/* /*
* Tigerlake Power Management Controller register offsets * Tigerlake Power Management Controller register offsets
@ -245,6 +247,7 @@ struct pmc_reg_map {
const struct pmc_bit_map *msr_sts; const struct pmc_bit_map *msr_sts;
const struct pmc_bit_map **lpm_sts; const struct pmc_bit_map **lpm_sts;
const u32 slp_s0_offset; const u32 slp_s0_offset;
const int slp_s0_res_counter_step;
const u32 ltr_ignore_offset; const u32 ltr_ignore_offset;
const int regmap_length; const int regmap_length;
const u32 ppfear0_offset; const u32 ppfear0_offset;

16
drivers/platform/x86/mlx-platform.c
View File

@ -328,15 +328,6 @@ static struct i2c_board_info mlxplat_mlxcpld_psu[] = {
}, },
}; };
static struct i2c_board_info mlxplat_mlxcpld_ng_psu[] = {
{
I2C_BOARD_INFO("24c32", 0x51),
},
{
I2C_BOARD_INFO("24c32", 0x50),
},
};
static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
{ {
I2C_BOARD_INFO("dps460", 0x59), I2C_BOARD_INFO("dps460", 0x59),
@ -770,15 +761,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = {
.label = "psu1", .label = "psu1",
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
.mask = BIT(0), .mask = BIT(0),
.hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[0], .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
}, },
{ {
.label = "psu2", .label = "psu2",
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
.mask = BIT(1), .mask = BIT(1),
.hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[1], .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
}, },
}; };
@ -1950,6 +1939,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
static struct mlxreg_core_platform_data mlxplat_default_fan_data = { static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
.data = mlxplat_mlxcpld_default_fan_data, .data = mlxplat_mlxcpld_default_fan_data,
.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
}; };
/* Watchdog type1: hardware implementation version1 /* Watchdog type1: hardware implementation version1

34
include/linux/platform_data/mlxreg.h
View File

@ -1,34 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
/* /*
* Copyright (c) 2017 Mellanox Technologies. All rights reserved. * Copyright (C) 2017-2020 Mellanox Technologies Ltd.
* Copyright (c) 2017 Vadim Pasternak <vadimp@mellanox.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the names of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef __LINUX_PLATFORM_DATA_MLXREG_H #ifndef __LINUX_PLATFORM_DATA_MLXREG_H
@ -137,6 +109,7 @@ struct mlxreg_core_item {
* @features: supported features of device; * @features: supported features of device;
* @version: implementation version; * @version: implementation version;
* @identity: device identity name; * @identity: device identity name;
* @capability: device capability register;
*/ */
struct mlxreg_core_platform_data { struct mlxreg_core_platform_data {
struct mlxreg_core_data *data; struct mlxreg_core_data *data;
@ -145,6 +118,7 @@ struct mlxreg_core_platform_data {
u32 features; u32 features;
u32 version; u32 version;
char identity[MLXREG_CORE_LABEL_MAX_SIZE]; char identity[MLXREG_CORE_LABEL_MAX_SIZE];
u32 capability;
}; };
/** /**

23
tools/power/x86/intel-speed-select/isst-config.c
View File

@ -15,7 +15,7 @@ struct process_cmd_struct {
int arg; int arg;
}; };
static const char *version_str = "v1.5"; static const char *version_str = "v1.6";
static const int supported_api_ver = 1; static const int supported_api_ver = 1;
static struct isst_if_platform_info isst_platform_info; static struct isst_if_platform_info isst_platform_info;
static char *progname; static char *progname;
@ -545,20 +545,23 @@ static void set_cpu_present_cpu_mask(void)
} }
} }
int get_core_count(int pkg_id, int die_id) int get_max_punit_core_id(int pkg_id, int die_id)
{ {
int cnt = 0; int max_id = 0;
int i;
if (pkg_id < MAX_PACKAGE_COUNT && die_id < MAX_DIE_PER_PACKAGE) { for (i = 0; i < topo_max_cpus; ++i)
int i; {
if (!CPU_ISSET_S(i, present_cpumask_size, present_cpumask))
continue;
for (i = 0; i < sizeof(long long) * 8; ++i) { if (cpu_map[i].pkg_id == pkg_id &&
if (core_mask[pkg_id][die_id] & (1ULL << i)) cpu_map[i].die_id == die_id &&
cnt++; cpu_map[i].punit_cpu_core > max_id)
} max_id = cpu_map[i].punit_cpu_core;
} }
return cnt; return max_id;
} }
int get_cpu_count(int pkg_id, int die_id) int get_cpu_count(int pkg_id, int die_id)

8
tools/power/x86/intel-speed-select/isst-core.c
View File

@ -396,7 +396,7 @@ int isst_get_pbf_info(int cpu, int level, struct isst_pbf_info *pbf_info)
{ {
struct isst_pkg_ctdp_level_info ctdp_level; struct isst_pkg_ctdp_level_info ctdp_level;
struct isst_pkg_ctdp pkg_dev; struct isst_pkg_ctdp pkg_dev;
int i, ret, core_cnt, max; int i, ret, max_punit_core, max_mask_index;
unsigned int req, resp; unsigned int req, resp;
ret = isst_get_ctdp_levels(cpu, &pkg_dev); ret = isst_get_ctdp_levels(cpu, &pkg_dev);
@ -421,10 +421,10 @@ int isst_get_pbf_info(int cpu, int level, struct isst_pbf_info *pbf_info)
pbf_info->core_cpumask_size = alloc_cpu_set(&pbf_info->core_cpumask); pbf_info->core_cpumask_size = alloc_cpu_set(&pbf_info->core_cpumask);
core_cnt = get_core_count(get_physical_package_id(cpu), get_physical_die_id(cpu)); max_punit_core = get_max_punit_core_id(get_physical_package_id(cpu), get_physical_die_id(cpu));
max = core_cnt > 32 ? 2 : 1; max_mask_index = max_punit_core > 32 ? 2 : 1;
for (i = 0; i < max; ++i) { for (i = 0; i < max_mask_index; ++i) {
unsigned long long mask; unsigned long long mask;
int count; int count;

2
tools/power/x86/intel-speed-select/isst.h
View File

@ -170,7 +170,7 @@ struct isst_pkg_ctdp {
extern int get_topo_max_cpus(void); extern int get_topo_max_cpus(void);
extern int get_cpu_count(int pkg_id, int die_id); extern int get_cpu_count(int pkg_id, int die_id);
extern int get_core_count(int pkg_id, int die_id); extern int get_max_punit_core_id(int pkg_id, int die_id);
/* Common interfaces */ /* Common interfaces */
FILE *get_output_file(void); FILE *get_output_file(void);