forked from Minki/linux
serial: pic32_uart: Add PIC32 UART driver
This adds UART and a serial console driver for Microchip PIC32 class devices. [ralf@linux-mips.org: Resolved merge conflict.] Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Reviewed-by: Alan Cox <alan@linux.intel.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-serial@vger.kernel.org Cc: linux-api@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12101/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrei Pistirica
Ralf Baechle
parent
81dfdd39c7
commit
157b939470
@ -900,6 +900,27 @@ config SERIAL_SGI_L1_CONSOLE
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controller serial port as your console (you want this!),
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say Y. Otherwise, say N.
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config SERIAL_PIC32
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tristate "Microchip PIC32 serial support"
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depends on MACH_PIC32
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select SERIAL_CORE
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help
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If you have a PIC32, this driver supports the serial ports.
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Say Y or M to use PIC32 serial ports, otherwise say N. Note that
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to use a serial port as a console, this must be included in kernel and
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not as a module.
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config SERIAL_PIC32_CONSOLE
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bool "PIC32 serial console support"
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depends on SERIAL_PIC32
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select SERIAL_CORE_CONSOLE
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help
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If you have a PIC32, this driver supports the putting a console on one
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of the serial ports.
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Say Y to use the PIC32 console, otherwise say N.
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config SERIAL_MPC52xx
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tristate "Freescale MPC52xx/MPC512x family PSC serial support"
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depends on PPC_MPC52xx || PPC_MPC512x
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@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o
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obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
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obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
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obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o
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obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o
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# GPIOLIB helpers for modem control lines
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obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
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960
drivers/tty/serial/pic32_uart.c
Normal file
960
drivers/tty/serial/pic32_uart.c
Normal file
@ -0,0 +1,960 @@
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/*
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* PIC32 Integrated Serial Driver.
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*
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* Copyright (C) 2015 Microchip Technology, Inc.
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*
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* Authors:
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* Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/console.h>
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#include <linux/clk.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/delay.h>
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#include <asm/mach-pic32/pic32.h>
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#include "pic32_uart.h"
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/* UART name and device definitions */
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#define PIC32_DEV_NAME "pic32-uart"
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#define PIC32_MAX_UARTS 6
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#define PIC32_SDEV_NAME "ttyPIC"
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/* pic32_sport pointer for console use */
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static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
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static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
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{
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/* wait for tx empty, otherwise chars will be lost or corrupted */
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while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
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udelay(1);
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}
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static inline int pic32_enable_clock(struct pic32_sport *sport)
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{
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int ret = clk_prepare_enable(sport->clk);
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if (ret)
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return ret;
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sport->ref_clk++;
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return 0;
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}
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static inline void pic32_disable_clock(struct pic32_sport *sport)
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{
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sport->ref_clk--;
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clk_disable_unprepare(sport->clk);
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}
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/* serial core request to check if uart tx buffer is empty */
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static unsigned int pic32_uart_tx_empty(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
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return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
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}
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/* serial core request to set UART outputs */
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static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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/* set loopback mode */
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if (mctrl & TIOCM_LOOP)
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pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
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PIC32_UART_MODE_LPBK);
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else
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pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
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PIC32_UART_MODE_LPBK);
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}
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/* get the state of CTS input pin for this port */
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static unsigned int get_cts_state(struct pic32_sport *sport)
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{
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/* read and invert UxCTS */
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if (gpio_is_valid(sport->cts_gpio))
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return !gpio_get_value(sport->cts_gpio);
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return 1;
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}
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/* serial core request to return the state of misc UART input pins */
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static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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unsigned int mctrl = 0;
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if (!sport->hw_flow_ctrl)
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mctrl |= TIOCM_CTS;
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else if (get_cts_state(sport))
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mctrl |= TIOCM_CTS;
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/* DSR and CD are not supported in PIC32, so return 1
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* RI is not supported in PIC32, so return 0
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*/
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mctrl |= TIOCM_CD;
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mctrl |= TIOCM_DSR;
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return mctrl;
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}
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/* stop tx and start tx are not called in pairs, therefore a flag indicates
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* the status of irq to control the irq-depth.
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*/
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static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
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{
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if (en && !tx_irq_enabled(sport)) {
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enable_irq(sport->irq_tx);
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tx_irq_enabled(sport) = 1;
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} else if (!en && tx_irq_enabled(sport)) {
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/* use disable_irq_nosync() and not disable_irq() to avoid self
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* imposed deadlock by not waiting for irq handler to end,
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* since this callback is called from interrupt context.
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*/
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disable_irq_nosync(sport->irq_tx);
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tx_irq_enabled(sport) = 0;
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}
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}
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/* serial core request to disable tx ASAP (used for flow control) */
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static void pic32_uart_stop_tx(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
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return;
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if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
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return;
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/* wait for tx empty */
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pic32_wait_deplete_txbuf(sport);
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pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
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PIC32_UART_STA_UTXEN);
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pic32_uart_irqtxen(sport, 0);
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}
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/* serial core request to (re)enable tx */
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static void pic32_uart_start_tx(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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pic32_uart_irqtxen(sport, 1);
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pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
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PIC32_UART_STA_UTXEN);
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}
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/* serial core request to stop rx, called before port shutdown */
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static void pic32_uart_stop_rx(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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/* disable rx interrupts */
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disable_irq(sport->irq_rx);
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/* receiver Enable bit OFF */
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pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
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PIC32_UART_STA_URXEN);
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}
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/* serial core request to start/stop emitting break char */
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static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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if (ctl)
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pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
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PIC32_UART_STA_UTXBRK);
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else
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pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
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PIC32_UART_STA_UTXBRK);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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/* get port type in string format */
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static const char *pic32_uart_type(struct uart_port *port)
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{
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return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
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}
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/* read all chars in rx fifo and send them to core */
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static void pic32_uart_do_rx(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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struct tty_port *tty;
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unsigned int max_count;
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/* limit number of char read in interrupt, should not be
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* higher than fifo size anyway since we're much faster than
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* serial port
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*/
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max_count = PIC32_UART_RX_FIFO_DEPTH;
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spin_lock(&port->lock);
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tty = &port->state->port;
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do {
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u32 sta_reg, c;
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char flag;
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/* get overrun/fifo empty information from status register */
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sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
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if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
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/* fifo reset is required to clear interrupt */
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pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
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PIC32_UART_STA_OERR);
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port->icount.overrun++;
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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}
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/* Can at least one more character can be read? */
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if (!(sta_reg & PIC32_UART_STA_URXDA))
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break;
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/* read the character and increment the rx counter */
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c = pic32_uart_readl(sport, PIC32_UART_RX);
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port->icount.rx++;
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flag = TTY_NORMAL;
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c &= 0xff;
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if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
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(sta_reg & PIC32_UART_STA_FERR))) {
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/* do stats first */
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if (sta_reg & PIC32_UART_STA_PERR)
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port->icount.parity++;
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if (sta_reg & PIC32_UART_STA_FERR)
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port->icount.frame++;
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/* update flag wrt read_status_mask */
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sta_reg &= port->read_status_mask;
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if (sta_reg & PIC32_UART_STA_FERR)
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flag = TTY_FRAME;
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if (sta_reg & PIC32_UART_STA_PERR)
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flag = TTY_PARITY;
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}
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if (uart_handle_sysrq_char(port, c))
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continue;
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if ((sta_reg & port->ignore_status_mask) == 0)
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tty_insert_flip_char(tty, c, flag);
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} while (--max_count);
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spin_unlock(&port->lock);
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tty_flip_buffer_push(tty);
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}
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/* fill tx fifo with chars to send, stop when fifo is about to be full
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* or when all chars have been sent.
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*/
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static void pic32_uart_do_tx(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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struct circ_buf *xmit = &port->state->xmit;
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unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
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if (port->x_char) {
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pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
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port->icount.tx++;
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port->x_char = 0;
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return;
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}
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if (uart_tx_stopped(port)) {
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pic32_uart_stop_tx(port);
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return;
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}
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if (uart_circ_empty(xmit))
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goto txq_empty;
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/* keep stuffing chars into uart tx buffer
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* 1) until uart fifo is full
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* or
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* 2) until the circ buffer is empty
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* (all chars have been sent)
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* or
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* 3) until the max count is reached
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* (prevents lingering here for too long in certain cases)
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*/
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while (!(PIC32_UART_STA_UTXBF &
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pic32_uart_readl(sport, PIC32_UART_STA))) {
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unsigned int c = xmit->buf[xmit->tail];
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pic32_uart_writel(sport, PIC32_UART_TX, c);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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if (--max_count == 0)
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break;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit))
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goto txq_empty;
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return;
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txq_empty:
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pic32_uart_irqtxen(sport, 0);
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}
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/* RX interrupt handler */
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static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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pic32_uart_do_rx(port);
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return IRQ_HANDLED;
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}
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/* TX interrupt handler */
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static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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pic32_uart_do_tx(port);
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spin_unlock_irqrestore(&port->lock, flags);
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return IRQ_HANDLED;
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}
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/* FAULT interrupt handler */
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static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
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{
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/* do nothing: pic32_uart_do_rx() handles faults. */
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return IRQ_HANDLED;
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}
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/* enable rx & tx operation on uart */
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static void pic32_uart_en_and_unmask(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
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PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
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pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
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PIC32_UART_MODE_ON);
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}
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/* disable rx & tx operation on uart */
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static void pic32_uart_dsbl_and_mask(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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/* wait for tx empty, otherwise chars will be lost or corrupted */
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pic32_wait_deplete_txbuf(sport);
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pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
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PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
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pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
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PIC32_UART_MODE_ON);
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}
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/* serial core request to initialize uart and start rx operation */
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static int pic32_uart_startup(struct uart_port *port)
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{
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struct pic32_sport *sport = to_pic32_sport(port);
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u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
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unsigned long flags;
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int ret;
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local_irq_save(flags);
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ret = pic32_enable_clock(sport);
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if (ret) {
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local_irq_restore(flags);
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goto out_done;
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}
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/* clear status and mode registers */
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pic32_uart_writel(sport, PIC32_UART_MODE, 0);
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pic32_uart_writel(sport, PIC32_UART_STA, 0);
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/* disable uart and mask all interrupts */
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pic32_uart_dsbl_and_mask(port);
|
||||
|
||||
/* set default baud */
|
||||
pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
/* Each UART of a PIC32 has three interrupts therefore,
|
||||
* we setup driver to register the 3 irqs for the device.
|
||||
*
|
||||
* For each irq request_irq() is called with interrupt disabled.
|
||||
* And the irq is enabled as soon as we are ready to handle them.
|
||||
*/
|
||||
tx_irq_enabled(sport) = 0;
|
||||
|
||||
sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
|
||||
pic32_uart_type(port),
|
||||
sport->idx);
|
||||
if (!sport->irq_fault_name) {
|
||||
dev_err(port->dev, "%s: kasprintf err!", __func__);
|
||||
ret = -ENOMEM;
|
||||
goto out_done;
|
||||
}
|
||||
irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
|
||||
ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
|
||||
sport->irqflags_fault, sport->irq_fault_name, port);
|
||||
if (ret) {
|
||||
dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
|
||||
__func__, sport->irq_fault, ret,
|
||||
pic32_uart_type(port));
|
||||
goto out_f;
|
||||
}
|
||||
|
||||
sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
|
||||
pic32_uart_type(port),
|
||||
sport->idx);
|
||||
if (!sport->irq_rx_name) {
|
||||
dev_err(port->dev, "%s: kasprintf err!", __func__);
|
||||
kfree(sport->irq_fault_name);
|
||||
ret = -ENOMEM;
|
||||
goto out_f;
|
||||
}
|
||||
irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
|
||||
ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
|
||||
sport->irqflags_rx, sport->irq_rx_name, port);
|
||||
if (ret) {
|
||||
dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
|
||||
__func__, sport->irq_rx, ret,
|
||||
pic32_uart_type(port));
|
||||
goto out_r;
|
||||
}
|
||||
|
||||
sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
|
||||
pic32_uart_type(port),
|
||||
sport->idx);
|
||||
if (!sport->irq_tx_name) {
|
||||
dev_err(port->dev, "%s: kasprintf err!", __func__);
|
||||
ret = -ENOMEM;
|
||||
goto out_r;
|
||||
}
|
||||
irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
|
||||
ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
|
||||
sport->irqflags_tx, sport->irq_tx_name, port);
|
||||
if (ret) {
|
||||
dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
|
||||
__func__, sport->irq_tx, ret,
|
||||
pic32_uart_type(port));
|
||||
goto out_t;
|
||||
}
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/* set rx interrupt on first receive */
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
|
||||
PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
|
||||
|
||||
/* set interrupt on empty */
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
|
||||
PIC32_UART_STA_UTXISEL1);
|
||||
|
||||
/* enable all interrupts and eanable uart */
|
||||
pic32_uart_en_and_unmask(port);
|
||||
|
||||
enable_irq(sport->irq_rx);
|
||||
|
||||
return 0;
|
||||
|
||||
out_t:
|
||||
kfree(sport->irq_tx_name);
|
||||
free_irq(sport->irq_tx, sport);
|
||||
out_r:
|
||||
kfree(sport->irq_rx_name);
|
||||
free_irq(sport->irq_rx, sport);
|
||||
out_f:
|
||||
kfree(sport->irq_fault_name);
|
||||
free_irq(sport->irq_fault, sport);
|
||||
out_done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* serial core request to flush & disable uart */
|
||||
static void pic32_uart_shutdown(struct uart_port *port)
|
||||
{
|
||||
struct pic32_sport *sport = to_pic32_sport(port);
|
||||
unsigned long flags;
|
||||
|
||||
/* disable uart */
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
pic32_uart_dsbl_and_mask(port);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
pic32_disable_clock(sport);
|
||||
|
||||
/* free all 3 interrupts for this UART */
|
||||
free_irq(sport->irq_fault, port);
|
||||
free_irq(sport->irq_tx, port);
|
||||
free_irq(sport->irq_rx, port);
|
||||
}
|
||||
|
||||
/* serial core request to change current uart setting */
|
||||
static void pic32_uart_set_termios(struct uart_port *port,
|
||||
struct ktermios *new,
|
||||
struct ktermios *old)
|
||||
{
|
||||
struct pic32_sport *sport = to_pic32_sport(port);
|
||||
unsigned int baud;
|
||||
unsigned int quot;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* disable uart and mask all interrupts while changing speed */
|
||||
pic32_uart_dsbl_and_mask(port);
|
||||
|
||||
/* stop bit options */
|
||||
if (new->c_cflag & CSTOPB)
|
||||
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_STSEL);
|
||||
else
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_STSEL);
|
||||
|
||||
/* parity options */
|
||||
if (new->c_cflag & PARENB) {
|
||||
if (new->c_cflag & PARODD) {
|
||||
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_PDSEL1);
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_PDSEL0);
|
||||
} else {
|
||||
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_PDSEL0);
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_PDSEL1);
|
||||
}
|
||||
} else {
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_PDSEL1 |
|
||||
PIC32_UART_MODE_PDSEL0);
|
||||
}
|
||||
/* if hw flow ctrl, then the pins must be specified in device tree */
|
||||
if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) {
|
||||
/* enable hardware flow control */
|
||||
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_UEN1);
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_UEN0);
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_RTSMD);
|
||||
} else {
|
||||
/* disable hardware flow control */
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_UEN1);
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_UEN0);
|
||||
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
|
||||
PIC32_UART_MODE_RTSMD);
|
||||
}
|
||||
|
||||
/* Always 8-bit */
|
||||
new->c_cflag |= CS8;
|
||||
|
||||
/* Mark/Space parity is not supported */
|
||||
new->c_cflag &= ~CMSPAR;
|
||||
|
||||
/* update baud */
|
||||
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
|
||||
quot = uart_get_divisor(port, baud) - 1;
|
||||
pic32_uart_writel(sport, PIC32_UART_BRG, quot);
|
||||
uart_update_timeout(port, new->c_cflag, baud);
|
||||
|
||||
if (tty_termios_baud_rate(new))
|
||||
tty_termios_encode_baud_rate(new, baud, baud);
|
||||
|
||||
/* enable uart */
|
||||
pic32_uart_en_and_unmask(port);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
/* serial core request to claim uart iomem */
|
||||
static int pic32_uart_request_port(struct uart_port *port)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(port->dev);
|
||||
struct resource *res_mem;
|
||||
|
||||
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (unlikely(!res_mem))
|
||||
return -EINVAL;
|
||||
|
||||
if (!request_mem_region(port->mapbase, resource_size(res_mem),
|
||||
"pic32_uart_mem"))
|
||||
return -EBUSY;
|
||||
|
||||
port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
|
||||
resource_size(res_mem));
|
||||
if (!port->membase) {
|
||||
dev_err(port->dev, "Unable to map registers\n");
|
||||
release_mem_region(port->mapbase, resource_size(res_mem));
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* serial core request to release uart iomem */
|
||||
static void pic32_uart_release_port(struct uart_port *port)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(port->dev);
|
||||
struct resource *res_mem;
|
||||
unsigned int res_size;
|
||||
|
||||
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (unlikely(!res_mem))
|
||||
return;
|
||||
res_size = resource_size(res_mem);
|
||||
|
||||
release_mem_region(port->mapbase, res_size);
|
||||
}
|
||||
|
||||
/* serial core request to do any port required auto-configuration */
|
||||
static void pic32_uart_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
if (flags & UART_CONFIG_TYPE) {
|
||||
if (pic32_uart_request_port(port))
|
||||
return;
|
||||
port->type = PORT_PIC32;
|
||||
}
|
||||
}
|
||||
|
||||
/* serial core request to check that port information in serinfo are suitable */
|
||||
static int pic32_uart_verify_port(struct uart_port *port,
|
||||
struct serial_struct *serinfo)
|
||||
{
|
||||
if (port->type != PORT_PIC32)
|
||||
return -EINVAL;
|
||||
if (port->irq != serinfo->irq)
|
||||
return -EINVAL;
|
||||
if (port->iotype != serinfo->io_type)
|
||||
return -EINVAL;
|
||||
if (port->mapbase != (unsigned long)serinfo->iomem_base)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* serial core callbacks */
|
||||
static const struct uart_ops pic32_uart_ops = {
|
||||
.tx_empty = pic32_uart_tx_empty,
|
||||
.get_mctrl = pic32_uart_get_mctrl,
|
||||
.set_mctrl = pic32_uart_set_mctrl,
|
||||
.start_tx = pic32_uart_start_tx,
|
||||
.stop_tx = pic32_uart_stop_tx,
|
||||
.stop_rx = pic32_uart_stop_rx,
|
||||
.break_ctl = pic32_uart_break_ctl,
|
||||
.startup = pic32_uart_startup,
|
||||
.shutdown = pic32_uart_shutdown,
|
||||
.set_termios = pic32_uart_set_termios,
|
||||
.type = pic32_uart_type,
|
||||
.release_port = pic32_uart_release_port,
|
||||
.request_port = pic32_uart_request_port,
|
||||
.config_port = pic32_uart_config_port,
|
||||
.verify_port = pic32_uart_verify_port,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SERIAL_PIC32_CONSOLE
|
||||
/* output given char */
|
||||
static void pic32_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
struct pic32_sport *sport = to_pic32_sport(port);
|
||||
|
||||
if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
|
||||
return;
|
||||
|
||||
if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
|
||||
return;
|
||||
|
||||
/* wait for tx empty */
|
||||
pic32_wait_deplete_txbuf(sport);
|
||||
|
||||
pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
|
||||
}
|
||||
|
||||
/* console core request to output given string */
|
||||
static void pic32_console_write(struct console *co, const char *s,
|
||||
unsigned int count)
|
||||
{
|
||||
struct pic32_sport *sport = pic32_sports[co->index];
|
||||
struct uart_port *port = pic32_get_port(sport);
|
||||
|
||||
/* call uart helper to deal with \r\n */
|
||||
uart_console_write(port, s, count, pic32_console_putchar);
|
||||
}
|
||||
|
||||
/* console core request to setup given console, find matching uart
|
||||
* port and setup it.
|
||||
*/
|
||||
static int pic32_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct pic32_sport *sport;
|
||||
struct uart_port *port = NULL;
|
||||
int baud = 115200;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
int ret = 0;
|
||||
|
||||
if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
|
||||
return -ENODEV;
|
||||
|
||||
sport = pic32_sports[co->index];
|
||||
if (!sport)
|
||||
return -ENODEV;
|
||||
port = pic32_get_port(sport);
|
||||
|
||||
ret = pic32_enable_clock(sport);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
||||
return uart_set_options(port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct uart_driver pic32_uart_driver;
|
||||
static struct console pic32_console = {
|
||||
.name = PIC32_SDEV_NAME,
|
||||
.write = pic32_console_write,
|
||||
.device = uart_console_device,
|
||||
.setup = pic32_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &pic32_uart_driver,
|
||||
};
|
||||
#define PIC32_SCONSOLE (&pic32_console)
|
||||
|
||||
static int __init pic32_console_init(void)
|
||||
{
|
||||
register_console(&pic32_console);
|
||||
return 0;
|
||||
}
|
||||
console_initcall(pic32_console_init);
|
||||
|
||||
static inline bool is_pic32_console_port(struct uart_port *port)
|
||||
{
|
||||
return port->cons && port->cons->index == port->line;
|
||||
}
|
||||
|
||||
/*
|
||||
* Late console initialization.
|
||||
*/
|
||||
static int __init pic32_late_console_init(void)
|
||||
{
|
||||
if (!(pic32_console.flags & CON_ENABLED))
|
||||
register_console(&pic32_console);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
core_initcall(pic32_late_console_init);
|
||||
|
||||
#else
|
||||
#define PIC32_SCONSOLE NULL
|
||||
#endif
|
||||
|
||||
static struct uart_driver pic32_uart_driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = PIC32_DEV_NAME,
|
||||
.dev_name = PIC32_SDEV_NAME,
|
||||
.nr = PIC32_MAX_UARTS,
|
||||
.cons = PIC32_SCONSOLE,
|
||||
};
|
||||
|
||||
static int pic32_uart_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct pic32_sport *sport;
|
||||
int uart_idx = 0;
|
||||
struct resource *res_mem;
|
||||
struct uart_port *port;
|
||||
int ret;
|
||||
|
||||
uart_idx = of_alias_get_id(np, "serial");
|
||||
if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
|
||||
return -EINVAL;
|
||||
|
||||
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res_mem)
|
||||
return -EINVAL;
|
||||
|
||||
sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
|
||||
if (!sport)
|
||||
return -ENOMEM;
|
||||
|
||||
sport->idx = uart_idx;
|
||||
sport->irq_fault = irq_of_parse_and_map(np, 0);
|
||||
sport->irqflags_fault = IRQF_NO_THREAD;
|
||||
sport->irq_rx = irq_of_parse_and_map(np, 1);
|
||||
sport->irqflags_rx = IRQF_NO_THREAD;
|
||||
sport->irq_tx = irq_of_parse_and_map(np, 2);
|
||||
sport->irqflags_tx = IRQF_NO_THREAD;
|
||||
sport->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
sport->cts_gpio = -EINVAL;
|
||||
sport->dev = &pdev->dev;
|
||||
|
||||
/* Hardware flow control: gpios
|
||||
* !Note: Basically, CTS is needed for reading the status.
|
||||
*/
|
||||
sport->hw_flow_ctrl = false;
|
||||
sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0);
|
||||
if (gpio_is_valid(sport->cts_gpio)) {
|
||||
sport->hw_flow_ctrl = true;
|
||||
|
||||
ret = devm_gpio_request(sport->dev,
|
||||
sport->cts_gpio, "CTS");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"error requesting CTS GPIO\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = gpio_direction_input(sport->cts_gpio);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "error setting CTS GPIO\n");
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
pic32_sports[uart_idx] = sport;
|
||||
port = &sport->port;
|
||||
memset(port, 0, sizeof(*port));
|
||||
port->iotype = UPIO_MEM;
|
||||
port->mapbase = res_mem->start;
|
||||
port->ops = &pic32_uart_ops;
|
||||
port->flags = UPF_BOOT_AUTOCONF;
|
||||
port->dev = &pdev->dev;
|
||||
port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
|
||||
port->uartclk = clk_get_rate(sport->clk);
|
||||
port->line = uart_idx;
|
||||
|
||||
ret = uart_add_one_port(&pic32_uart_driver, port);
|
||||
if (ret) {
|
||||
port->membase = NULL;
|
||||
dev_err(port->dev, "%s: uart add port error!\n", __func__);
|
||||
goto err;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIAL_PIC32_CONSOLE
|
||||
if (is_pic32_console_port(port) &&
|
||||
(pic32_console.flags & CON_ENABLED)) {
|
||||
/* The peripheral clock has been enabled by console_setup,
|
||||
* so disable it till the port is used.
|
||||
*/
|
||||
pic32_disable_clock(sport);
|
||||
}
|
||||
#endif
|
||||
|
||||
platform_set_drvdata(pdev, port);
|
||||
|
||||
dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
|
||||
__func__, uart_idx);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
/* automatic unroll of sport and gpios */
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pic32_uart_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uart_port *port = platform_get_drvdata(pdev);
|
||||
struct pic32_sport *sport = to_pic32_sport(port);
|
||||
|
||||
uart_remove_one_port(&pic32_uart_driver, port);
|
||||
pic32_disable_clock(sport);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
pic32_sports[sport->idx] = NULL;
|
||||
|
||||
/* automatic unroll of sport and gpios */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id pic32_serial_dt_ids[] = {
|
||||
{ .compatible = "microchip,pic32mzda-uart" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
|
||||
|
||||
static struct platform_driver pic32_uart_platform_driver = {
|
||||
.probe = pic32_uart_probe,
|
||||
.remove = pic32_uart_remove,
|
||||
.driver = {
|
||||
.name = PIC32_DEV_NAME,
|
||||
.of_match_table = of_match_ptr(pic32_serial_dt_ids),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init pic32_uart_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = uart_register_driver(&pic32_uart_driver);
|
||||
if (ret) {
|
||||
pr_err("failed to register %s:%d\n",
|
||||
pic32_uart_driver.driver_name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = platform_driver_register(&pic32_uart_platform_driver);
|
||||
if (ret) {
|
||||
pr_err("fail to register pic32 uart\n");
|
||||
uart_unregister_driver(&pic32_uart_driver);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
arch_initcall(pic32_uart_init);
|
||||
|
||||
static void __exit pic32_uart_exit(void)
|
||||
{
|
||||
#ifdef CONFIG_SERIAL_PIC32_CONSOLE
|
||||
unregister_console(&pic32_console);
|
||||
#endif
|
||||
platform_driver_unregister(&pic32_uart_platform_driver);
|
||||
uart_unregister_driver(&pic32_uart_driver);
|
||||
}
|
||||
module_exit(pic32_uart_exit);
|
||||
|
||||
MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
|
||||
MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
126
drivers/tty/serial/pic32_uart.h
Normal file
126
drivers/tty/serial/pic32_uart.h
Normal file
@ -0,0 +1,126 @@
|
||||
/*
|
||||
* PIC32 Integrated Serial Driver.
|
||||
*
|
||||
* Copyright (C) 2015 Microchip Technology, Inc.
|
||||
*
|
||||
* Authors:
|
||||
* Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
#ifndef __DT_PIC32_UART_H__
|
||||
#define __DT_PIC32_UART_H__
|
||||
|
||||
#define PIC32_UART_DFLT_BRATE (9600)
|
||||
#define PIC32_UART_TX_FIFO_DEPTH (8)
|
||||
#define PIC32_UART_RX_FIFO_DEPTH (8)
|
||||
|
||||
#define PIC32_UART_MODE 0x00
|
||||
#define PIC32_UART_STA 0x10
|
||||
#define PIC32_UART_TX 0x20
|
||||
#define PIC32_UART_RX 0x30
|
||||
#define PIC32_UART_BRG 0x40
|
||||
|
||||
struct pic32_console_opt {
|
||||
int baud;
|
||||
int parity;
|
||||
int bits;
|
||||
int flow;
|
||||
};
|
||||
|
||||
/* struct pic32_sport - pic32 serial port descriptor
|
||||
* @port: uart port descriptor
|
||||
* @idx: port index
|
||||
* @irq_fault: virtual fault interrupt number
|
||||
* @irqflags_fault: flags related to fault irq
|
||||
* @irq_fault_name: irq fault name
|
||||
* @irq_rx: virtual rx interrupt number
|
||||
* @irqflags_rx: flags related to rx irq
|
||||
* @irq_rx_name: irq rx name
|
||||
* @irq_tx: virtual tx interrupt number
|
||||
* @irqflags_tx: : flags related to tx irq
|
||||
* @irq_tx_name: irq tx name
|
||||
* @cts_gpio: clear to send gpio
|
||||
* @dev: device descriptor
|
||||
**/
|
||||
struct pic32_sport {
|
||||
struct uart_port port;
|
||||
struct pic32_console_opt opt;
|
||||
int idx;
|
||||
|
||||
int irq_fault;
|
||||
int irqflags_fault;
|
||||
const char *irq_fault_name;
|
||||
int irq_rx;
|
||||
int irqflags_rx;
|
||||
const char *irq_rx_name;
|
||||
int irq_tx;
|
||||
int irqflags_tx;
|
||||
const char *irq_tx_name;
|
||||
u8 enable_tx_irq;
|
||||
|
||||
bool hw_flow_ctrl;
|
||||
int cts_gpio;
|
||||
|
||||
int ref_clk;
|
||||
struct clk *clk;
|
||||
|
||||
struct device *dev;
|
||||
};
|
||||
#define to_pic32_sport(c) container_of(c, struct pic32_sport, port)
|
||||
#define pic32_get_port(sport) (&sport->port)
|
||||
#define pic32_get_opt(sport) (&sport->opt)
|
||||
#define tx_irq_enabled(sport) (sport->enable_tx_irq)
|
||||
|
||||
static inline void pic32_uart_writel(struct pic32_sport *sport,
|
||||
u32 reg, u32 val)
|
||||
{
|
||||
struct uart_port *port = pic32_get_port(sport);
|
||||
|
||||
__raw_writel(val, port->membase + reg);
|
||||
}
|
||||
|
||||
static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
|
||||
{
|
||||
struct uart_port *port = pic32_get_port(sport);
|
||||
|
||||
return __raw_readl(port->membase + reg);
|
||||
}
|
||||
|
||||
/* pic32 uart mode register bits */
|
||||
#define PIC32_UART_MODE_ON BIT(15)
|
||||
#define PIC32_UART_MODE_FRZ BIT(14)
|
||||
#define PIC32_UART_MODE_SIDL BIT(13)
|
||||
#define PIC32_UART_MODE_IREN BIT(12)
|
||||
#define PIC32_UART_MODE_RTSMD BIT(11)
|
||||
#define PIC32_UART_MODE_RESV1 BIT(10)
|
||||
#define PIC32_UART_MODE_UEN1 BIT(9)
|
||||
#define PIC32_UART_MODE_UEN0 BIT(8)
|
||||
#define PIC32_UART_MODE_WAKE BIT(7)
|
||||
#define PIC32_UART_MODE_LPBK BIT(6)
|
||||
#define PIC32_UART_MODE_ABAUD BIT(5)
|
||||
#define PIC32_UART_MODE_RXINV BIT(4)
|
||||
#define PIC32_UART_MODE_BRGH BIT(3)
|
||||
#define PIC32_UART_MODE_PDSEL1 BIT(2)
|
||||
#define PIC32_UART_MODE_PDSEL0 BIT(1)
|
||||
#define PIC32_UART_MODE_STSEL BIT(0)
|
||||
|
||||
/* pic32 uart status register bits */
|
||||
#define PIC32_UART_STA_UTXISEL1 BIT(15)
|
||||
#define PIC32_UART_STA_UTXISEL0 BIT(14)
|
||||
#define PIC32_UART_STA_UTXINV BIT(13)
|
||||
#define PIC32_UART_STA_URXEN BIT(12)
|
||||
#define PIC32_UART_STA_UTXBRK BIT(11)
|
||||
#define PIC32_UART_STA_UTXEN BIT(10)
|
||||
#define PIC32_UART_STA_UTXBF BIT(9)
|
||||
#define PIC32_UART_STA_TRMT BIT(8)
|
||||
#define PIC32_UART_STA_URXISEL1 BIT(7)
|
||||
#define PIC32_UART_STA_URXISEL0 BIT(6)
|
||||
#define PIC32_UART_STA_ADDEN BIT(5)
|
||||
#define PIC32_UART_STA_RIDLE BIT(4)
|
||||
#define PIC32_UART_STA_PERR BIT(3)
|
||||
#define PIC32_UART_STA_FERR BIT(2)
|
||||
#define PIC32_UART_STA_OERR BIT(1)
|
||||
#define PIC32_UART_STA_URXDA BIT(0)
|
||||
|
||||
#endif /* __DT_PIC32_UART_H__ */
|
||||
@ -264,4 +264,7 @@
|
||||
/* MVEBU UART */
|
||||
#define PORT_MVEBU 114
|
||||
|
||||
/* Microchip PIC32 UART */
|
||||
#define PORT_PIC32 114
|
||||
|
||||
#endif /* _UAPILINUX_SERIAL_CORE_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user