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pciehp: use pci_pcie_cap()

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Use pci_pcie_cap() instead of pci_find_capability() to get PCIe capability
offset in pciehp driver. This avoids unnecessary search in PCI
configuration space. This patch also removes 'cap_base' field in
struct controller, that was used to hold PCIe capability offset by
pciehp itself.

Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Kenji Kaneshige 2009-11-11 14:34:52 +09:00 committed by Jesse Barnes
parent d3ccc4091f
commit 1518c17ab7
3 changed files with 25 additions and 25 deletions
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1
drivers/pci/hotplug/pciehp.h
View File

@ -91,7 +91,6 @@ struct controller {
struct slot *slot; struct slot *slot;
wait_queue_head_t queue; /* sleep & wake process */ wait_queue_head_t queue; /* sleep & wake process */
u32 slot_cap; u32 slot_cap;
u8 cap_base;
struct timer_list poll_timer; struct timer_list poll_timer;
unsigned int cmd_busy:1; unsigned int cmd_busy:1;
unsigned int no_cmd_complete:1; unsigned int no_cmd_complete:1;

3
drivers/pci/hotplug/pciehp_acpi.c
View File

@ -87,7 +87,8 @@ static int __init dummy_probe(struct pcie_device *dev)
/* Note: pciehp_detect_mode != PCIEHP_DETECT_ACPI here */ /* Note: pciehp_detect_mode != PCIEHP_DETECT_ACPI here */
if (pciehp_get_hp_hw_control_from_firmware(pdev)) if (pciehp_get_hp_hw_control_from_firmware(pdev))
return -ENODEV; return -ENODEV;
if (!(pos = pci_find_capability(pdev, PCI_CAP_ID_EXP))) pos = pci_pcie_cap(pdev);
if (!pos)
return -ENODEV; return -ENODEV;
pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &slot_cap); pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &slot_cap);
slot = kzalloc(sizeof(*slot), GFP_KERNEL); slot = kzalloc(sizeof(*slot), GFP_KERNEL);

46
drivers/pci/hotplug/pciehp_hpc.c
View File

@ -45,25 +45,25 @@ static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
{ {
struct pci_dev *dev = ctrl->pcie->port; struct pci_dev *dev = ctrl->pcie->port;
return pci_read_config_word(dev, ctrl->cap_base + reg, value); return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
} }
static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
{ {
struct pci_dev *dev = ctrl->pcie->port; struct pci_dev *dev = ctrl->pcie->port;
return pci_read_config_dword(dev, ctrl->cap_base + reg, value); return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
} }
static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
{ {
struct pci_dev *dev = ctrl->pcie->port; struct pci_dev *dev = ctrl->pcie->port;
return pci_write_config_word(dev, ctrl->cap_base + reg, value); return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
} }
static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
{ {
struct pci_dev *dev = ctrl->pcie->port; struct pci_dev *dev = ctrl->pcie->port;
return pci_write_config_dword(dev, ctrl->cap_base + reg, value); return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
} }
/* Power Control Command */ /* Power Control Command */
@ -318,8 +318,8 @@ int pciehp_get_attention_status(struct slot *slot, u8 *status)
return retval; return retval;
} }
ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
@ -356,8 +356,8 @@ int pciehp_get_power_status(struct slot *slot, u8 *status)
ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
return retval; return retval;
} }
ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
@ -442,8 +442,8 @@ int pciehp_set_attention_status(struct slot *slot, u8 value)
default: default:
return -EINVAL; return -EINVAL;
} }
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
} }
@ -456,8 +456,8 @@ void pciehp_green_led_on(struct slot *slot)
slot_cmd = 0x0100; slot_cmd = 0x0100;
cmd_mask = PCI_EXP_SLTCTL_PIC; cmd_mask = PCI_EXP_SLTCTL_PIC;
pcie_write_cmd(ctrl, slot_cmd, cmd_mask); pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
} }
void pciehp_green_led_off(struct slot *slot) void pciehp_green_led_off(struct slot *slot)
@ -469,8 +469,8 @@ void pciehp_green_led_off(struct slot *slot)
slot_cmd = 0x0300; slot_cmd = 0x0300;
cmd_mask = PCI_EXP_SLTCTL_PIC; cmd_mask = PCI_EXP_SLTCTL_PIC;
pcie_write_cmd(ctrl, slot_cmd, cmd_mask); pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
} }
void pciehp_green_led_blink(struct slot *slot) void pciehp_green_led_blink(struct slot *slot)
@ -482,8 +482,8 @@ void pciehp_green_led_blink(struct slot *slot)
slot_cmd = 0x0200; slot_cmd = 0x0200;
cmd_mask = PCI_EXP_SLTCTL_PIC; cmd_mask = PCI_EXP_SLTCTL_PIC;
pcie_write_cmd(ctrl, slot_cmd, cmd_mask); pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
} }
int pciehp_power_on_slot(struct slot * slot) int pciehp_power_on_slot(struct slot * slot)
@ -525,8 +525,8 @@ int pciehp_power_on_slot(struct slot * slot)
ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
return retval; return retval;
} }
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
ctrl->power_fault_detected = 0; ctrl->power_fault_detected = 0;
return retval; return retval;
@ -552,8 +552,8 @@ int pciehp_power_off_slot(struct slot * slot)
ctrl_err(ctrl, "Write command failed!\n"); ctrl_err(ctrl, "Write command failed!\n");
return retval; return retval;
} }
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
return 0; return 0;
} }
@ -885,7 +885,8 @@ static inline void dbg_ctrl(struct controller *ctrl)
pdev->subsystem_device); pdev->subsystem_device);
ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
pdev->subsystem_vendor); pdev->subsystem_vendor);
ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base); ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
pci_pcie_cap(pdev));
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
if (!pci_resource_len(pdev, i)) if (!pci_resource_len(pdev, i))
continue; continue;
@ -929,8 +930,7 @@ struct controller *pcie_init(struct pcie_device *dev)
goto abort; goto abort;
} }
ctrl->pcie = dev; ctrl->pcie = dev;
ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); if (!pci_pcie_cap(pdev)) {
if (!ctrl->cap_base) {
ctrl_err(ctrl, "Cannot find PCI Express capability\n"); ctrl_err(ctrl, "Cannot find PCI Express capability\n");
goto abort_ctrl; goto abort_ctrl;
} }