forked from Minki/linux
Merge remote-tracking branches 'spi/fix/bcm63xx', 'spi/fix/dspi', 'spi/fix/hspi', 'spi/fix/imx', 'spi/fix/msiof', 'spi/fix/pxa2xx', 'spi/fix/qspi', 'spi/topic/altera', 'spi/topic/ath79' and 'spi/topic/atmel' into spi-linus
This commit is contained in:
parent
3c1039745e
9637b86fd1
e07725be73
caedb997a4
6fd8b8503a
e4d313ff79
483c319188
e3d8bee385
646d79b2d7
a6f4c8e06b
8090d6d1a4
commit
1504d226f7
@ -220,8 +220,6 @@ static int altera_spi_probe(struct platform_device *pdev)
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/* setup the state for the bitbang driver */
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hw->bitbang.master = master;
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if (!hw->bitbang.master)
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return err;
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hw->bitbang.chipselect = altera_spi_chipsel;
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hw->bitbang.txrx_bufs = altera_spi_txrx;
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@ -243,21 +243,21 @@ static int ath79_spi_probe(struct platform_device *pdev)
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goto err_put_master;
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}
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sp->base = ioremap(r->start, resource_size(r));
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sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!sp->base) {
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ret = -ENXIO;
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goto err_put_master;
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}
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sp->clk = clk_get(&pdev->dev, "ahb");
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sp->clk = devm_clk_get(&pdev->dev, "ahb");
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if (IS_ERR(sp->clk)) {
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ret = PTR_ERR(sp->clk);
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goto err_unmap;
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goto err_put_master;
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}
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ret = clk_enable(sp->clk);
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if (ret)
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goto err_clk_put;
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goto err_put_master;
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rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
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if (!rate) {
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@ -280,10 +280,6 @@ err_disable:
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ath79_spi_disable(sp);
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err_clk_disable:
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clk_disable(sp->clk);
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err_clk_put:
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clk_put(sp->clk);
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err_unmap:
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iounmap(sp->base);
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err_put_master:
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spi_master_put(sp->bitbang.master);
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@ -297,8 +293,6 @@ static int ath79_spi_remove(struct platform_device *pdev)
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spi_bitbang_stop(&sp->bitbang);
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ath79_spi_disable(sp);
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clk_disable(sp->clk);
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clk_put(sp->clk);
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iounmap(sp->base);
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spi_master_put(sp->bitbang.master);
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return 0;
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File diff suppressed because it is too large
Load Diff
@ -169,8 +169,6 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
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transfer_list);
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}
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len -= prepend_len;
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init_completion(&bs->done);
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/* Fill in the Message control register */
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@ -320,8 +320,10 @@ static void dspi_chipselect(struct spi_device *spi, int value)
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switch (value) {
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case BITBANG_CS_ACTIVE:
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pushr |= SPI_PUSHR_CONT;
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break;
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case BITBANG_CS_INACTIVE:
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pushr &= ~SPI_PUSHR_CONT;
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break;
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}
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writel(pushr, dspi->base + SPI_PUSHR);
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@ -206,7 +206,8 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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#define MX51_ECSPI_STAT_RR (1 << 3)
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/* MX51 eCSPI */
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static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
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static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
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unsigned int *fres)
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{
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/*
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* there are two 4-bit dividers, the pre-divider divides by
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@ -234,6 +235,10 @@ static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
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pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
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__func__, fin, fspi, post, pre);
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/* Resulting frequency for the SCLK line. */
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*fres = (fin / (pre + 1)) >> post;
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return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
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(post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
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}
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@ -264,6 +269,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
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u32 clk = config->speed_hz, delay;
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/*
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* The hardware seems to have a race condition when changing modes. The
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@ -275,7 +281,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
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/* set clock speed */
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ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
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ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
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/* set chip select to use */
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ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
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@ -297,6 +303,23 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
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writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
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/*
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* Wait until the changes in the configuration register CONFIGREG
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* propagate into the hardware. It takes exactly one tick of the
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* SCLK clock, but we will wait two SCLK clock just to be sure. The
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* effect of the delay it takes for the hardware to apply changes
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* is noticable if the SCLK clock run very slow. In such a case, if
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* the polarity of SCLK should be inverted, the GPIO ChipSelect might
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* be asserted before the SCLK polarity changes, which would disrupt
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* the SPI communication as the device on the other end would consider
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* the change of SCLK polarity as a clock tick already.
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*/
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delay = (2 * 1000000) / clk;
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if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
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udelay(delay);
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else /* SCLK is _very_ slow */
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usleep_range(delay, delay + 10);
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return 0;
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}
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@ -1066,6 +1066,8 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
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pdata->num_chipselect = 1;
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pdata->enable_dma = true;
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pdata->tx_chan_id = -1;
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pdata->rx_chan_id = -1;
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return pdata;
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}
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@ -353,4 +353,4 @@ module_platform_driver(hspi_driver);
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MODULE_DESCRIPTION("SuperH HSPI bus driver");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
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MODULE_ALIAS("platform:sh_spi");
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MODULE_ALIAS("platform:sh-hspi");
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@ -152,7 +152,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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size_t k;
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if (!WARN_ON(!spi_hz || !parent_rate))
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div = parent_rate / spi_hz;
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div = DIV_ROUND_UP(parent_rate, spi_hz);
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/* TODO: make more fine grained */
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@ -417,10 +417,8 @@ out:
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static int ti_qspi_runtime_resume(struct device *dev)
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{
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struct ti_qspi *qspi;
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struct spi_master *master;
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master = dev_get_drvdata(dev);
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qspi = spi_master_get_devdata(master);
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qspi = dev_get_drvdata(dev);
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ti_qspi_restore_ctx(qspi);
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return 0;
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@ -516,13 +514,9 @@ free_master:
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static int ti_qspi_remove(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct ti_qspi *qspi;
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struct ti_qspi *qspi = platform_get_drvdata(pdev);
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int ret;
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master = platform_get_drvdata(pdev);
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qspi = spi_master_get_devdata(master);
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ret = pm_runtime_get_sync(qspi->dev);
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if (ret < 0) {
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dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
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@ -534,8 +528,6 @@ static int ti_qspi_remove(struct platform_device *pdev)
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pm_runtime_put(qspi->dev);
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pm_runtime_disable(&pdev->dev);
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spi_unregister_master(master);
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return 0;
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}
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