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drm/amd/display: Adjust stream enable sequence

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[Why]
We observed an issue where a display would not accept programming of
the ignore_MSA_timing_param bit if the stream was blanked.

[How]
move enable_stream_features from enable_link_dp to
core_link_enable_stream, after unblank_stream

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joshua Aberback 2018-10-30 15:34:33 -04:00 committed by Alex Deucher
parent 00737c59a2
commit 14fee4ca84
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/drm/amd/display/dc/core/dc_link.c
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@ -1396,8 +1396,6 @@ static enum dc_status enable_link_dp(
else else
status = DC_FAIL_DP_LINK_TRAINING; status = DC_FAIL_DP_LINK_TRAINING;
enable_stream_features(pipe_ctx);
return status; return status;
} }
@ -2594,6 +2592,9 @@ void core_link_enable_stream(
core_dc->hwss.unblank_stream(pipe_ctx, core_dc->hwss.unblank_stream(pipe_ctx,
&pipe_ctx->stream->sink->link->cur_link_settings); &pipe_ctx->stream->sink->link->cur_link_settings);
if (dc_is_dp_signal(pipe_ctx->stream->signal))
enable_stream_features(pipe_ctx);
dc_link_set_backlight_level(pipe_ctx->stream->sink->link, dc_link_set_backlight_level(pipe_ctx->stream->sink->link,
pipe_ctx->stream->bl_pwm_level, pipe_ctx->stream->bl_pwm_level,
0, 0,