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i.MX device tree changes for 3.15:

Browse Source 
- New SoC device tree support for imx35 and imx50
  - A good number of new board support: imx25-eukrea, imx28-duckbill,
    imx28-eukrea, Eukrea cpuimx35, imx50-evk, imx51-eukrea, imx53-voipac,
    MCIMX53-START-R and Ka-Ro TX53.
  - Quite some updates and tweaking on imx27 phycore and apf27dev boards
  - Add pinfunc headers for imx25, imx27 and imx50
  - Make pinctrl nodes board specific to avoid floating board specific
    device tree blob with so many unused pinctrl data
  - Use generic node name for fixed regulator
  - Use clock defines in imx5 DTS files
  - Use macros for interrupt and gpio flags
  - A plenty of random updates on various SoC and board device tree
    sources, adding pinctrl settings, device nodes, properties, aliases.
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Merge tag 'imx-dt-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt

Merge "i.MX device tree changes for 3.15" from Shawn Guo:

 - New SoC device tree support for imx35 and imx50
 - A good number of new board support: imx25-eukrea, imx28-duckbill,
   imx28-eukrea, Eukrea cpuimx35, imx50-evk, imx51-eukrea, imx53-voipac,
   MCIMX53-START-R and Ka-Ro TX53.
 - Quite some updates and tweaking on imx27 phycore and apf27dev boards
 - Add pinfunc headers for imx25, imx27 and imx50
 - Make pinctrl nodes board specific to avoid floating board specific
   device tree blob with so many unused pinctrl data
 - Use generic node name for fixed regulator
 - Use clock defines in imx5 DTS files
 - Use macros for interrupt and gpio flags
 - A plenty of random updates on various SoC and board device tree
   sources, adding pinctrl settings, device nodes, properties, aliases.

* tag 'imx-dt-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (89 commits)
  ARM: dts: imx28-m28cu3: Remove 'reset-active-high'
  ARM: dts: imx5: use imx51-ssi
  ARM: dts: imx51: Add mmc aliases
  ARM: dts: imx53: Add mmc aliases
  ARM: dts: imx53: add support for Ka-Ro TX53 modules
  ARM: dts: Add support for the cpuimx35 board from Eukrea and its baseboard.
  ARM: dts: imx28-apf28dev: add user button
  ARM: dts: i.MX51: Switch to use standard definitions for input subsystem
  ARM: dts: i.MX53: add support for MCIMX53-START-R
  ARM: dts: i.MX53: move common QSB nodes to new file
  ARM: dts: imx53-evk: Remove board support
  ARM: dts: vf610: use the interrupt macros
  ARM: dts: imx53: Add gpio and input dt includes.
  ARM: dts: i.MX27: Add SSI nodes
  ARM: dts: mxs: add mxs phy controller id
  ARM: dts: imx27-phytec-phycore-rdk: Add pinctrl definitions for WEIM
  ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC
  ARM: dts: imx27-phytec-phycore-som: Add spi-cs-high property to PMIC
  ARM: dts: imx27-phytec-phycore-rdk: Enable 1-Wire module
  ARM: dts: imx27-phytec-phycore-som: Add NFC pin group
  ...
This commit is contained in:
Olof Johansson 2014-02-20 00:51:18 -08:00
commit 11dd54384b
66 changed files with 8141 additions and 1763 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -35,6 +35,7 @@ emmicro EM Microelectronic
epfl Ecole Polytechnique Fédérale de Lausanne
epson Seiko Epson Corp.
est ESTeem Wireless Modems
eukrea Eukréa Electromatique
fsl Freescale Semiconductor
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
@ -92,6 +93,7 @@ toshiba Toshiba Corporation
toumaz Toumaz
v3 V3 Semiconductor
via VIA Technologies, Inc.
voipac Voipac Technologies s.r.o.
winbond Winbond Electronics corp.
wlf Wolfson Microelectronics
wm Wondermedia Technologies, Inc.

13
arch/arm/boot/dts/Makefile
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@ -134,25 +134,31 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
armada-xp-matrix.dtb \
armada-xp-openblocks-ax3-4.dtb
dtb-$(CONFIG_ARCH_MXC) += \
imx25-eukrea-mbimxsd25-baseboard.dtb \
imx25-karo-tx25.dtb \
imx25-pdk.dtb \
imx27-apf27.dtb \
imx27-apf27dev.dtb \
imx27-pdk.dtb \
imx27-phytec-phycore-som.dtb \
imx27-phytec-phycore-rdk.dtb \
imx27-phytec-phycard-s-som.dtb \
imx27-phytec-phycard-s-rdk.dtb \
imx31-bug.dtb \
imx35-eukrea-mbimxsd35-baseboard.dtb \
imx50-evk.dtb \
imx51-apf51.dtb \
imx51-apf51dev.dtb \
imx51-babbage.dtb \
imx51-eukrea-mbimxsd51-baseboard.dtb \
imx53-ard.dtb \
imx53-evk.dtb \
imx53-m53evk.dtb \
imx53-mba53.dtb \
imx53-qsb.dtb \
imx53-qsrb.dtb \
imx53-smd.dtb \
imx53-tx53-x03x.dtb \
imx53-tx53-x13x.dtb \
imx53-voipac-bsb.dtb \
imx6dl-cubox-i.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
@ -200,6 +206,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-cfa10056.dtb \
imx28-cfa10057.dtb \
imx28-cfa10058.dtb \
imx28-duckbill.dtb \
imx28-eukrea-mbmx283lc.dtb \
imx28-eukrea-mbmx287lc.dtb \
imx28-evk.dtb \
imx28-m28cu3.dtb \
imx28-m28evk.dtb \

8
arch/arm/boot/dts/imx23-evk.dts
View File

@ -127,17 +127,21 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_vddio_sd0: vddio-sd0 {
reg_vddio_sd0: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 29 0>;
};
reg_lcd_3v3: lcd-3v3 {
reg_lcd_3v3: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

5
arch/arm/boot/dts/imx23-olinuxino.dts
View File

@ -100,9 +100,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb0_vbus: usb0_vbus {
reg_usb0_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

5
arch/arm/boot/dts/imx23-stmp378x_devb.dts
View File

@ -66,9 +66,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_vddio_sd0: vddio-sd0 {
reg_vddio_sd0: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

8
arch/arm/boot/dts/imx23.dtsi
View File

@ -23,6 +23,7 @@
serial1 = &auart1;
spi0 = &ssp0;
spi1 = &ssp1;
usbphy0 = &usbphy0;
};
cpus {
@ -428,7 +429,7 @@
status = "disabled";
};
lradc@80050000 {
lradc: lradc@80050000 {
compatible = "fsl,imx23-lradc";
reg = <0x80050000 0x2000>;
interrupts = <36 37 38 39 40 41 42 43 44>;
@ -526,4 +527,9 @@
status = "disabled";
};
};
iio_hwmon {
compatible = "iio-hwmon";
io-channels = <&lradc 8>;
};
};

73
arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi Normal file
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@ -0,0 +1,73 @@
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "imx25.dtsi"
/ {
model = "Eukrea CPUIMX25";
compatible = "eukrea,cpuimx25", "fsl,imx25";
memory {
reg = <0x80000000 0x4000000>; /* 64M */
};
};
&fec {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&iomuxc {
imx25-eukrea-cpuimx25 {
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
>;
};
};
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};

174
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts Normal file
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@ -0,0 +1,174 @@
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx25-eukrea-cpuimx25.dtsi"
/ {
model = "Eukrea MBIMXSD25";
compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
bp1 {
label = "BP1";
gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
gpio-key,wakeup;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioled>;
led1 {
label = "led1";
gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
sound {
compatible = "eukrea,asoc-tlv320";
eukrea,model = "imx25-eukrea-tlv320aic23";
ssi-controller = <&ssi1>;
fsl,mux-int-port = <1>;
fsl,mux-ext-port = <5>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio1 20>;
status = "okay";
};
&i2c1 {
tlv320aic23: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
};
};
&iomuxc {
imx25-eukrea-mbimxsd25-baseboard {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0
MX25_PAD_KPP_COL2__AUD5_TXC 0xe0
MX25_PAD_KPP_COL1__AUD5_RXD 0xe0
MX25_PAD_KPP_COL0__AUD5_TXD 0xe0
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0
MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0
MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0
MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0
MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0
MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0
>;
};
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
};
pinctrl_gpioled: gpioledgrp {
fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
};
pinctrl_lcdc: lcdcgrp {
fsl,pins = <
MX25_PAD_LD0__LD0 0x1
MX25_PAD_LD1__LD1 0x1
MX25_PAD_LD2__LD2 0x1
MX25_PAD_LD3__LD3 0x1
MX25_PAD_LD4__LD4 0x1
MX25_PAD_LD5__LD5 0x1
MX25_PAD_LD6__LD6 0x1
MX25_PAD_LD7__LD7 0x1
MX25_PAD_LD8__LD8 0x1
MX25_PAD_LD9__LD9 0x1
MX25_PAD_LD10__LD10 0x1
MX25_PAD_LD11__LD11 0x1
MX25_PAD_LD12__LD12 0x1
MX25_PAD_LD13__LD13 0x1
MX25_PAD_LD14__LD14 0x1
MX25_PAD_LD15__LD15 0x1
MX25_PAD_GPIO_E__LD16 0x1
MX25_PAD_GPIO_F__LD17 0x1
MX25_PAD_HSYNC__HSYNC 0x80000000
MX25_PAD_VSYNC__VSYNC 0x80000000
MX25_PAD_LSCLK__LSCLK 0x80000000
MX25_PAD_OE_ACD__OE_ACD 0x80000000
MX25_PAD_CONTRAST__CONTRAST 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_RTS__UART1_RTS 0xe0
MX25_PAD_UART1_CTS__UART1_CTS 0xe0
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
MX25_PAD_UART1_RXD__UART1_RXD 0xc0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX25_PAD_UART2_RXD__UART2_RXD 0x80000000
MX25_PAD_UART2_TXD__UART2_TXD 0x80000000
MX25_PAD_UART2_RTS__UART2_RTS 0x80000000
MX25_PAD_UART2_CTS__UART2_CTS 0x80000000
>;
};
};
};
&ssi1 {
codec-handle = <&tlv320aic23>;
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "okay";
};

494
arch/arm/boot/dts/imx25-pinfunc.h Normal file
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@ -0,0 +1,494 @@
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
* Based on imx35-pinfunc.h in the same directory Which is:
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX25_PINFUNC_H
#define __DTS_IMX25_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x15 0x000
#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x17 0x000
#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x10 0x000
#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x14 0x000
#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x15 0x000
#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x10 0x000
#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x14 0x000
#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x15 0x000
#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x10 0x000
#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x14 0x000
#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x15 0x000
#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000
#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000
#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000
#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000
#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000
#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x10 0x000
#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000
#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000
#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000
#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000
#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000
#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000
#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000
#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000
#define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000
#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000
#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000
#define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000
#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000
#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000
#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x10 0x000
#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x14 0x000
#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x15 0x000
#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x10 0x000
#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x15 0x000
#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x10 0x000
#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x15 0x000
#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x10 0x000
#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x15 0x000
#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x10 0x000
#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x15 0x000
#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x10 0x000
#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x15 0x000
#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x10 0x000
#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x15 0x000
#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000
#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000
#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000
#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000
#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000
#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000
#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000
#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000
#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000
#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000
#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000
#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000
#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000
#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000
#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000
#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000
#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000
#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000
#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000
#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000
#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000
#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000
#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000
#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x10 0x000
#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x12 0x000
#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x15 0x000
#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x10 0x000
#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x12 0x000
#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x15 0x000
#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x10 0x000
#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x15 0x000
#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x10 0x000
#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x15 0x000
#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x10 0x000
#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x15 0x000
#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x10 0x000
#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x15 0x000
#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x10 0x000
#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x15 0x000
#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x10 0x000
#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000
#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001
#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x15 0x000
#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x10 0x000
#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x15 0x000
#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x10 0x000
#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x10 0x000
#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x15 0x000
#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001
#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x15 0x000
#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x10 0x000
#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000
#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000
#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000
#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000
#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001
#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000
#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000
#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000
#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000
#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x13 0x000
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002
#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002
#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
#define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001
#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000
#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000
#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000
#define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000
#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000
#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000
#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000
#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000
#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000
#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000
#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000
#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000
#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x12 0x000
#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x15 0x000
#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x10 0x000
#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x12 0x001
#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x15 0x000
#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x10 0x000
#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x12 0x001
#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x15 0x000
#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x10 0x000
#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x15 0x000
#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x10 0x000
#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x12 0x001
#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x15 0x000
#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x10 0x000
#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x15 0x000
#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x10 0x000
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x10 0x000
#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x15 0x000
#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x10 0x000
#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x11 0x000
#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x15 0x000
#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000
#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000
#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001
#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000
#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000
#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000
#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
#endif /* __DTS_IMX25_PINFUNC_H */

18
arch/arm/boot/dts/imx25.dtsi
View File

@ -10,6 +10,7 @@
*/
#include "skeleton.dtsi"
#include "imx25-pinfunc.h"
/ {
aliases {
@ -173,12 +174,12 @@
status = "disabled";
};
iomuxc@43fac000{
iomuxc: iomuxc@43fac000 {
compatible = "fsl,imx25-iomuxc";
reg = <0x43fac000 0x4000>;
};
audmux@43fb0000 {
audmux: audmux@43fb0000 {
compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
reg = <0x43fb0000 0x4000>;
status = "disabled";
@ -236,6 +237,11 @@
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50014000 0x4000>;
interrupts = <11>;
clocks = <&clks 118>;
clock-names = "ipg";
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -266,6 +272,11 @@
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50034000 0x4000>;
interrupts = <12>;
clocks = <&clks 117>;
clock-names = "ipg";
dmas = <&sdma 28 1 0>,
<&sdma 29 1 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -436,13 +447,14 @@
#interrupt-cells = <2>;
};
sdma@53fd4000 {
sdma: sdma@53fd4000 {
compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
reg = <0x53fd4000 0x4000>;
clocks = <&clks 112>, <&clks 68>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
interrupts = <34>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
};
wdog@53fdc000 {

38
arch/arm/boot/dts/imx27-apf27.dts
View File

@ -34,11 +34,49 @@
};
};
&iomuxc {
imx27-apf27 {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};

149
arch/arm/boot/dts/imx27-apf27dev.dts
View File

@ -22,10 +22,10 @@
bits-per-pixel = <16>; /* non-standard but required */
fsl,pcr = <0xfae80083>; /* non-standard but required */
display-timings {
timing0: 640x480 {
timing0: 800x480 {
clock-frequency = <33000033>;
hactive = <800>;
vactive = <640>;
vactive = <480>;
hback-porch = <96>;
hfront-porch = <96>;
vback-porch = <20>;
@ -38,20 +38,24 @@
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
user-key {
label = "user";
gpios = <&gpio6 13 0>;
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
linux,code = <276>; /* BTN_EXTRA */
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
user {
label = "Heartbeat";
gpios = <&gpio6 14 0>;
gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
@ -59,25 +63,34 @@
&cspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 28 1>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
status = "okay";
};
&cspi2 {
fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>,
<&gpio2 17 1>;
cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>,
<&gpio4 27 GPIO_ACTIVE_LOW>,
<&gpio2 17 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>;
status = "okay";
};
&fb {
display = <&display>;
fsl,dmacr = <0x00020010>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imxfb1>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
rtc@68 {
@ -87,5 +100,127 @@
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&iomuxc {
imx27-apf27dev {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
>;
};
pinctrl_cspi1_cs: cspi1csgrp {
fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
};
pinctrl_cspi2: cspi2grp {
fsl,pins = <
MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
>;
};
pinctrl_cspi2_cs: cspi2csgrp {
fsl,pins = <
MX27_PAD_CSI_D5__GPIO2_17 0x0
MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
};
pinctrl_imxfb1: imxfbgrp {
fsl,pins = <
MX27_PAD_CLS__CLS 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_LSCLK__LSCLK 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_PS__PS 0x0
MX27_PAD_REV__REV 0x0
MX27_PAD_SPL_SPR__SPL_SPR 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_pwm: pwmgrp {
fsl,pins = <
MX27_PAD_PWMO__PWMO 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
>;
};
pinctrl_sdhc2_cd: sdhc2cdgrp {
fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
};
};
};
&sdhci2 {
bus-width = <4>;
cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>;
status = "okay";
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm>;
};

61
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
View File

@ -37,9 +37,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3v3: 3v3 {
reg_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -54,6 +57,8 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
rtc@51 {
@ -68,26 +73,78 @@
};
};
&iomuxc {
imx27-phycard-s-rdk {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_owire1: owire1grp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX27_PAD_UART3_TXD__UART3_TXD 0x0
MX27_PAD_UART3_RXD__UART3_RXD 0x0
MX27_PAD_UART3_CTS__UART3_CTS 0x0
MX27_PAD_UART3_RTS__UART3_RTS 0x0
>;
};
};
};
&owire {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_owire1>;
status = "okay";
};
&sdhci2 {
cd-gpios = <&gpio3 29 0>;
cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart1 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};

42
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
View File

@ -24,16 +24,54 @@
&cspi1 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 0>,
<&gpio4 27 0>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
<&gpio4 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
imx27-phycard-s-som {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
at24@52 {

97
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
View File

@ -7,7 +7,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx27-phytec-phycore-som.dts"
#include "imx27-phytec-phycore-som.dtsi"
/ {
model = "Phytec pcm970";
@ -16,32 +16,119 @@
&cspi1 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
<&gpio4 27 GPIO_ACTIVE_LOW>;
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
camgpio: pca9536@41 {
compatible = "nxp,pca9536";
reg = <0x41>;
gpio-controller;
#gpio-cells = <2>;
};
};
&iomuxc {
imx27_phycore_rdk {
pinctrl_i2c1: i2c1grp {
/* Add pullup to DATA line */
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x1
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_owire1: owire1grp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */
MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */
>;
};
};
};
&owire {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_owire1>;
status = "okay";
};
&sdhci2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhc2>;
bus-width = <4>;
cd-gpios = <&gpio3 29 0>;
wp-gpios = <&gpio3 28 0>;
cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vmmc1_reg>;
status = "okay";
};
&uart1 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>;
can@d4000000 {
compatible = "nxp,sja1000";
reg = <4 0x00000000 0x00000100>;
interrupt-parent = <&gpio5>;
interrupts = <19 0x2>;
interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
nxp,external-clock-frequency = <16000000>;
nxp,tx-output-config = <0x16>;
nxp,no-comparator-bypass;

97
arch/arm/boot/dts/imx27-phytec-phycore-som.dts → arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
View File

@ -19,6 +19,20 @@
memory {
reg = <0xa0000000 0x08000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
};
&audmux {
@ -37,18 +51,21 @@
};
&cspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 28 0>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: mc13783@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13783";
spi-max-frequency = <20000000>;
reg = <0>;
spi-cs-high;
spi-max-frequency = <20000000>;
interrupt-parent = <&gpio2>;
interrupts = <23 0x4>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
fsl,mc13xxx-uses-adc;
fsl,mc13xxx-uses-rtc;
@ -134,12 +151,18 @@
};
&fec {
phy-reset-gpios = <&gpio3 30 0>;
phy-mode = "mii";
phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
phy-supply = <&reg_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
at24@52 {
@ -159,13 +182,69 @@
};
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
&iomuxc {
imx27_phycore_som {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
};
};
&uart1 {
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};

526
arch/arm/boot/dts/imx27-pinfunc.h Normal file
View File

@ -0,0 +1,526 @@
/*
* Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DTS_IMX27_PINFUNC_H
#define __DTS_IMX27_PINFUNC_H
/*
* The pin function ID is a tuple of
* <pin mux_id>
* mux_id consists of
* function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
*
* function: 0 - Primary function
* 1 - Alternate function
* 2 - GPIO
* direction: 0 - Input
* 1 - Output
* gpio_oconf: 0 - A_IN
* 1 - B_IN
* 2 - C_IN
* 3 - Data Register
* gpio_iconfa/b: 0 - GPIO_IN
* 1 - Interrupt Status Register
* 2 - 0
* 3 - 1
*
* 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
* configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
* number on the specific port (between 0 and 31).
*/
#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032
#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032
#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004
#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032
#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000
#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032
#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004
#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032
#define MX27_PAD_LSCLK__LSCLK 0x05 0x004
#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032
#define MX27_PAD_LD0__LD0 0x06 0x004
#define MX27_PAD_LD0__GPIO1_6 0x06 0x032
#define MX27_PAD_LD1__LD1 0x07 0x004
#define MX27_PAD_LD1__GPIO1_7 0x07 0x032
#define MX27_PAD_LD2__LD2 0x08 0x004
#define MX27_PAD_LD2__GPIO1_8 0x08 0x032
#define MX27_PAD_LD3__LD3 0x09 0x004
#define MX27_PAD_LD3__GPIO1_9 0x09 0x032
#define MX27_PAD_LD4__LD4 0x0a 0x004
#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032
#define MX27_PAD_LD5__LD5 0x0b 0x004
#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032
#define MX27_PAD_LD6__LD6 0x0c 0x004
#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032
#define MX27_PAD_LD7__LD7 0x0d 0x004
#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032
#define MX27_PAD_LD8__LD8 0x0e 0x004
#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032
#define MX27_PAD_LD9__LD9 0x0f 0x004
#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032
#define MX27_PAD_LD10__LD10 0x10 0x004
#define MX27_PAD_LD10__GPIO1_16 0x10 0x032
#define MX27_PAD_LD11__LD11 0x11 0x004
#define MX27_PAD_LD11__GPIO1_17 0x11 0x032
#define MX27_PAD_LD12__LD12 0x12 0x004
#define MX27_PAD_LD12__GPIO1_18 0x12 0x032
#define MX27_PAD_LD13__LD13 0x13 0x004
#define MX27_PAD_LD13__GPIO1_19 0x13 0x032
#define MX27_PAD_LD14__LD14 0x14 0x004
#define MX27_PAD_LD14__GPIO1_20 0x14 0x032
#define MX27_PAD_LD15__LD15 0x15 0x004
#define MX27_PAD_LD15__GPIO1_21 0x15 0x032
#define MX27_PAD_LD16__LD16 0x16 0x004
#define MX27_PAD_LD16__GPIO1_22 0x16 0x032
#define MX27_PAD_LD17__LD17 0x17 0x004
#define MX27_PAD_LD17__GPIO1_23 0x17 0x032
#define MX27_PAD_REV__REV 0x18 0x004
#define MX27_PAD_REV__GPIO1_24 0x18 0x032
#define MX27_PAD_CLS__CLS 0x19 0x004
#define MX27_PAD_CLS__GPIO1_25 0x19 0x032
#define MX27_PAD_PS__PS 0x1a 0x004
#define MX27_PAD_PS__GPIO1_26 0x1a 0x032
#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004
#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032
#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004
#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032
#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004
#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032
#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004
#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032
#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004
#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032
#define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004
#define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x032
#define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004
#define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x032
#define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004
#define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x032
#define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004
#define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x032
#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004
#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005
#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032
#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004
#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005
#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032
#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004
#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005
#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032
#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004
#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005
#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032
#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004
#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005
#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032
#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004
#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005
#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032
#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000
#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005
#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032
#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000
#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001
#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032
#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000
#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005
#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032
#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000
#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001
#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032
#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000
#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032
#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004
#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032
#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000
#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032
#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000
#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032
#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000
#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005
#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032
#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000
#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001
#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032
#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000
#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005
#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032
#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000
#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001
#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032
#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004
#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032
#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004
#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032
#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000
#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032
#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004
#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032
#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004
#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001
#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032
#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004
#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032
#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004
#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005
#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032
#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004
#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005
#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032
#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004
#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032
#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004
#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001
#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032
#define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004
#define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x032
#define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004
#define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x032
#define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004
#define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x032
#define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004
#define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x032
#define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004
#define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x032
#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004
#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032
#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004
#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032
#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004
#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032
#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004
#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032
#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004
#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032
#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004
#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032
#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004
#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032
#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004
#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032
#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004
#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032
#define MX27_PAD_TOUT__TOUT 0x4e 0x004
#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032
#define MX27_PAD_TIN__TIN 0x4f 0x000
#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032
#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004
#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032
#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004
#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032
#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004
#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032
#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004
#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032
#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004
#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032
#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004
#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032
#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004
#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032
#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004
#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032
#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004
#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005
#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032
#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004
#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001
#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032
#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004
#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005
#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032
#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004
#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001
#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032
#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004
#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001
#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032
#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004
#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001
#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032
#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004
#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001
#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032
#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004
#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001
#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032
#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004
#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006
#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032
#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004
#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005
#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006
#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032
#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004
#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005
#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006
#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032
#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004
#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005
#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006
#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032
#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004
#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005
#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002
#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032
#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004
#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005
#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002
#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032
#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004
#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005
#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002
#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032
#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004
#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005
#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002
#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032
#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004
#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005
#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032
#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004
#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005
#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006
#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032
#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004
#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005
#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002
#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032
#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004
#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005
#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002
#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032
#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004
#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005
#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002
#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032
#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004
#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005
#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002
#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032
#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004
#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005
#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002
#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032
#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004
#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005
#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002
#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032
#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004
#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005
#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006
#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032
#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004
#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032
#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004
#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032
#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004
#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005
#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032
#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004
#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005
#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032
#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004
#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005
#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032
#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004
#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005
#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032
#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004
#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005
#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032
#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004
#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005
#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032
#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000
#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032
#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004
#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005
#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032
#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004
#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032
#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004
#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032
#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004
#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032
#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004
#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032
#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004
#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032
#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000
#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005
#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032
#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004
#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005
#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032
#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000
#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005
#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032
#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004
#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005
#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032
#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000
#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005
#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032
#define MX27_PAD_PWMO__PWMO 0x85 0x004
#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032
#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004
#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005
#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032
#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000
#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005
#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032
#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004
#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032
#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000
#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032
#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004
#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032
#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000
#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032
#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004
#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032
#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000
#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032
#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004
#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032
#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000
#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032
#define MX27_PAD_RTCK__RTCK 0x90 0x004
#define MX27_PAD_RTCK__OWIRE 0x90 0x005
#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032
#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004
#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032
#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004
#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001
#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032
#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004
#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032
#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004
#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032
#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004
#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005
#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032
#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004
#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005
#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032
#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004
#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005
#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032
#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000
#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032
#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004
#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032
#define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004
#define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x032
#define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004
#define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x032
#define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004
#define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x032
#define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004
#define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x032
#define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004
#define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x032
#define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004
#define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x032
#define MX27_PAD_NFRB__NFRB 0xa0 0x000
#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005
#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032
#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004
#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005
#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032
#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004
#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005
#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032
#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004
#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005
#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032
#define MX27_PAD_NFALE__NFALE 0xa4 0x004
#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005
#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032
#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004
#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005
#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032
#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004
#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005
#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032
#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004
#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005
#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032
#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004
#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001
#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032
#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000
#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001
#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032
#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004
#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005
#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032
#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000
#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005
#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032
#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000
#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001
#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032
#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000
#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005
#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032
#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000
#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005
#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032
#define MX27_PAD_CLKO__CLKO 0xaf 0x004
#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032
#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000
#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005
#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032
#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000
#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005
#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032
#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000
#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005
#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032
#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000
#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005
#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032
#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000
#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005
#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032
#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004
#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005
#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032
#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004
#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005
#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032
#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004
#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005
#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006
#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032
#define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004
#define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x032
#define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004
#define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x032
#define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004
#define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x032
#define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004
#define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x032
#define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004
#define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x032
#define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004
#define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x032
#define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004
#define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x032
#define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004
#define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x032
#endif /* __DTS_IMX27_PINFUNC_H */

141
arch/arm/boot/dts/imx27.dtsi
View File

@ -10,6 +10,9 @@
*/
#include "skeleton.dtsi"
#include "imx27-pinfunc.h"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
@ -204,6 +207,30 @@
status = "disabled";
};
ssi1: ssi@10010000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
reg = <0x10010000 0x1000>;
interrupts = <14>;
clocks = <&clks 26>;
dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
dma-names = "rx0", "tx0", "rx1", "tx1";
fsl,fifo-depth = <8>;
status = "disabled";
};
ssi2: ssi@10011000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
reg = <0x10011000 0x1000>;
interrupts = <13>;
clocks = <&clks 25>;
dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
dma-names = "rx0", "tx0", "rx1", "tx1";
fsl,fifo-depth = <8>;
status = "disabled";
};
i2c1: i2c@10012000 {
#address-cells = <1>;
#size-cells = <0>;
@ -236,64 +263,72 @@
status = "disabled";
};
gpio1: gpio@10015000 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015000 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio2: gpio@10015100 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015100 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@10015000 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015000 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@10015200 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015200 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@10015100 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015100 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@10015300 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015300 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@10015200 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015200 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@10015400 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015400 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@10015300 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015300 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@10015500 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015500 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio5: gpio@10015400 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015400 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@10015500 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015500 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
audmux: audmux@10016000 {

29
arch/arm/boot/dts/imx28-apf28dev.dts
View File

@ -48,6 +48,7 @@
MX28_PAD_LCD_D20__GPIO_1_20
MX28_PAD_LCD_D21__GPIO_1_21
MX28_PAD_LCD_D22__GPIO_1_22
MX28_PAD_GPMI_CE1N__GPIO_0_17
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
@ -66,6 +67,16 @@
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
usb0_otg_apf28dev: otg-apf28dev@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D23__GPIO_1_23
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
lcdif@80030000 {
@ -131,6 +142,8 @@
ahb@80080000 {
usb0: usb@80080000 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_otg_apf28dev>;
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
@ -150,13 +163,17 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb0_vbus: usb0_vbus {
reg_usb0_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 23 1>;
enable-active-high;
};
};
@ -177,4 +194,14 @@
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
gpio-keys {
compatible = "gpio-keys";
user-button {
label = "User button";
gpios = <&gpio0 17 0>;
linux,code = <0x100>;
};
};
};

5
arch/arm/boot/dts/imx28-apx4devkit.dts
View File

@ -193,9 +193,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: 3p3v {
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

2
arch/arm/boot/dts/imx28-cfa10036.dts
View File

@ -100,6 +100,8 @@
usb0: usb@80080000 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_otg_cfa10036>;
dr_mode = "peripheral";
phy_type = "utmi";
status = "okay";
};
};

7
arch/arm/boot/dts/imx28-cfa10037.dts
View File

@ -54,7 +54,7 @@
ahb@80080000 {
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-0 = <&usbphy1_pins_a>;
pinctrl-0 = <&usb1_pins_a>;
pinctrl-names = "default";
status = "okay";
};
@ -72,9 +72,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb1_vbus: usb1_vbus {
reg_usb1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&usb_pins_cfa10037>;
regulator-name = "usb1_vbus";

31
arch/arm/boot/dts/imx28-cfa10049.dts
View File

@ -229,15 +229,39 @@
i2c-parent = <&i2c1>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adc0: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adc1: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
adc2: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@3 {
@ -274,7 +298,7 @@
ahb@80080000 {
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-0 = <&usbphy1_pins_a>;
pinctrl-0 = <&usb1_pins_a>;
pinctrl-names = "default";
status = "okay";
};
@ -282,9 +306,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb1_vbus: usb1_vbus {
reg_usb1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&usb_pins_cfa10049>;
regulator-name = "usb1_vbus";

7
arch/arm/boot/dts/imx28-cfa10057.dts
View File

@ -134,7 +134,7 @@
ahb@80080000 {
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-0 = <&usbphy1_pins_a>;
pinctrl-0 = <&usb1_pins_a>;
pinctrl-names = "default";
status = "okay";
};
@ -142,9 +142,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb1_vbus: usb1_vbus {
reg_usb1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&usb_pins_cfa10057>;
regulator-name = "usb1_vbus";

7
arch/arm/boot/dts/imx28-cfa10058.dts
View File

@ -101,7 +101,7 @@
ahb@80080000 {
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-0 = <&usbphy1_pins_a>;
pinctrl-0 = <&usb1_pins_a>;
pinctrl-names = "default";
status = "okay";
};
@ -109,11 +109,14 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb1_vbus: usb1_vbus {
reg_usb1_vbus: regulator@0 {
pinctrl-names = "default";
pinctrl-0 = <&usb_pins_cfa10058>;
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

121
arch/arm/boot/dts/imx28-duckbill.dts Normal file
View File

@ -0,0 +1,121 @@
/*
* Copyright (C) 2013 Michael Heimpold <mhei@heimpold.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx28.dtsi"
/ {
model = "I2SE Duckbill";
compatible = "i2se,duckbill", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;
};
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a
&mmc0_cd_cfg &mmc0_sck_cfg>;
bus-width = <8>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
led_pins_a: led_gpio@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__GPIO_3_4
MX28_PAD_AUART1_TX__GPIO_3_5
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
};
apbx@80040000 {
duart: serial@80074000 {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
usbphy0: usbphy@8007c000 {
status = "okay";
};
};
};
ahb@80080000 {
usb0: usb@80080000 {
status = "okay";
};
mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-supply = <&reg_3p3v>;
phy-reset-gpios = <&gpio4 13 0>;
phy-reset-duration = <100>;
status = "okay";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_a>;
status {
label = "duckbill:green:status";
gpios = <&gpio3 5 0>;
};
failure {
label = "duckbill:red:status";
gpios = <&gpio3 4 0>;
};
};
};

71
arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts Normal file
View File

@ -0,0 +1,71 @@
/*
* Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
*/
/dts-v1/;
#include "imx28-eukrea-mbmx28lc.dtsi"
/ {
model = "Eukrea Electromatique MBMX283LC";
compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
memory {
reg = <0x40000000 0x04000000>;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&mac0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pinctrl{
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_cpuimx283>;
hog_pins_cpuimx283: hog-cpuimx283@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_ENET0_RX_CLK__GPIO_4_13
MX28_PAD_ENET0_TX_CLK__GPIO_4_5
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
};

50
arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC
*/
#include "imx28-eukrea-mbmx283lc.dts"
/ {
model = "Eukrea Electromatique MBMX287LC";
compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;
};
};
&mac1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac1_pins_a>;
phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>;
hog_pins_cpuimx287: hog-cpuimx287@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SPDIF__GPIO_3_27
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
};

326
arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi Normal file
View File

@ -0,0 +1,326 @@
/*
* Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx28.dtsi"
/ {
model = "Eukrea Electromatique MBMX28LC";
compatible = "eukrea,mbmx28lc", "fsl,imx28";
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 4 1000000>;
brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>;
default-brightness-level = <10>;
};
button-sw3 {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>;
sw3 {
label = "SW3";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
gpio-key,wakeup;
};
};
button-sw4 {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>;
sw4 {
label = "SW4";
gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
gpio-key,wakeup;
};
};
led-d6 {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_d6_pins_mbmx28lc>;
led1 {
label = "d6";
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
led-d7 {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_d7_pins_mbmx28lc>;
led1 {
label = "d7";
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_lcd_3v3: regulator@1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&reg_lcd_3v3_pins_mbmx28lc>;
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb0_vbus: regulator@2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&reg_usb0_vbus_pins_mbmx28lc>;
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb1_vbus: regulator@3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&reg_usb1_vbus_pins_mbmx28lc>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx28-mbmx28lc-sgtl5000",
"fsl,mxs-audio-sgtl5000";
model = "imx28-mbmx28lc-sgtl5000";
saif-controllers = <&saif0 &saif1>;
audio-codec = <&sgtl5000>;
};
};
&duart {
pinctrl-names = "default";
pinctrl-0 = <&duart_4pins_a>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
model = "43WVF1G-0";
bits-per-pixel = <16>;
bus-width = <18>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9072000>;
hactive = <480>;
vactive = <272>;
hback-porch = <10>;
hfront-porch = <5>;
vback-porch = <8>;
vfront-porch = <8>;
hsync-len = <40>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&lradc {
fsl,lradc-touchscreen-wires = <4>;
status = "okay";
};
&pinctrl {
gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D21__GPIO_1_21
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D20__GPIO_1_20
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_VSYNC__LCD_VSYNC
MX28_PAD_LCD_HSYNC__LCD_HSYNC
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
MX28_PAD_LCD_ENABLE__LCD_ENABLE
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D23__GPIO_1_23
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D22__GPIO_1_22
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_RESET__GPIO_3_30
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D18__GPIO_1_18
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D19__GPIO_1_19
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm4_pins_a>;
status = "okay";
};
&saif0 {
pinctrl-names = "default";
pinctrl-0 = <&saif0_pins_a>;
status = "okay";
};
&saif1 {
pinctrl-names = "default";
pinctrl-0 = <&saif1_pins_a>;
fsl,saif-master = <&saif0>;
status = "okay";
};
&ssp0 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>;
bus-width = <4>;
cd-inverted;
status = "okay";
};
&usb0 {
disable-over-current;
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_pins_b>;
};
&usb1 {
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usbphy0 {
status = "okay";
};
&usbphy1 {
status = "okay";
};

24
arch/arm/boot/dts/imx28-evk.dts
View File

@ -193,6 +193,7 @@
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
clock-frequency = <400000>;
status = "okay";
sgtl5000: codec@0a {
@ -278,33 +279,39 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: 3p3v {
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vddio_sd0: vddio-sd0 {
reg_vddio_sd0: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 28 0>;
};
reg_fec_3v3: fec-3v3 {
reg_fec_3v3: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "fec-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 15 0>;
};
reg_usb0_vbus: usb0_vbus {
reg_usb0_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -312,8 +319,9 @@
enable-active-high;
};
reg_usb1_vbus: usb1_vbus {
reg_usb1_vbus: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -321,8 +329,9 @@
enable-active-high;
};
reg_lcd_3v3: lcd-3v3 {
reg_lcd_3v3: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -330,8 +339,9 @@
enable-active-high;
};
reg_can_3v3: can-3v3 {
reg_can_3v3: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "can-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

17
arch/arm/boot/dts/imx28-m28cu3.dts
View File

@ -116,7 +116,6 @@
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_m28>;
display = <&display>;
reset-active-high;
status = "okay";
display: display0 {
@ -180,7 +179,7 @@
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&usbphy1_pins_a>;
pinctrl-0 = <&usb1_pins_a>;
disable-over-current;
status = "okay";
};
@ -229,33 +228,39 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: 3p3v {
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vddio_sd0: vddio-sd0 {
reg_vddio_sd0: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 29 0>;
};
reg_vddio_sd1: vddio-sd1 {
reg_vddio_sd1: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "vddio-sd1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 0>;
};
reg_usb1_vbus: usb1_vbus {
reg_usb1_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

18
arch/arm/boot/dts/imx28-m28evk.dts
View File

@ -248,14 +248,14 @@
usb0: usb@80080000 {
vbus-supply = <&reg_usb0_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&usbphy0_pins_a>;
pinctrl-0 = <&usb0_pins_a>;
status = "okay";
};
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&usbphy1_pins_a>;
pinctrl-0 = <&usb1_pins_a>;
status = "okay";
};
@ -285,33 +285,39 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: 3p3v {
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vddio_sd0: vddio-sd0 {
reg_vddio_sd0: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 28 0>;
};
reg_usb0_vbus: usb0_vbus {
reg_usb0_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 12 0>;
};
reg_usb1_vbus: usb1_vbus {
reg_usb1_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

7
arch/arm/boot/dts/imx28-sps1.dts
View File

@ -106,7 +106,7 @@
usb0: usb@80080000 {
vbus-supply = <&reg_usb0_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&usbphy0_pins_b>;
pinctrl-0 = <&usb0_pins_b>;
status = "okay";
};
@ -127,9 +127,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb0_vbus: usb0_vbus {
reg_usb0_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

23
arch/arm/boot/dts/imx28-tx28.dts
View File

@ -43,9 +43,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb0_vbus: usb0_vbus {
reg_usb0_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -53,8 +56,9 @@
enable-active-high;
};
reg_usb1_vbus: usb1_vbus {
reg_usb1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -62,24 +66,27 @@
enable-active-high;
};
reg_2p5v: 2p5v {
reg_2p5v: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: 3p3v {
reg_3p3v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_can_xcvr: can-xcvr {
reg_can_xcvr: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -89,8 +96,9 @@
pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
};
reg_lcd: lcd-power {
reg_lcd: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "LCD POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -98,8 +106,9 @@
enable-active-high;
};
reg_lcd_reset: lcd-reset {
reg_lcd_reset: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "LCD RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

65
arch/arm/boot/dts/imx28.dtsi
View File

@ -32,6 +32,8 @@
serial4 = &auart4;
spi0 = &ssp1;
spi1 = &ssp2;
usbphy0 = &usbphy0;
usbphy1 = &usbphy1;
};
cpus {
@ -343,6 +345,19 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
auart2_pins_a: auart2-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__AUART2_RX
MX28_PAD_AUART2_TX__AUART2_TX
MX28_PAD_AUART2_CTS__AUART2_CTS
MX28_PAD_AUART2_RTS__AUART2_RTS
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
auart3_pins_a: auart3@0 {
reg = <0>;
fsl,pinmux-ids = <
@ -655,6 +670,33 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
lcdif_18bit_pins_a: lcdif-18bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
MX28_PAD_LCD_D02__LCD_D2
MX28_PAD_LCD_D03__LCD_D3
MX28_PAD_LCD_D04__LCD_D4
MX28_PAD_LCD_D05__LCD_D5
MX28_PAD_LCD_D06__LCD_D6
MX28_PAD_LCD_D07__LCD_D7
MX28_PAD_LCD_D08__LCD_D8
MX28_PAD_LCD_D09__LCD_D9
MX28_PAD_LCD_D10__LCD_D10
MX28_PAD_LCD_D11__LCD_D11
MX28_PAD_LCD_D12__LCD_D12
MX28_PAD_LCD_D13__LCD_D13
MX28_PAD_LCD_D14__LCD_D14
MX28_PAD_LCD_D15__LCD_D15
MX28_PAD_LCD_D16__LCD_D16
MX28_PAD_LCD_D17__LCD_D17
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
lcdif_16bit_pins_a: lcdif-16bit@0 {
reg = <0>;
fsl,pinmux-ids = <
@ -743,7 +785,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
usbphy0_pins_a: usbphy0@0 {
usb0_pins_a: usb0@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
@ -753,7 +795,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
usbphy0_pins_b: usbphy0@1 {
usb0_pins_b: usb0@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
@ -763,7 +805,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
usbphy1_pins_a: usbphy1@0 {
usb1_pins_a: usb1@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
@ -782,6 +824,17 @@
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
usb0_id_pins_b: usb0id1@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_PWM2__USB0_ID
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
};
digctl: digctl@8001c000 {
@ -946,6 +999,7 @@
20 21 22 23 24 25>;
status = "disabled";
clocks = <&clks 41>;
#io-channel-cells = <1>;
};
spdif: spdif@80054000 {
@ -1130,4 +1184,9 @@
status = "disabled";
};
};
iio_hwmon {
compatible = "iio-hwmon";
io-channels = <&lradc 8>;
};
};

81
arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi Normal file
View File

@ -0,0 +1,81 @@
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "imx35.dtsi"
/ {
model = "Eukrea CPUIMX35";
compatible = "eukrea,cpuimx35", "fsl,imx35";
memory {
reg = <0x80000000 0x8000000>; /* 128M */
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&iomuxc {
imx35-eukrea {
pinctrl_fec: fecgrp {
fsl,pins = <
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000
MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX35_PAD_FEC_COL__FEC_COL 0x80000000
MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000
MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000
MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX35_PAD_FEC_MDC__FEC_MDC 0x80000000
MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000
MX35_PAD_FEC_CRS__FEC_CRS 0x80000000
MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000
MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000
MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000
MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000
MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000
MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000
MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000
>;
};
};
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};

143
arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts Normal file
View File

@ -0,0 +1,143 @@
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx35-eukrea-cpuimx35.dtsi"
/ {
model = "Eukrea CPUIMX35";
compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35";
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bp1>;
bp1 {
label = "BP1";
gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
gpio-key,wakeup;
linux,input-type = <1>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led1>;
led1 {
label = "led1";
gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio3 24>;
status = "okay";
};
&i2c1 {
tlv320aic23: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
};
};
&iomuxc {
imx35-eukrea {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000
MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000
MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000
>;
};
pinctrl_bp1: bp1grp {
fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */
>;
};
pinctrl_led1: led1grp {
fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>;
};
pinctrl_reg_lcd_3v3: reg-lcd-3v3 {
fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
MX35_PAD_CTS1__UART1_CTS 0x1c5
MX35_PAD_RTS1__UART1_RTS 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5
MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5
MX35_PAD_RTS2__UART2_RTS 0x1c5
MX35_PAD_CTS2__UART2_CTS 0x1c5
>;
};
};
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "okay";
};

359
arch/arm/boot/dts/imx35.dtsi Normal file
View File

@ -0,0 +1,359 @@
/*
* Copyright 2012 Steffen Trumtrar, Pengutronix
*
* based on imx27.dtsi
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include "skeleton.dtsi"
#include "imx35-pinfunc.h"
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &spi1;
spi1 = &spi2;
};
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm1136";
device_type = "cpu";
};
};
avic: avic-interrupt-controller@68000000 {
compatible = "fsl,imx35-avic", "fsl,avic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x68000000 0x10000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&avic>;
ranges;
L2: l2-cache@30000000 {
compatible = "arm,l210-cache";
reg = <0x30000000 0x1000>;
cache-unified;
cache-level = <2>;
};
aips1: aips@43f00000 {
compatible = "fsl,aips", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x43f00000 0x100000>;
ranges;
i2c1: i2c@43f80000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
reg = <0x43f80000 0x4000>;
clocks = <&clks 51>;
clock-names = "ipg_per";
interrupts = <10>;
status = "disabled";
};
i2c3: i2c@43f84000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
reg = <0x43f84000 0x4000>;
clocks = <&clks 53>;
clock-names = "ipg_per";
interrupts = <3>;
status = "disabled";
};
uart1: serial@43f90000 {
compatible = "fsl,imx35-uart", "fsl,imx21-uart";
reg = <0x43f90000 0x4000>;
clocks = <&clks 9>, <&clks 70>;
clock-names = "ipg", "per";
interrupts = <45>;
status = "disabled";
};
uart2: serial@43f94000 {
compatible = "fsl,imx35-uart", "fsl,imx21-uart";
reg = <0x43f94000 0x4000>;
clocks = <&clks 9>, <&clks 71>;
clock-names = "ipg", "per";
interrupts = <32>;
status = "disabled";
};
i2c2: i2c@43f98000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
reg = <0x43f98000 0x4000>;
clocks = <&clks 52>;
clock-names = "ipg_per";
interrupts = <4>;
status = "disabled";
};
ssi1: ssi@43fa0000 {
compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
reg = <0x43fa0000 0x4000>;
interrupts = <11>;
clocks = <&clks 68>;
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
spi1: cspi@43fa4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx35-cspi";
reg = <0x43fa4000 0x4000>;
clocks = <&clks 35 &clks 35>;
clock-names = "ipg", "per";
interrupts = <14>;
status = "disabled";
};
iomuxc: iomuxc@43fac000 {
compatible = "fsl,imx35-iomuxc";
reg = <0x43fac000 0x4000>;
};
};
spba: spba-bus@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x100000>;
ranges;
uart3: serial@5000c000 {
compatible = "fsl,imx35-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
clocks = <&clks 9>, <&clks 72>;
clock-names = "ipg", "per";
interrupts = <18>;
status = "disabled";
};
spi2: cspi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx35-cspi";
reg = <0x50010000 0x4000>;
interrupts = <13>;
clocks = <&clks 36 &clks 36>;
clock-names = "ipg", "per";
status = "disabled";
};
fec: fec@50038000 {
compatible = "fsl,imx35-fec", "fsl,imx27-fec";
reg = <0x50038000 0x4000>;
clocks = <&clks 46>, <&clks 8>;
clock-names = "ipg", "ahb";
interrupts = <57>;
status = "disabled";
};
};
aips2: aips@53f00000 {
compatible = "fsl,aips", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x53f00000 0x100000>;
ranges;
clks: ccm@53f80000 {
compatible = "fsl,imx35-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};
gpio3: gpio@53fa4000 {
compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
reg = <0x53fa4000 0x4000>;
interrupts = <56>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
esdhc2: esdhc@53fb8000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb8000 0x4000>;
interrupts = <8>;
clocks = <&clks 9>, <&clks 8>, <&clks 44>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
esdhc3: esdhc@53fbc000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fbc000 0x4000>;
interrupts = <9>;
clocks = <&clks 9>, <&clks 8>, <&clks 45>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
audmux: audmux@53fc4000 {
compatible = "fsl,imx35-audmux", "fsl,imx31-audmux";
reg = <0x53fc4000 0x4000>;
status = "disabled";
};
gpio1: gpio@53fcc000 {
compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
reg = <0x53fcc000 0x4000>;
interrupts = <52>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@53fd0000 {
compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
reg = <0x53fd0000 0x4000>;
interrupts = <51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sdma: sdma@53fd4000 {
compatible = "fsl,imx35-sdma";
reg = <0x53fd4000 0x4000>;
clocks = <&clks 9>, <&clks 65>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
interrupts = <34>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin";
};
wdog: wdog@53fdc000 {
compatible = "fsl,imx35-wdt", "fsl,imx21-wdt";
reg = <0x53fdc000 0x4000>;
clocks = <&clks 74>;
clock-names = "";
interrupts = <55>;
};
can1: can@53fe4000 {
compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
reg = <0x53fe4000 0x1000>;
clocks = <&clks 33>;
clock-names = "ipg";
interrupts = <43>;
status = "disabled";
};
can2: can@53fe8000 {
compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
reg = <0x53fe8000 0x1000>;
clocks = <&clks 34>;
clock-names = "ipg";
interrupts = <44>;
status = "disabled";
};
usbotg: usb@53ff4000 {
compatible = "fsl,imx35-usb", "fsl,imx27-usb";
reg = <0x53ff4000 0x0200>;
interrupts = <37>;
clocks = <&clks 9>, <&clks 73>, <&clks 28>;
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
usbhost1: usb@53ff4400 {
compatible = "fsl,imx35-usb", "fsl,imx27-usb";
reg = <0x53ff4400 0x0200>;
interrupts = <35>;
clocks = <&clks 9>, <&clks 73>, <&clks 28>;
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
usbmisc: usbmisc@53ff4600 {
#index-cells = <1>;
compatible = "fsl,imx35-usbmisc";
clocks = <&clks 9>, <&clks 73>, <&clks 28>;
clock-names = "ipg", "ahb", "per";
reg = <0x53ff4600 0x00f>;
};
};
emi@80000000 { /* External Memory Interface */
compatible = "fsl,emi", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x40000000>;
ranges;
nfc: nand@bb000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx35-nand", "fsl,imx25-nand";
reg = <0xbb000000 0x2000>;
clocks = <&clks 29>;
clock-names = "";
interrupts = <33>;
status = "disabled";
};
weim: weim@b8002000 {
#address-cells = <2>;
#size-cells = <1>;
clocks = <&clks 0>;
compatible = "fsl,imx35-weim", "fsl,imx27-weim";
reg = <0xb8002000 0x1000>;
ranges = <
0 0 0xa0000000 0x8000000
1 0 0xa8000000 0x8000000
2 0 0xb0000000 0x2000000
3 0 0xb2000000 0x2000000
4 0 0xb4000000 0x2000000
5 0 0xb6000000 0x2000000
>;
status = "disabled";
};
};
};
};

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/*
* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx50.dtsi"
/ {
model = "Freescale i.MX50 Evaluation Kit";
compatible = "fsl,imx50-evk", "fsl,imx50";
memory {
reg = <0x70000000 0x80000000>;
};
};
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
status = "okay";
flash: m25p32@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p32", "m25p80";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "kernel";
reg = <0x100000 0x300000>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 12 0>;
status = "okay";
};
&iomuxc {
imx50-evk {
pinctrl_cspi: cspigrp {
fsl,pins = <
MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX50_PAD_SSI_RXFS__FEC_MDC 0x80
MX50_PAD_SSI_RXC__FEC_MDIO 0x80
MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
MX50_PAD_DISP_D2__FEC_RX_DV 0x80
MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
MX50_PAD_DISP_D5__FEC_TX_EN 0x80
MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbh2 {
status = "okay";
};
&usbh3 {
status = "okay";
};
&usbotg {
status = "okay";
};

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arch/arm/boot/dts/imx50-pinfunc.h Normal file
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/*
* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX50_PINFUNC_H
#define __DTS_IMX50_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
#define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
#define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
#define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
#define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0
#define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0
#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0
#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0
#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0
#define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0
#define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0
#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0
#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0
#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0
#define MX50_PAD_KEY_COL2__KPP_COL_1 0x030 0x2dc 0x000 0x0 0x0
#define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0
#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0
#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0
#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0
#define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0
#define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0
#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0
#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0
#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0
#define MX50_PAD_KEY_COL3__KPP_COL_2 0x038 0x2e4 0x000 0x0 0x0
#define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0
#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0
#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0
#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0
#define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0
#define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0
#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0
#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0
#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0
#define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0
#define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0
#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0
#define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0
#define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0
#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1
#define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0
#define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0
#define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0
#define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0
#define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0
#define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1
#define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0
#define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0
#define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0
#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0
#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0
#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0
#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0
#define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0
#define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0
#define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0
#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0
#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0
#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0
#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0
#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0
#define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0
#define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0
#define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1
#define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0
#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0
#define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0
#define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0
#define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0
#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0
#define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0
#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0
#define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0
#define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0
#define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0
#define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0
#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0
#define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0
#define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0
#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0
#define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0
#define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0
#define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0
#define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0
#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0
#define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0
#define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0
#define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0
#define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0
#define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0
#define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0
#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0
#define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0
#define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0
#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0
#define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0
#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0
#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0
#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0
#define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0
#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0
#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0
#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0
#define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0
#define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0
#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0
#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0
#define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0
#define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0
#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0
#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0
#define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0
#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0
#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0
#define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0
#define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0
#define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0
#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0
#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0
#define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0
#define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1
#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0
#define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0
#define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0
#define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1
#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0
#define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0
#define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0
#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0
#define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1
#define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0
#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0
#define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0
#define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0
#define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2
#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0
#define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0
#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0
#define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3
#define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0
#define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3
#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0
#define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0
#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0
#define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2
#define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0
#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0
#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1
#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0
#define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3
#define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0
#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0
#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1
#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0
#define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0
#define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0
#define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1
#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1
#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0
#define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2
#define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0
#define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1
#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1
#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0
#define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0
#define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0
#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0
#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0
#define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0
#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0
#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0
#define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1
#define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0
#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0
#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0
#define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0
#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0
#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0
#define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0
#define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0
#define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0
#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0
#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0
#define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0
#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0
#define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1
#define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0
#define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1
#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0
#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0
#define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0
#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0
#define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0
#define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0
#define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0
#define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0
#define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0
#define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0
#define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0
#define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0
#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0
#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0
#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1
#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0
#define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2
#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0
#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0
#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0
#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0
#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1
#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0
#define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0
#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0
#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0
#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0
#define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0
#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1
#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0
#define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0
#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0
#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0
#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0
#define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0
#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1
#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0
#define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0
#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0
#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0
#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0
#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0
#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0
#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0
#define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0
#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0
#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0
#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1
#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0
#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0
#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0
#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0
#define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1
#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0
#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0
#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1
#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0
#define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0
#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0
#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0
#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4
#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0
#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0
#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1
#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0
#define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0
#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0
#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0
#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5
#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0
#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0
#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1
#define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0
#define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0
#define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0
#define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0
#define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0
#define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0
#define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0
#define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0
#define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0
#define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0
#define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0
#define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0
#define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0
#define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0
#define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0
#define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0
#define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0
#define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0
#define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0
#define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0
#define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0
#define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0
#define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0
#define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0
#define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0
#define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0
#define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0
#define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0
#define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0
#define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0
#define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0
#define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0
#define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0
#define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0
#define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0
#define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0
#define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0
#define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0
#define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0
#define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0
#define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0
#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0
#define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0
#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0
#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0
#define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0
#define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0
#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0
#define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0
#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0
#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0
#define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0
#define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0
#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0
#define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0
#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0
#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0
#define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0
#define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0
#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0
#define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0
#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0
#define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0
#define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1
#define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0
#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0
#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0
#define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0
#define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1
#define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0
#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0
#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0
#define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0
#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0
#define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0
#define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0
#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0
#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0
#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0
#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0
#define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0
#define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0
#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0
#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0
#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0
#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0
#define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0
#define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0
#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0
#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0
#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0
#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0
#define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0
#define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0
#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0
#define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1
#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0
#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0
#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0
#define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0
#define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0
#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0
#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0
#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0
#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0
#define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0
#define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0
#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0
#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0
#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0
#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0
#define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0
#define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0
#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0
#define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1
#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0
#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0
#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0
#define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0
#define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0
#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0
#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0
#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0
#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0
#define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0
#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0
#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0
#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0
#define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0
#define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0
#define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0
#define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0
#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0
#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0
#define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0
#define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0
#define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0
#define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1
#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0
#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0
#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0
#define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0
#define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0
#define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1
#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0
#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0
#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0
#define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0
#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2
#define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0
#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0
#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0
#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0
#define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0
#define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0
#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0
#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0
#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0
#define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0
#define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0
#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0
#define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0
#define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0
#define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0
#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0
#define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0
#define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0
#define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0
#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0
#define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0
#define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1
#define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0
#define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0
#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0
#define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0
#define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0
#define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0
#define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0
#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0
#define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0
#define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1
#define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0
#define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0
#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0
#define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0
#define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0
#define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0
#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0
#define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0
#define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0
#define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0
#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0
#define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0
#define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0
#define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0
#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0
#define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0
#define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0
#define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0
#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0
#define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0
#define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0
#define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0
#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0
#define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0
#define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0
#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0
#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0
#define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0
#define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0
#define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0
#define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2
#define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1
#define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1
#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0
#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0
#define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0
#define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0
#define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0
#define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2
#define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1
#define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1
#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0
#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0
#define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0
#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0
#define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0
#define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0
#define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1
#define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1
#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0
#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0
#define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0
#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0
#define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1
#define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1
#define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1
#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0
#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0
#define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0
#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0
#define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0
#define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1
#define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1
#define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1
#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0
#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0
#define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0
#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0
#define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0
#define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1
#define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1
#define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0
#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0
#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0
#define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0
#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1
#define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0
#define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0
#define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1
#define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0
#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0
#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0
#define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0
#define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1
#define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0
#define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0
#define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1
#define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0
#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0
#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0
#define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0
#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1
#define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0
#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0
#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0
#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0
#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0
#define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0
#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1
#define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0
#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0
#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0
#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0
#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0
#define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0
#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1
#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0
#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2
#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0
#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0
#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0
#define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0
#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1
#define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0
#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3
#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0
#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0
#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0
#define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0
#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1
#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0
#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0
#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0
#define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0
#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1
#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0
#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0
#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0
#define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0
#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1
#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0
#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0
#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0
#define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0
#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1
#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0
#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0
#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0
#define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0
#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2
#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0
#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0
#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0
#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0
#define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0
#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2
#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0
#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0
#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0
#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0
#define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0
#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2
#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0
#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0
#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0
#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0
#define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0
#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2
#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0
#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0
#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0
#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0
#define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0
#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1
#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0
#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0
#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0
#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0
#define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0
#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1
#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0
#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0
#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0
#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0
#define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0
#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1
#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0
#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0
#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0
#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0
#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0
#define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0
#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1
#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0
#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0
#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0
#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0
#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0
#define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0
#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0
#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0
#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0
#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0
#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0
#define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0
#define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0
#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0
#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0
#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0
#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0
#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0
#define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0
#define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0
#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0
#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0
#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0
#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0
#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0
#define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0
#define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0
#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0
#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0
#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0
#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0
#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0
#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0
#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0
#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0
#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0
#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0
#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0
#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0
#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0
#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0
#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0
#define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0
#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0
#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0
#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0
#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0
#define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0
#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0
#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0
#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0
#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0
#define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0
#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1
#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0
#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0
#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0
#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0
#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1
#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0
#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0
#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0
#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0
#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1
#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1
#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0
#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0
#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0
#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0
#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0
#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1
#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1
#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0
#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0
#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0
#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0
#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0
#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1
#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1
#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0
#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0
#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0
#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0
#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0
#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1
#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1
#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0
#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0
#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0
#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0
#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0
#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1
#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1
#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0
#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0
#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0
#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0
#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0
#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1
#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1
#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1
#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0
#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0
#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0
#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0
#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1
#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0
#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0
#define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0
#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0
#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0
#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0
#define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0
#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0
#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0
#define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0
#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1
#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0
#define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0
#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1
#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1
#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0
#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1
#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1
#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1
#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0
#define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0
#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1
#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0
#define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0
#define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2
#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0
#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0
#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0
#define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0
#define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2
#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0
#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0
#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0
#define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0
#define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2
#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0
#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0
#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0
#define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0
#define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2
#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0
#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0
#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0
#define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0
#define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2
#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0
#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0
#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0
#define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0
#define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2
#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0
#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0
#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0
#define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0
#define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2
#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0
#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0
#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0
#define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0
#define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2
#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0
#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0
#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0
#define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0
#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0
#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0
#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0
#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0
#define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0
#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0
#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0
#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0
#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0
#define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0
#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0
#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0
#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0
#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0
#define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0
#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0
#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0
#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0
#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0
#define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0
#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0
#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0
#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0
#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0
#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0
#define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0
#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0
#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0
#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0
#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0
#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0
#define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0
#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2
#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0
#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0
#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0
#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0
#define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0
#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2
#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0
#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0
#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0
#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0
#define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0
#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0
#define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0
#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0
#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0
#define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0
#define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0
#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0
#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0
#define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0
#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0
#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0
#define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0
#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0
#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0
#define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0
#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0
#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0
#define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0
#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0
#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0
#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0
#define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0
#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0
#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0
#define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0
#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0
#define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0
#define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0
#define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0
#define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0
#define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0
#define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0
#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0
#define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0
#define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0
#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0
#define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0
#endif /* __DTS_IMX50_PINFUNC_H */

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arch/arm/boot/dts/imx50.dtsi Normal file
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/*
* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0x0>;
};
};
tzic: tz-interrupt-controller@0fffc000 {
compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x0fffc000 0x4000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&tzic>;
ranges;
aips@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x10000000>;
ranges;
spba@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x40000>;
ranges;
esdhc1: esdhc@50004000 {
compatible = "fsl,imx50-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
esdhc2: esdhc@50008000 {
compatible = "fsl,imx50-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
uart3: serial@5000c000 {
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi1: ecspi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
ssi2: ssi@50014000 {
compatible = "fsl,imx50-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x50014000 0x4000>;
interrupts = <30>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
esdhc3: esdhc@50020000 {
compatible = "fsl,imx50-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
esdhc4: esdhc@50024000 {
compatible = "fsl,imx50-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
};
usbotg: usb@53f80000 {
compatible = "fsl,imx50-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
status = "disabled";
};
usbh1: usb@53f80200 {
compatible = "fsl,imx50-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
status = "disabled";
};
usbh2: usb@53f80400 {
compatible = "fsl,imx50-usb", "fsl,imx27-usb";
reg = <0x53f80400 0x0200>;
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
status = "disabled";
};
usbh3: usb@53f80600 {
compatible = "fsl,imx50-usb", "fsl,imx27-usb";
reg = <0x53f80600 0x0200>;
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
status = "disabled";
};
gpio1: gpio@53f84000 {
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
reg = <0x53f84000 0x4000>;
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@53f88000 {
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
reg = <0x53f88000 0x4000>;
interrupts = <52 53>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@53f8c000 {
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
reg = <0x53f8c000 0x4000>;
interrupts = <54 55>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@53f90000 {
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
reg = <0x53f90000 0x4000>;
interrupts = <56 57>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
wdog1: wdog@53f98000 {
compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
clocks = <&clks IMX5_CLK_DUMMY>;
};
gpt: timer@53fa0000 {
compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
reg = <0x53fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
iomuxc: iomuxc@53fa8000 {
compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
};
gpr: iomuxc-gpr@53fa8000 {
compatible = "fsl,imx50-iomuxc-gpr", "syscon";
reg = <0x53fa8000 0xc>;
};
pwm1: pwm@53fb4000 {
#pwm-cells = <2>;
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
pwm2: pwm@53fb8000 {
#pwm-cells = <2>;
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
uart1: serial@53fbc000 {
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@53fc0000 {
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
src: src@53fd0000 {
compatible = "fsl,imx50-src", "fsl,imx51-src";
reg = <0x53fd0000 0x4000>;
#reset-cells = <1>;
};
clks: ccm@53fd4000{
compatible = "fsl,imx50-ccm";
reg = <0x53fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
#clock-cells = <1>;
};
gpio5: gpio@53fdc000 {
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
reg = <0x53fdc000 0x4000>;
interrupts = <103 104>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@53fe0000 {
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
reg = <0x53fe0000 0x4000>;
interrupts = <105 106>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2c3: i2c@53fec000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
reg = <0x53fec000 0x4000>;
interrupts = <64>;
clocks = <&clks IMX5_CLK_I2C3_GATE>;
status = "disabled";
};
uart4: serial@53ff0000 {
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
<&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
};
aips@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x60000000 0x10000000>;
ranges;
uart5: serial@63f90000 {
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
<&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
owire: owire@63fa4000 {
compatible = "fsl,imx50-owire", "fsl,imx21-owire";
reg = <0x63fa4000 0x4000>;
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
status = "disabled";
};
ecspi2: ecspi@63fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
sdma: sdma@63fb0000 {
compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
};
cspi: cspi@63fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c2: i2c@63fc4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
reg = <0x63fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks IMX5_CLK_I2C2_GATE>;
status = "disabled";
};
i2c1: i2c@63fc8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
reg = <0x63fc8000 0x4000>;
interrupts = <62>;
clocks = <&clks IMX5_CLK_I2C1_GATE>;
status = "disabled";
};
ssi1: ssi@63fcc000 {
compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
audmux: audmux@63fd0000 {
compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
reg = <0x63fd0000 0x4000>;
status = "disabled";
};
fec: ethernet@63fec000 {
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
};
};
};

40
arch/arm/boot/dts/imx51-apf51.dts
View File

@ -34,13 +34,47 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_2>;
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio3 0 0>;
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
phy-reset-duration = <1>;
status = "okay";
};
&iomuxc {
imx51-apf51 {
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
>;
};
};
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
@ -50,6 +84,6 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_2>;
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};

102
arch/arm/boot/dts/imx51-apf51dev.dts
View File

@ -21,7 +21,7 @@
crtcs = <&ipu 0>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
pinctrl-0 = <&pinctrl_ipu_disp1>;
display-timings {
lw700 {
@ -48,7 +48,7 @@
user-key {
label = "user";
gpios = <&gpio1 3 0>;
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
linux,code = <256>; /* BTN_0 */
};
};
@ -58,7 +58,7 @@
user {
label = "Heartbeat";
gpios = <&gpio1 2 0>;
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
@ -66,31 +66,33 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2_1>;
pinctrl-0 = <&pinctrl_ecspi2>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>;
cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
<&gpio3 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio2 29 0>;
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
pinctrl-0 = <&pinctrl_esdhc2>;
bus-width = <4>;
non-removable;
status = "okay";
@ -98,7 +100,7 @@
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_2>;
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
@ -106,7 +108,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx51-apf51dev {
pinctrl_hog: hoggrp {
fsl,pins = <
MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
@ -120,5 +122,81 @@
MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
>;
};
pinctrl_ipu_disp1: ipudisp1grp {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
>;
};
};
};

238
arch/arm/boot/dts/imx51-babbage.dts
View File

@ -26,7 +26,7 @@
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
pinctrl-0 = <&pinctrl_ipu_disp1>;
display-timings {
native-mode = <&timing0>;
timing0: dvi {
@ -48,7 +48,7 @@
crtcs = <&ipu 1>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
pinctrl-0 = <&pinctrl_ipu_disp2>;
status = "disabled";
display-timings {
native-mode = <&timing1>;
@ -75,7 +75,7 @@
power {
label = "Power Button";
gpios = <&gpio2 21 0>;
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
@ -105,14 +105,14 @@
reg=<0>;
#clock-cells = <0>;
clock-frequency = <26000000>;
gpios = <&gpio4 26 1>;
gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
pinctrl-0 = <&pinctrl_esdhc1>;
fsl,cd-controller;
fsl,wp-controller;
status = "okay";
@ -120,24 +120,25 @@
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio1 6 0>;
wp-gpios = <&gpio1 5 0>;
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_LOW>;
status = "okay";
pmic: mc13892@0 {
@ -148,7 +149,7 @@
spi-cs-high;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 0x4>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
regulators {
sw1_reg: sw1 {
@ -267,7 +268,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx51-babbage {
pinctrl_hog: hoggrp {
fsl,pins = <
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
@ -280,25 +281,188 @@
MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
>;
};
pinctrl_ipu_disp1: ipudisp1grp {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
>;
};
pinctrl_ipu_disp2: ipudisp2grp {
fsl,pins = <
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
MX51_PAD_DI_GP4__DI2_PIN15 0x5
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@0a {
@ -312,35 +476,39 @@
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp_1>;
linux,keymap = <0x00000067 /* KEY_UP */
0x0001006c /* KEY_DOWN */
0x00020072 /* KEY_VOLUMEDOWN */
0x00030066 /* KEY_HOME */
0x0100006a /* KEY_RIGHT */
0x01010069 /* KEY_LEFT */
0x0102001c /* KEY_ENTER */
0x01030073 /* KEY_VOLUMEUP */
0x02000040 /* KEY_F6 */
0x02010042 /* KEY_F8 */
0x02020043 /* KEY_F9 */
0x02030044 /* KEY_F10 */
0x0300003b /* KEY_F1 */
0x0301003c /* KEY_F2 */
0x0302003d /* KEY_F3 */
0x03030074>; /* KEY_POWER */
pinctrl-0 = <&pinctrl_kpp>;
linux,keymap = <
MATRIX_KEY(0, 0, KEY_UP)
MATRIX_KEY(0, 1, KEY_DOWN)
MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
MATRIX_KEY(0, 3, KEY_HOME)
MATRIX_KEY(1, 0, KEY_RIGHT)
MATRIX_KEY(1, 1, KEY_LEFT)
MATRIX_KEY(1, 2, KEY_ENTER)
MATRIX_KEY(1, 3, KEY_VOLUMEUP)
MATRIX_KEY(2, 0, KEY_F6)
MATRIX_KEY(2, 1, KEY_F8)
MATRIX_KEY(2, 2, KEY_F9)
MATRIX_KEY(2, 3, KEY_F10)
MATRIX_KEY(3, 0, KEY_F1)
MATRIX_KEY(3, 1, KEY_F2)
MATRIX_KEY(3, 2, KEY_F3)
MATRIX_KEY(3, 3, KEY_POWER)
>;
status = "okay";
};

93
arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi Normal file
View File

@ -0,0 +1,93 @@
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include "imx51.dtsi"
/ {
model = "Eukrea CPUIMX51";
compatible = "eukrea,cpuimx51", "fsl,imx51";
memory {
reg = <0x90000000 0x10000000>; /* 256M */
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&iomuxc {
imx51-eukrea {
pinctrl_tsc2007_1: tsc2007grp-1 {
fsl,pins = <
MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed
MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
>;
};
};
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};

175
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts Normal file
View File

@ -0,0 +1,175 @@
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
/dts-v1/;
#include "imx51-eukrea-cpuimx51.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Eukrea CPUIMX51";
compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys_1>;
button-1 {
label = "BP1";
gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
linux,code = <256>;
gpio-key,wakeup;
linux,input-type = <1>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioled>;
led1 {
label = "led1";
gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
sound {
compatible = "eukrea,asoc-tlv320";
eukrea,model = "imx51-eukrea-tlv320aic23";
ssi-controller = <&ssi2>;
fsl,mux-int-port = <2>;
fsl,mux-ext-port = <3>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>;
fsl,cd-controller;
status = "okay";
};
&i2c1 {
tlv320aic23: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
};
};
&iomuxc {
imx51-eukrea {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
>;
};
pinctrl_uart3_rtscts: uart3rtsctsgrp {
fsl,pins = <
MX51_PAD_KEY_COL4__UART3_RTS 0x1c5
MX51_PAD_KEY_COL5__UART3_CTS 0x1c5
>;
};
pinctrl_backlight_1: backlightgrp-1 {
fsl,pins = <
MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5
>;
};
pinctrl_esdhc1_cd: esdhc1_cd {
fsl,pins = <
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
>;
};
pinctrl_gpiokeys_1: gpiokeysgrp-1 {
fsl,pins = <
MX51_PAD_NANDF_D9__GPIO3_31 0x1f5
>;
};
pinctrl_gpioled: gpioledgrp-1 {
fsl,pins = <
MX51_PAD_NANDF_D10__GPIO3_30 0x80000000
>;
};
pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
fsl,pins = <
MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
>;
};
};
};
&ssi2 {
codec-handle = <&tlv320aic23>;
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};

459
arch/arm/boot/dts/imx51.dtsi
View File

@ -12,6 +12,10 @@
#include "skeleton.dtsi"
#include "imx51-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
@ -21,6 +25,10 @@
gpio3 = &gpio4;
i2c0 = &i2c1;
i2c1 = &i2c2;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
mmc3 = &esdhc4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
@ -64,18 +72,32 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 24>;
clock-latency = <62500>;
clocks = <&clks IMX5_CLK_CPU_PODF>;
clock-names = "cpu";
operating-points = <
/* kHz uV (No regulator support) */
160000 0
800000 0
166000 1000000
600000 1050000
800000 1100000
>;
voltage-tolerance = <5>;
};
};
usbphy {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-bus";
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
reg = <0>;
clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
clock-names = "main_clk";
};
};
@ -96,7 +118,9 @@
compatible = "fsl,imx51-ipu";
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
};
@ -119,7 +143,9 @@
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@ -128,7 +154,9 @@
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -138,7 +166,8 @@
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
clocks = <&clks 32>, <&clks 33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -149,7 +178,8 @@
compatible = "fsl,imx51-ecspi";
reg = <0x70010000 0x4000>;
interrupts = <36>;
clocks = <&clks 51>, <&clks 52>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -158,7 +188,7 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
clocks = <&clks 49>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
@ -171,7 +201,9 @@
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
interrupts = <3>;
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -181,25 +213,20 @@
compatible = "fsl,imx51-esdhc";
reg = <0x70024000 0x4000>;
interrupts = <4>;
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
};
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
clocks = <&clks 75>;
clock-names = "main_clk";
status = "okay";
};
usbotg: usb@73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
@ -209,7 +236,7 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
@ -218,7 +245,7 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
@ -227,7 +254,7 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
status = "disabled";
};
@ -236,7 +263,7 @@
#index-cells = <1>;
compatible = "fsl,imx51-usbmisc";
reg = <0x73f80800 0x200>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
};
gpio1: gpio@73f84000 {
@ -283,7 +310,7 @@
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
reg = <0x73f94000 0x4000>;
interrupts = <60>;
clocks = <&clks 0>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
@ -291,14 +318,14 @@
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
clocks = <&clks 0>;
clocks = <&clks IMX5_CLK_DUMMY>;
};
wdog2: wdog@73f9c000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f9c000 0x4000>;
interrupts = <59>;
clocks = <&clks 0>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
@ -306,7 +333,8 @@
compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
reg = <0x73fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks 36>, <&clks 41>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@ -319,7 +347,8 @@
#pwm-cells = <2>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks 37>, <&clks 38>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@ -328,7 +357,8 @@
#pwm-cells = <2>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks 39>, <&clks 40>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@ -337,7 +367,8 @@
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks 28>, <&clks 29>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -346,7 +377,8 @@
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks 30>, <&clks 31>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -376,14 +408,14 @@
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
clocks = <&clks 107>;
clocks = <&clks IMX5_CLK_IIM_GATE>;
};
owire: owire@83fa4000 {
compatible = "fsl,imx51-owire", "fsl,imx21-owire";
reg = <0x83fa4000 0x4000>;
interrupts = <88>;
clocks = <&clks 159>;
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
status = "disabled";
};
@ -393,7 +425,8 @@
compatible = "fsl,imx51-ecspi";
reg = <0x83fac000 0x4000>;
interrupts = <37>;
clocks = <&clks 53>, <&clks 54>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -402,7 +435,8 @@
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks 56>, <&clks 56>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
@ -414,7 +448,8 @@
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
reg = <0x83fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks 55>, <&clks 55>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -425,7 +460,7 @@
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks 35>;
clocks = <&clks IMX5_CLK_I2C2_GATE>;
status = "disabled";
};
@ -435,7 +470,7 @@
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc8000 0x4000>;
interrupts = <62>;
clocks = <&clks 34>;
clocks = <&clks IMX5_CLK_I2C1_GATE>;
status = "disabled";
};
@ -443,7 +478,7 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks 48>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
@ -455,6 +490,8 @@
audmux: audmux@83fd0000 {
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
reg = <0x83fd0000 0x4000>;
clocks = <&clks IMX5_CLK_DUMMY>;
clock-names = "audmux";
status = "disabled";
};
@ -463,7 +500,7 @@
#size-cells = <1>;
compatible = "fsl,imx51-weim";
reg = <0x83fda000 0x1000>;
clocks = <&clks 57>;
clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
ranges = <
0 0 0xb0000000 0x08000000
1 0 0xb8000000 0x08000000
@ -479,7 +516,7 @@
compatible = "fsl,imx51-nand";
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
interrupts = <8>;
clocks = <&clks 60>;
clocks = <&clks IMX5_CLK_NFC_GATE>;
status = "disabled";
};
@ -487,7 +524,7 @@
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks 172>;
clocks = <&clks IMX5_CLK_PATA_GATE>;
status = "disabled";
};
@ -495,7 +532,7 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>;
interrupts = <96>;
clocks = <&clks 50>;
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
dmas = <&sdma 46 0 0>,
<&sdma 47 0 0>;
dma-names = "rx", "tx";
@ -508,336 +545,12 @@
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
};
};
};
&iomuxc {
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>;
};
};
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
>;
};
pinctrl_fec_2: fecgrp-2 {
fsl,pins = <
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
>;
};
};
ecspi2 {
pinctrl_ecspi2_1: ecspi2grp-1 {
fsl,pins = <
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
>;
};
};
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
>;
};
pinctrl_i2c2_2: i2c2grp-2 {
fsl,pins = <
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
>;
};
pinctrl_i2c2_3: i2c2grp-3 {
fsl,pins = <
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
>;
};
};
ipu_disp1 {
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
>;
};
};
ipu_disp2 {
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
fsl,pins = <
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
>;
};
};
kpp {
pinctrl_kpp_1: kppgrp-1 {
fsl,pins = <
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
>;
};
};
pata {
pinctrl_pata_1: patagrp-1 {
fsl,pins = <
MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
>;
};
pinctrl_uart1_rtscts_1: uart1rtscts-1 {
fsl,pins = <
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
>;
};
};
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
>;
};
pinctrl_uart3_rtscts_1: uart3rtscts-1 {
fsl,pins = <
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
>;
};
};
usbh1 {
pinctrl_usbh1_1: usbh1grp-1 {
fsl,pins = <
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
>;
};
};
usbh2 {
pinctrl_usbh2_1: usbh2grp-1 {
fsl,pins = <
MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
MX51_PAD_EIM_A26__USBH2_STP 0x1e5
>;
};
};
};

33
arch/arm/boot/dts/imx53-ard.dts
View File

@ -49,9 +49,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: 3p3v {
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -99,7 +102,7 @@
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_2>;
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
@ -109,7 +112,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx53-ard {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_1__GPIO1_1 0x80000000
@ -148,11 +151,33 @@
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};

126
arch/arm/boot/dts/imx53-evk.dts
View File

@ -1,126 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53.dtsi"
/ {
model = "Freescale i.MX53 Evaluation Kit";
compatible = "fsl,imx53-evk", "fsl,imx53";
memory {
reg = <0x70000000 0x80000000>;
};
leds {
compatible = "gpio-leds";
green {
label = "Heartbeat";
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio3 14 0>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
MX53_PAD_EIM_D19__GPIO3_19 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
pmic: mc13892@08 {
compatible = "fsl,mc13892", "fsl,mc13xxx";
reg = <0x08>;
};
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};

233
arch/arm/boot/dts/imx53-m53evk.dts
View File

@ -26,7 +26,7 @@
crtcs = <&ipu 1>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
pinctrl-0 = <&pinctrl_ipu_disp1>;
display-timings {
800x480p60 {
@ -51,6 +51,7 @@
pwms = <&pwm1 0 3000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&reg_backlight>;
};
leds {
@ -73,14 +74,37 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p2v: 3p2v {
reg_3p2v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_backlight: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "lcd-supply";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_usbh1_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 0>;
enable-active-low;
};
};
sound {
@ -102,25 +126,25 @@
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_2>;
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_3>;
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2_1>;
pinctrl-0 = <&pinctrl_can2>;
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
@ -128,14 +152,14 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_2>;
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
sgtl5000: codec@0a {
@ -143,13 +167,13 @@
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks 150>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_2>;
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <400000>;
status = "okay";
@ -193,7 +217,7 @@
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_1>;
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
@ -201,14 +225,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx53-m53evk {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
MX53_PAD_GPIO_2__GPIO1_2 0x80000000
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
>;
};
@ -218,12 +242,168 @@
MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
>;
};
pinctrl_ipu_disp1: ipudisp1grp {
fsl,pins = <
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
>;
};
pinctrl_nand: nandgrp {
fsl,pins = <
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
>;
};
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_1>;
pinctrl-0 = <&pinctrl_nand>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
@ -231,7 +411,11 @@
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1_1>;
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&sata {
status = "okay";
};
@ -242,18 +426,29 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usbh1_vbus>;
phy_type = "utmi";
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};

40
arch/arm/boot/dts/imx53-mba53.dts
View File

@ -17,14 +17,6 @@
model = "TQ MBa53 starter kit";
compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
reg_backlight: fixed@0 {
compatible = "regulator-fixed";
regulator-name = "lcd-supply";
gpio = <&gpio2 5 0>;
startup-delay-us = <5000>;
enable-active-low;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 50000>;
@ -43,12 +35,28 @@
status = "disabled";
};
reg_3p2v: 3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_backlight: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "lcd-supply";
gpio = <&gpio2 5 0>;
startup-delay-us = <5000>;
enable-active-low;
};
reg_3p2v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
};
sound {
@ -148,14 +156,14 @@
&audmux {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
pinctrl-0 = <&pinctrl_audmux>;
};
&i2c2 {
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 150>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
};

336
arch/arm/boot/dts/imx53-qsb-common.dtsi Normal file
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@ -0,0 +1,336 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx53.dtsi"
/ {
memory {
reg = <0x70000000 0x40000000>;
};
display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0>;
status = "disabled";
display-timings {
claawvga {
native-mode;
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio1 8 0>;
linux,code = <116>; /* KEY_POWER */
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 14 0>;
linux,code = <115>; /* KEY_VOLUMEUP */
gpio-key,wakeup;
};
volume-down {
label = "Volume Down";
gpios = <&gpio2 15 0>;
linux,code = <114>; /* KEY_VOLUMEDOWN */
gpio-key,wakeup;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio7_7>;
user {
label = "Heartbeat";
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p2v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_usb_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio7 8 0>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx53-qsb-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-qsb-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
bus-width = <8>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx53-qsb {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
>;
};
led_pin_gpio7_7: led_gpio7_7@0 {
fsl,pins = <
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_esdhc3: esdhc3grp {
fsl,pins = <
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_ipu_disp0: ipudisp0grp {
fsl,pins = <
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
&sata {
status = "okay";
};
&vpu {
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
phy_type = "utmi";
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};

210
arch/arm/boot/dts/imx53-qsb.dts
View File

@ -11,193 +11,14 @@
*/
/dts-v1/;
#include "imx53.dtsi"
#include "imx53-qsb-common.dtsi"
/ {
model = "Freescale i.MX53 Quick Start Board";
compatible = "fsl,imx53-qsb", "fsl,imx53";
memory {
reg = <0x70000000 0x40000000>;
};
display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0_1>;
status = "disabled";
display-timings {
claawvga {
native-mode;
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio1 8 0>;
linux,code = <116>; /* KEY_POWER */
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 14 0>;
linux,code = <115>; /* KEY_VOLUMEUP */
gpio-key,wakeup;
};
volume-down {
label = "Volume Down";
gpios = <&gpio2 15 0>;
linux,code = <114>; /* KEY_VOLUMEDOWN */
gpio-key,wakeup;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio7_7>;
user {
label = "Heartbeat";
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
reg_3p2v: 3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_usb_vbus: usb_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio7 8 0>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx53-qsb-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-qsb-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
bus-width = <8>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
>;
};
led_pin_gpio7_7: led_gpio7_7@0 {
fsl,pins = <
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks 150>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
pmic: dialog@48 {
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
@ -292,32 +113,3 @@
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
&vpu {
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
phy_type = "utmi";
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};

158
arch/arm/boot/dts/imx53-qsrb.dts Normal file
View File

@ -0,0 +1,158 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53-qsb-common.dtsi"
/ {
model = "Freescale i.MX53 Quick Start-R Board";
compatible = "fsl,imx53-qsrb", "fsl,imx53";
};
&iomuxc {
i2c1 {
/* open drain */
pinctrl_i2c1_qsrb: i2c1grp-1 {
fsl,pins = <
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
>;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_qsrb>;
status = "okay";
pmic: mc34708@8 {
compatible = "fsl,mc34708";
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <23 0x8>;
regulators {
sw1_reg: sw1a {
regulator-name = "SW1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1437500>;
regulator-boot-on;
regulator-always-on;
};
sw1b_reg: sw1b {
regulator-name = "SW1B";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1437500>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-name = "SW2";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1437500>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-name = "SW3";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1425000>;
regulator-boot-on;
};
sw4a_reg: sw4a {
regulator-name = "SW4A";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw4b_reg: sw4b {
regulator-name = "SW4B";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw5_reg: sw5 {
regulator-name = "SW5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-name = "SWBST";
regulator-boot-on;
regulator-always-on;
};
vpll_reg: vpll {
regulator-name = "VPLL";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
vrefddr_reg: vrefddr {
regulator-name = "VREFDDR";
regulator-boot-on;
regulator-always-on;
};
vusb_reg: vusb {
regulator-name = "VUSB";
regulator-boot-on;
regulator-always-on;
};
vusb2_reg: vusb2 {
regulator-name = "VUSB2";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vdac_reg: vdac {
regulator-name = "VDAC";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2775000>;
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-name = "VGEN1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1550000>;
regulator-boot-on;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-name = "VGEN2";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};

119
arch/arm/boot/dts/imx53-smd.dts
View File

@ -40,7 +40,7 @@
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio4 11 0>;
status = "okay";
@ -48,21 +48,21 @@
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
pinctrl-0 = <&pinctrl_esdhc2>;
non-removable;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
@ -95,7 +95,7 @@
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
pinctrl-0 = <&pinctrl_esdhc3>;
non-removable;
status = "okay";
};
@ -104,7 +104,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx53-smd {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
@ -116,24 +116,121 @@
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
>;
};
pinctrl_esdhc3: esdhc3grp {
fsl,pins = <
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
codec: sgtl5000@0a {
@ -154,7 +251,7 @@
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
accelerometer: mma8450@1c {
@ -175,7 +272,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";

175
arch/arm/boot/dts/imx53-tqma53.dtsi
View File

@ -22,9 +22,12 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: 3p3v {
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -35,8 +38,8 @@
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>,
<&pinctrl_tqma53_esdhc2_2>;
pinctrl-0 = <&pinctrl_esdhc2>,
<&pinctrl_esdhc2_cdwp>;
vmmc-supply = <&reg_3p3v>;
wp-gpios = <&gpio1 2 0>;
cd-gpios = <&gpio1 4 0>;
@ -45,13 +48,13 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_2>;
pinctrl-0 = <&pinctrl_uart3>;
status = "disabled";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <4>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
<&gpio3 24 0>, <&gpio3 25 0>;
@ -60,7 +63,7 @@
&esdhc3 { /* EMMC */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
pinctrl-0 = <&pinctrl_esdhc3>;
vmmc-supply = <&reg_3p3v>;
non-removable;
bus-width = <8>;
@ -71,27 +74,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
esdhc2_2 {
pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
fsl,pins = <
MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
>;
};
};
i2s {
pinctrl_i2s_1: i2s-grp1 {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */
>;
};
};
hog {
imx53-tqma53 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
@ -107,43 +90,165 @@
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
>;
};
pinctrl_cspi: cspigrp {
fsl,pins = <
MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
>;
};
pinctrl_esdhc2_cdwp: esdhc2cdwp {
fsl,pins = <
MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
>;
};
pinctrl_esdhc3: esdhc3grp {
fsl,pins = <
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_2>;
pinctrl-0 = <&pinctrl_can1>;
status = "disabled";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2_1>;
pinctrl-0 = <&pinctrl_can2>;
status = "disabled";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_1>;
pinctrl-0 = <&pinctrl_i2c3>;
status = "disabled";
};
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi_1>;
pinctrl-0 = <&pinctrl_cspi>;
fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
<&gpio1 21 0>;
@ -152,7 +257,7 @@
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: mc34708@8 {
@ -177,7 +282,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
status = "disabled";
};

315
arch/arm/boot/dts/imx53-tx53-x03x.dts Normal file
View File

@ -0,0 +1,315 @@
/*
* Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53-tx53.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Ka-Ro electronics TX53 module (LCD)";
compatible = "karo,tx53", "fsl,imx53";
aliases {
display = &display;
};
soc {
display: display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgb24_vga1>;
status = "okay";
display-timings {
VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_3v3>;
brightness-levels = <
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100
>;
default-brightness-level = <50>;
};
regulators {
reg_lcd_pwr: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "LCD POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
reg_lcd_reset: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "LCD RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_2v5>;
VDDIO-supply = <&reg_3v3>;
clocks = <&mclk>;
};
polytouch: edt-ft5x06@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
interrupt-parent = <&gpio6>;
interrupts = <15 0>;
reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
};
touchscreen: tsc2007@48 {
compatible = "ti,tsc2007";
reg = <0x48>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc2007>;
interrupt-parent = <&gpio3>;
interrupts = <26 0>;
gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
ti,x-plate-ohms = <660>;
linux,wakeup;
};
};
&iomuxc {
imx53-tx53-x03x {
pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
fsl,pins = <
MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */
MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */
MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX53_PAD_GPIO_9__KPP_COL_6 0x1f4
MX53_PAD_GPIO_4__KPP_COL_7 0x1f4
MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4
MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4
MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4
MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4
MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4
MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4
>;
};
pinctrl_rgb24_vga1: rgb24-vgagrp1 {
fsl,pins = <
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
};
pinctrl_tsc2007: tsc2007grp {
fsl,pins = <
MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */
>;
};
};
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
/* sample keymap */
/* row/col 0,1 are mapped to KPP row/col 6,7 */
linux,keymap = <
MATRIX_KEY(6, 6, KEY_POWER)
MATRIX_KEY(6, 7, KEY_KP0)
MATRIX_KEY(6, 2, KEY_KP1)
MATRIX_KEY(6, 3, KEY_KP2)
MATRIX_KEY(7, 6, KEY_KP3)
MATRIX_KEY(7, 7, KEY_KP4)
MATRIX_KEY(7, 2, KEY_KP5)
MATRIX_KEY(7, 3, KEY_KP6)
MATRIX_KEY(2, 6, KEY_KP7)
MATRIX_KEY(2, 7, KEY_KP8)
MATRIX_KEY(2, 2, KEY_KP9)
>;
status = "okay";
};

243
arch/arm/boot/dts/imx53-tx53-x13x.dts Normal file
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@ -0,0 +1,243 @@
/*
* Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53-tx53.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Ka-Ro electronics TX53 module (LVDS)";
compatible = "karo,tx53", "fsl,imx53";
aliases {
display = &lvds0;
lvds0 = &lvds0;
lvds1 = &lvds1;
};
backlight0: backlight0 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 0>;
power-supply = <&reg_3v3>;
brightness-levels = <
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100
>;
default-brightness-level = <50>;
};
backlight1: backlight1 {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500000 0>;
power-supply = <&reg_3v3>;
brightness-levels = <
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100
>;
default-brightness-level = <50>;
};
regulators {
reg_lcd_pwr0: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "LVDS0 POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
reg_lcd_pwr1: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "LVDS1 POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
touchscreen2: eeti@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eeti2>;
interrupt-parent = <&gpio3>;
interrupts = <23 0>;
wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
linux,wakeup;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_2v5>;
VDDIO-supply = <&reg_3v3>;
clocks = <&mclk>;
};
touchscreen1: eeti@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eeti1>;
interrupt-parent = <&gpio3>;
interrupts = <22 0>;
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
linux,wakeup;
};
};
&iomuxc {
imx53-tx53-x13x {
pinctrl_i2c2: i2c2-grp1 {
fsl,pins = <
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_lvds0: lvds0grp {
fsl,pins = <
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
>;
};
pinctrl_lvds1: lvds1grp {
fsl,pins = <
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>;
};
pinctrl_eeti1: eeti1grp {
fsl,pins = <
MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */
>;
};
pinctrl_eeti2: eeti2grp {
fsl,pins = <
MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */
>;
};
};
};
&ldb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>;
status = "okay";
lvds0: lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
status = "okay";
display-timings {
native-mode = <&lvds_timing0>;
lvds_timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hsync-len = <60>;
hfront-porch = <40>;
vback-porch = <21>;
vsync-len = <10>;
vfront-porch = <7>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
lvds1: lvds-channel@1 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
status = "okay";
display-timings {
native-mode = <&lvds_timing1>;
lvds_timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hsync-len = <60>;
hfront-porch = <40>;
vback-porch = <21>;
vsync-len = <10>;
vfront-porch = <7>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
};
&sata {
status = "okay";
};

511
arch/arm/boot/dts/imx53-tx53.dtsi
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@ -1,122 +1,551 @@
/*
* Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
* Copyright 2012 <LW@KARO-electronics.de>
* based on imx53-qsb.dts
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "imx53.dtsi"
#include "imx53.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Ka-Ro TX53";
model = "Ka-Ro electronics TX53 module";
compatible = "karo,tx53", "fsl,imx53";
memory {
reg = <0x70000000 0x40000000>; /* Up to 1GiB */
aliases {
can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
can1 = &can1;
ipu = &ipu;
reg_can_xcvr = &reg_can_xcvr;
usbh1 = &usbh1;
usbotg = &usbotg;
};
clocks {
ckih1 {
clock-frequency = <0>;
};
mclk: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_key>;
power {
label = "Power Button";
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_stk5led>;
user {
label = "Heartbeat";
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: 3p3v {
reg_2v5: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "3P3V";
reg = <0>;
regulator-name = "2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_3v3: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_can_xcvr: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_xcvr>;
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
enable-active-low;
};
reg_usbh1_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "usbh1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1_vbus>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg_vbus: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "usbotg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_vbus>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound {
compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000";
model = "tx53-audio-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
/* '1' based port numbers according to datasheet names */
mux-int-port = <1>;
mux-ext-port = <5>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssi1>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_2>;
status = "disabled";
pinctrl-0 = <&pinctrl_can1>;
xceiver-supply = <&reg_can_xcvr>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2_1>;
status = "disabled";
pinctrl-0 = <&pinctrl_can2>;
xceiver-supply = <&reg_can_xcvr>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_2>;
status = "disabled";
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <2>;
status = "okay";
cs-gpios = <
&gpio2 30 GPIO_ACTIVE_HIGH
&gpio3 19 GPIO_ACTIVE_HIGH
>;
spidev0: spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <54000000>;
};
spidev1: spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <54000000>;
};
};
&esdhc1 {
cd-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
fsl,wp-controller;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_2>;
status = "disabled";
pinctrl-0 = <&pinctrl_esdhc1>;
status = "okay";
};
&esdhc2 {
cd-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
fsl,wp-controller;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
status = "disabled";
pinctrl-0 = <&pinctrl_esdhc2>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
status = "disabled";
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
phy-handle = <&phy0>;
mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
status = "okay";
phy0: ethernet-phy@0 {
interrupt-parent = <&gpio2>;
interrupts = <4>;
device_type = "ethernet-phy";
};
};
&i2c3 {
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_2>;
status = "disabled";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
rtc1: ds1339@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ds1339>;
interrupt-parent = <&gpio4>;
interrupts = <20 0>;
};
};
&owire {
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_owire_1>;
status = "disabled";
pinctrl-0 = <&pinctrl_hog>;
imx53-tx53 {
pinctrl_hog: hoggrp {
/* pins not in use by any device on the Starterkit board series */
fsl,pins = <
/* CMOS Sensor Interface */
MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4
MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4
MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4
MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4
MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4
MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4
MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4
MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4
MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4
MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4
MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4
MX53_PAD_GPIO_0__GPIO1_0 0x1f4
/* Module Specific Signal */
/* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */
/* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */
MX53_PAD_EIM_D29__GPIO3_29 0x1f4
MX53_PAD_EIM_EB3__GPIO2_31 0x1f4
/* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */
/* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */
MX53_PAD_EIM_A19__GPIO2_19 0x1f4
MX53_PAD_EIM_A20__GPIO2_18 0x1f4
MX53_PAD_EIM_A21__GPIO2_17 0x1f4
MX53_PAD_EIM_A22__GPIO2_16 0x1f4
MX53_PAD_EIM_A23__GPIO6_6 0x1f4
MX53_PAD_EIM_A24__GPIO5_4 0x1f4
MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4
MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4
MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4
MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4
/* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */
/* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */
MX53_PAD_GPIO_13__GPIO4_3 0x1f4
MX53_PAD_EIM_CS0__GPIO2_23 0x1f4
MX53_PAD_EIM_CS1__GPIO2_24 0x1f4
MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4
MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4
MX53_PAD_EIM_EB0__GPIO2_28 0x1f4
MX53_PAD_EIM_EB1__GPIO2_29 0x1f4
MX53_PAD_EIM_OE__GPIO2_25 0x1f4
MX53_PAD_EIM_LBA__GPIO2_27 0x1f4
MX53_PAD_EIM_RW__GPIO2_26 0x1f4
MX53_PAD_EIM_DA8__GPIO3_8 0x1f4
MX53_PAD_EIM_DA9__GPIO3_9 0x1f4
MX53_PAD_EIM_DA10__GPIO3_10 0x1f4
MX53_PAD_EIM_DA11__GPIO3_11 0x1f4
MX53_PAD_EIM_DA12__GPIO3_12 0x1f4
MX53_PAD_EIM_DA13__GPIO3_13 0x1f4
MX53_PAD_EIM_DA14__GPIO3_14 0x1f4
MX53_PAD_EIM_DA15__GPIO3_15 0x1f4
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
>;
};
pinctrl_can_xcvr: can-xcvrgrp {
fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */
};
pinctrl_ds1339: ds1339grp {
fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
MX53_PAD_EIM_D24__GPIO3_24 0x1f0
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
MX53_PAD_EIM_D25__GPIO3_25 0x1f0
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
pinctrl_gpio_key: gpio-keygrp {
fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
>;
};
pinctrl_nand: nandgrp {
fsl,pins = <
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
>;
};
pinctrl_ssi1: ssi1grp {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
pinctrl_ssi2: ssi2grp {
fsl,pins = <
MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
MX53_PAD_EIM_D27__GPIO3_27 0x1f0
>;
};
pinctrl_stk5led: stk5ledgrp {
fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */
>;
};
pinctrl_usbh1_vbus: usbh1-vbusgrp {
fsl,pins = <
MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */
>;
};
pinctrl_usbotg_vbus: usbotg-vbusgrp {
fsl,pins = <
MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */
MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */
>;
};
};
};
&ipu {
status = "okay";
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2_1>;
status = "disabled";
pinctrl-0 = <&pinctrl_pwm2>;
#pwm-cells = <3>;
};
&sdma {
fsl,sdma-ram-script-name = "sdma-imx53.bin";
};
&ssi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "disabled";
fsl,mode = "i2s-slave";
codec-handle = <&sgtl5000>;
status = "okay";
};
&ssi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_2>;
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>,
<&pinctrl_uart1_3>;
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "disabled";
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_2>;
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "disabled";
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "disabled";
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
phy_type = "utmi";
disable-over-current;
vbus-supply = <&reg_usbh1_vbus>;
status = "okay";
};
&usbotg {
phy_type = "utmi";
dr_mode = "peripheral";
disable-over-current;
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};

159
arch/arm/boot/dts/imx53-voipac-bsb.dts Normal file
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@ -0,0 +1,159 @@
/*
* Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53-voipac-dmm-668.dtsi"
/ {
sound {
compatible = "fsl,imx53-voipac-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-voipac-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio>;
led1 {
label = "led-red";
gpios = <&gpio3 29 0>;
default-state = "off";
};
led2 {
label = "led-orange";
gpios = <&gpio2 31 0>;
default-state = "off";
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx53-voipac {
pinctrl_hog: hoggrp {
fsl,pins = <
/* SD2_CD */
MX53_PAD_EIM_D25__GPIO3_25 0x80000000
/* SD2_WP */
MX53_PAD_EIM_A19__GPIO2_19 0x80000000
>;
};
led_pin_gpio: led_gpio {
fsl,pins = <
MX53_PAD_EIM_D29__GPIO3_29 0x80000000
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
>;
};
/* Keyboard controller */
pinctrl_kpp_1: kppgrp-1 {
fsl,pins = <
MX53_PAD_GPIO_9__KPP_COL_6 0xe8
MX53_PAD_GPIO_4__KPP_COL_7 0xe8
MX53_PAD_KEY_COL2__KPP_COL_2 0xe8
MX53_PAD_KEY_COL3__KPP_COL_3 0xe8
MX53_PAD_KEY_COL4__KPP_COL_4 0xe8
MX53_PAD_GPIO_2__KPP_ROW_6 0xe0
MX53_PAD_GPIO_5__KPP_ROW_7 0xe0
MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0
MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0
MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
>;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio3 25 0>;
wp-gpios = <&gpio2 19 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&clks 150>;
};
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp_1>;
linux,keymap = <
0x0203003b /* KEY_F1 */
0x0603003c /* KEY_F2 */
0x0207003d /* KEY_F3 */
0x0607003e /* KEY_F4 */
>;
keypad,num-rows = <8>;
keypad,num-columns = <1>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};

277
arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi Normal file
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@ -0,0 +1,277 @@
/*
* Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx53.dtsi"
/ {
model = "Voipac i.MX53 X53-DMM-668";
compatible = "voipac,imx53-dmm-668", "fsl,imx53";
memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x20000000>;
};
memory@b0000000 {
device_type = "memory";
reg = <0xb0000000 0x20000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 31 0>; /* PEN */
enable-active-high;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx53-voipac {
pinctrl_hog: hoggrp {
fsl,pins = <
/* Make DA9053 regulator functional */
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
/* FEC Power enable */
MX53_PAD_GPIO_11__GPIO4_1 0x80000000
/* FEC RST */
MX53_PAD_GPIO_12__GPIO4_2 0x80000000
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
>;
};
pinctrl_nand: nandgrp {
fsl,pins = <
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
>;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <4>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 2 0>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: dialog@48 {
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
interrupt-parent = <&gpio7>;
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
regulators {
buck1_reg: buck1 {
regulator-name = "BUCKCORE";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-name = "BUCKPRO";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
buck3_reg: buck3 {
regulator-name = "BUCKMEM";
regulator-min-microvolt = <1420000>;
regulator-max-microvolt = <1580000>;
regulator-always-on;
};
buck4_reg: buck4 {
regulator-name = "BUCKPERI";
regulator-min-microvolt = <2370000>;
regulator-max-microvolt = <2630000>;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-name = "ldo1_1v3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-name = "ldo2_1v3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-name = "ldo3_3v3";
regulator-min-microvolt = <3250000>;
regulator-max-microvolt = <3350000>;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-name = "ldo4_2v775";
regulator-min-microvolt = <2770000>;
regulator-max-microvolt = <2780000>;
regulator-always-on;
};
ldo5_reg: ldo5 {
regulator-name = "ldo5_3v3";
regulator-min-microvolt = <3250000>;
regulator-max-microvolt = <3350000>;
regulator-always-on;
};
ldo6_reg: ldo6 {
regulator-name = "ldo6_1v3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
ldo7_reg: ldo7 {
regulator-name = "ldo7_2v75";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo8_reg: ldo8 {
regulator-name = "ldo8_1v8";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <1850000>;
regulator-always-on;
};
ldo9_reg: ldo9 {
regulator-name = "ldo9_1v5";
regulator-min-microvolt = <1450000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
ldo10_reg: ldo10 {
regulator-name = "ldo10_1v3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
};
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
phy_type = "utmi";
status = "okay";
};

663
arch/arm/boot/dts/imx53.dtsi
View File

@ -12,6 +12,9 @@
#include "skeleton.dtsi"
#include "imx53-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
@ -25,6 +28,10 @@
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
mmc3 = &esdhc4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
@ -84,12 +91,25 @@
interrupt-parent = <&tzic>;
ranges;
sata: sata@10000000 {
compatible = "fsl,imx53-ahci";
reg = <0x10000000 0x1000>;
interrupts = <28>;
clocks = <&clks IMX5_CLK_SATA_GATE>,
<&clks IMX5_CLK_SATA_REF>,
<&clks IMX5_CLK_AHB>;
clock-names = "sata_gate", "sata_ref", "ahb";
status = "disabled";
};
ipu: ipu@18000000 {
#crtc-cells = <1>;
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
};
@ -112,7 +132,9 @@
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -122,7 +144,9 @@
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -132,7 +156,8 @@
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks 32>, <&clks 33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -143,16 +168,19 @@
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks 51>, <&clks 52>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
ssi2: ssi@50014000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
compatible = "fsl,imx53-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x50014000 0x4000>;
interrupts = <30>;
clocks = <&clks 49>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
@ -165,7 +193,9 @@
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -175,7 +205,9 @@
compatible = "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -184,14 +216,14 @@
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
clocks = <&clks 124>;
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
clock-names = "main_clk";
status = "okay";
};
usbphy1: usbphy@1 {
compatible = "usb-nop-xceiv";
clocks = <&clks 125>;
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
clock-names = "main_clk";
status = "okay";
};
@ -200,7 +232,7 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
@ -210,7 +242,7 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
status = "disabled";
@ -220,7 +252,7 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80400 0x0200>;
interrupts = <16>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
@ -229,7 +261,7 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80600 0x0200>;
interrupts = <17>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
status = "disabled";
};
@ -238,7 +270,7 @@
#index-cells = <1>;
compatible = "fsl,imx53-usbmisc";
reg = <0x53f80800 0x200>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
};
gpio1: gpio@53f84000 {
@ -281,18 +313,26 @@
#interrupt-cells = <2>;
};
kpp: kpp@53f94000 {
compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
reg = <0x53f94000 0x4000>;
interrupts = <60>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
wdog1: wdog@53f98000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
clocks = <&clks 0>;
clocks = <&clks IMX5_CLK_DUMMY>;
};
wdog2: wdog@53f9c000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f9c000 0x4000>;
interrupts = <59>;
clocks = <&clks 0>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
@ -300,521 +340,14 @@
compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
reg = <0x53fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks 36>, <&clks 41>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
iomuxc: iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
pinctrl_audmux_2: audmuxgrp-2 {
fsl,pins = <
MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
>;
};
pinctrl_audmux_3: audmuxgrp-3 {
fsl,pins = <
MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
>;
};
};
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
pinctrl_fec_2: fecgrp-2 {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
>;
};
};
csi {
pinctrl_csi_1: csigrp-1 {
fsl,pins = <
MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
>;
};
pinctrl_csi_2: csigrp-2 {
fsl,pins = <
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
>;
};
};
cspi {
pinctrl_cspi_1: cspigrp-1 {
fsl,pins = <
MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
>;
};
pinctrl_cspi_2: cspigrp-2 {
fsl,pins = <
MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
>;
};
pinctrl_ecspi1_2: ecspi1grp-2 {
fsl,pins = <
MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
>;
};
};
ecspi2 {
pinctrl_ecspi2_1: ecspi2grp-1 {
fsl,pins = <
MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_esdhc1_2: esdhc1grp-2 {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
};
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
>;
};
};
esdhc3 {
pinctrl_esdhc3_1: esdhc3grp-1 {
fsl,pins = <
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
>;
};
};
can1 {
pinctrl_can1_1: can1grp-1 {
fsl,pins = <
MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
>;
};
pinctrl_can1_2: can1grp-2 {
fsl,pins = <
MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
>;
};
pinctrl_can1_3: can1grp-3 {
fsl,pins = <
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
>;
};
};
can2 {
pinctrl_can2_1: can2grp-1 {
fsl,pins = <
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_i2c2_2: i2c2grp-2 {
fsl,pins = <
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
>;
};
};
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
>;
};
};
ipu_disp0 {
pinctrl_ipu_disp0_1: ipudisp0grp-1 {
fsl,pins = <
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
};
};
ipu_disp1 {
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
fsl,pins = <
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
>;
};
};
ipu_disp2 {
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
fsl,pins = <
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
>;
};
};
nand {
pinctrl_nand_1: nandgrp-1 {
fsl,pins = <
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
>;
};
};
owire {
pinctrl_owire_1: owiregrp-1 {
fsl,pins = <
MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
>;
};
};
pwm1 {
pinctrl_pwm1_1: pwm1grp-1 {
fsl,pins = <
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
>;
};
};
pwm2 {
pinctrl_pwm2_1: pwm2grp-1 {
fsl,pins = <
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
>;
};
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
>;
};
pinctrl_uart1_3: uart1grp-3 {
fsl,pins = <
MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
>;
};
pinctrl_uart2_2: uart2grp-2 {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
>;
};
};
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
>;
};
};
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
>;
};
};
uart5 {
pinctrl_uart5_1: uart5grp-1 {
fsl,pins = <
MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
>;
};
};
};
gpr: iomuxc-gpr@53fa8000 {
@ -828,9 +361,12 @@
compatible = "fsl,imx53-ldb";
reg = <0x53fa8008 0x4>;
gpr = <&gpr>;
clocks = <&clks 122>, <&clks 120>,
<&clks 115>, <&clks 116>,
<&clks 123>, <&clks 85>;
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
<&clks IMX5_CLK_LDB_DI1_SEL>,
<&clks IMX5_CLK_IPU_DI0_SEL>,
<&clks IMX5_CLK_IPU_DI1_SEL>,
<&clks IMX5_CLK_LDB_DI0_GATE>,
<&clks IMX5_CLK_LDB_DI1_GATE>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
@ -853,7 +389,8 @@
#pwm-cells = <2>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks 37>, <&clks 38>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@ -862,7 +399,8 @@
#pwm-cells = <2>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks 39>, <&clks 40>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@ -871,7 +409,8 @@
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks 28>, <&clks 29>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -880,7 +419,8 @@
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks 30>, <&clks 31>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -889,7 +429,8 @@
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks 158>, <&clks 157>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -898,7 +439,8 @@
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fcc000 0x4000>;
interrupts = <83>;
clocks = <&clks 87>, <&clks 86>;
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -952,7 +494,7 @@
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
reg = <0x53fec000 0x4000>;
interrupts = <64>;
clocks = <&clks 88>;
clocks = <&clks IMX5_CLK_I2C3_GATE>;
status = "disabled";
};
@ -960,7 +502,8 @@
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks 65>, <&clks 66>;
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
<&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -977,14 +520,15 @@
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
reg = <0x63f98000 0x4000>;
interrupts = <69>;
clocks = <&clks 107>;
clocks = <&clks IMX5_CLK_IIM_GATE>;
};
uart5: serial@63f90000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks 67>, <&clks 68>;
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
<&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -992,7 +536,7 @@
owire: owire@63fa4000 {
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
reg = <0x63fa4000 0x4000>;
clocks = <&clks 159>;
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
status = "disabled";
};
@ -1002,7 +546,8 @@
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks 53>, <&clks 54>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -1011,7 +556,8 @@
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks 56>, <&clks 56>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
@ -1023,7 +569,8 @@
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks 55>, <&clks 55>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -1034,7 +581,7 @@
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
reg = <0x63fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks 35>;
clocks = <&clks IMX5_CLK_I2C2_GATE>;
status = "disabled";
};
@ -1044,15 +591,16 @@
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
reg = <0x63fc8000 0x4000>;
interrupts = <62>;
clocks = <&clks 34>;
clocks = <&clks IMX5_CLK_I2C1_GATE>;
status = "disabled";
};
ssi1: ssi@63fcc000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks 48>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
@ -1071,15 +619,16 @@
compatible = "fsl,imx53-nand";
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
interrupts = <8>;
clocks = <&clks 60>;
clocks = <&clks IMX5_CLK_NFC_GATE>;
status = "disabled";
};
ssi3: ssi@63fe8000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fe8000 0x4000>;
interrupts = <96>;
clocks = <&clks 50>;
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
dmas = <&sdma 46 0 0>,
<&sdma 47 0 0>;
dma-names = "rx", "tx";
@ -1092,7 +641,9 @@
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
@ -1101,7 +652,8 @@
compatible = "fsl,imx53-tve";
reg = <0x63ff0000 0x1000>;
interrupts = <92>;
clocks = <&clks 69>, <&clks 116>;
clocks = <&clks IMX5_CLK_TVE_GATE>,
<&clks IMX5_CLK_IPU_DI1_SEL>;
clock-names = "tve", "di_sel";
crtcs = <&ipu 1>;
status = "disabled";
@ -1111,7 +663,8 @@
compatible = "fsl,imx53-vpu";
reg = <0x63ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks 63>, <&clks 63>;
clocks = <&clks IMX5_CLK_VPU_GATE>,
<&clks IMX5_CLK_VPU_GATE>;
clock-names = "per", "ahb";
iram = <&ocram>;
status = "disabled";
@ -1121,7 +674,7 @@
ocram: sram@f8000000 {
compatible = "mmio-sram";
reg = <0xf8000000 0x20000>;
clocks = <&clks 186>;
clocks = <&clks IMX5_CLK_OCRAM>;
};
};
};

29
arch/arm/boot/dts/vf610-cosmic.dts
View File

@ -36,12 +36,37 @@
&fec1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1_1>;
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&iomuxc {
vf610-cosmic {
pinctrl_fec1: fec1grp {
fsl,pins = <
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
VF610_PAD_PTB4__UART1_TX 0x21a2
VF610_PAD_PTB5__UART1_RX 0x21a1
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};

66
arch/arm/boot/dts/vf610-twr.dts
View File

@ -39,7 +39,7 @@
&dspi0 {
bus-num = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi0_1>;
pinctrl-0 = <&pinctrl_dspi0>;
status = "okay";
sflash: at26df081a@0 {
@ -56,26 +56,82 @@
&fec0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec0_1>;
pinctrl-0 = <&pinctrl_fec0>;
status = "okay";
};
&fec1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1_1>;
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_1>;
pinctrl-0 = <&pinctrl_i2c0>;
status = "okay";
};
&iomuxc {
vf610-twr {
pinctrl_dspi0: dspi0grp {
fsl,pins = <
VF610_PAD_PTB19__DSPI0_CS0 0x1182
VF610_PAD_PTB20__DSPI0_SIN 0x1181
VF610_PAD_PTB21__DSPI0_SOUT 0x1182
VF610_PAD_PTB22__DSPI0_SCK 0x1182
>;
};
pinctrl_fec0: fec0grp {
fsl,pins = <
VF610_PAD_PTA6__RMII_CLKIN 0x30d1
VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};
pinctrl_i2c0: i2c0grp {
fsl,pins = <
VF610_PAD_PTB14__I2C0_SCL 0x30d3
VF610_PAD_PTB15__I2C0_SDA 0x30d3
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
VF610_PAD_PTB4__UART1_TX 0x21a2
VF610_PAD_PTB5__UART1_RX 0x21a1
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};

207
arch/arm/boot/dts/vf610.dtsi
View File

@ -10,6 +10,7 @@
#include "skeleton.dtsi"
#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
@ -90,7 +91,7 @@
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
interrupts = <0 61 0x00>;
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
status = "disabled";
@ -99,7 +100,7 @@
uart1: serial@40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
interrupts = <0 62 0x04>;
interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
status = "disabled";
@ -108,7 +109,7 @@
uart2: serial@40029000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40029000 0x1000>;
interrupts = <0 63 0x04>;
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART2>;
clock-names = "ipg";
status = "disabled";
@ -117,7 +118,7 @@
uart3: serial@4002a000 {
compatible = "fsl,vf610-lpuart";
reg = <0x4002a000 0x1000>;
interrupts = <0 64 0x04>;
interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART3>;
clock-names = "ipg";
status = "disabled";
@ -128,7 +129,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
interrupts = <0 67 0x04>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <5>;
@ -138,7 +139,7 @@
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
interrupts = <0 86 0x04>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI2>;
clock-names = "sai";
status = "disabled";
@ -147,7 +148,7 @@
pit: pit@40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
interrupts = <0 39 0x04>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
@ -164,7 +165,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
interrupts = <0 24 0x04>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_QSPI0_EN>,
<&clks VF610_CLK_QSPI0>;
clock-names = "qspi_en", "qspi";
@ -175,182 +176,12 @@
compatible = "fsl,vf610-iomuxc";
reg = <0x40048000 0x1000>;
#gpio-range-cells = <3>;
/* functions and groups pins */
dcu0 {
pinctrl_dcu0_1: dcu0grp_1 {
fsl,pins = <
VF610_PAD_PTB8__GPIO_30 0x42
VF610_PAD_PTE0__DCU0_HSYNC 0x42
VF610_PAD_PTE1__DCU0_VSYNC 0x42
VF610_PAD_PTE2__DCU0_PCLK 0x42
VF610_PAD_PTE4__DCU0_DE 0x42
VF610_PAD_PTE5__DCU0_R0 0x42
VF610_PAD_PTE6__DCU0_R1 0x42
VF610_PAD_PTE7__DCU0_R2 0x42
VF610_PAD_PTE8__DCU0_R3 0x42
VF610_PAD_PTE9__DCU0_R4 0x42
VF610_PAD_PTE10__DCU0_R5 0x42
VF610_PAD_PTE11__DCU0_R6 0x42
VF610_PAD_PTE12__DCU0_R7 0x42
VF610_PAD_PTE13__DCU0_G0 0x42
VF610_PAD_PTE14__DCU0_G1 0x42
VF610_PAD_PTE15__DCU0_G2 0x42
VF610_PAD_PTE16__DCU0_G3 0x42
VF610_PAD_PTE17__DCU0_G4 0x42
VF610_PAD_PTE18__DCU0_G5 0x42
VF610_PAD_PTE19__DCU0_G6 0x42
VF610_PAD_PTE20__DCU0_G7 0x42
VF610_PAD_PTE21__DCU0_B0 0x42
VF610_PAD_PTE22__DCU0_B1 0x42
VF610_PAD_PTE23__DCU0_B2 0x42
VF610_PAD_PTE24__DCU0_B3 0x42
VF610_PAD_PTE25__DCU0_B4 0x42
VF610_PAD_PTE26__DCU0_B5 0x42
VF610_PAD_PTE27__DCU0_B6 0x42
VF610_PAD_PTE28__DCU0_B7 0x42
>;
};
};
dspi0 {
pinctrl_dspi0_1: dspi0grp_1 {
fsl,pins = <
VF610_PAD_PTB19__DSPI0_CS0 0x1182
VF610_PAD_PTB20__DSPI0_SIN 0x1181
VF610_PAD_PTB21__DSPI0_SOUT 0x1182
VF610_PAD_PTB22__DSPI0_SCK 0x1182
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp_1 {
fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
VF610_PAD_PTA7__GPIO_134 0x219d
>;
};
};
fec0 {
pinctrl_fec0_1: fec0grp_1 {
fsl,pins = <
VF610_PAD_PTA6__RMII_CLKIN 0x30d1
VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
>;
};
};
fec1 {
pinctrl_fec1_1: fec1grp_1 {
fsl,pins = <
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};
};
i2c0 {
pinctrl_i2c0_1: i2c0grp_1 {
fsl,pins = <
VF610_PAD_PTB14__I2C0_SCL 0x30d3
VF610_PAD_PTB15__I2C0_SDA 0x30d3
>;
};
};
pwm0 {
pinctrl_pwm0_1: pwm0grp_1 {
fsl,pins = <
VF610_PAD_PTB0__FTM0_CH0 0x1582
VF610_PAD_PTB1__FTM0_CH1 0x1582
VF610_PAD_PTB2__FTM0_CH2 0x1582
VF610_PAD_PTB3__FTM0_CH3 0x1582
VF610_PAD_PTB6__FTM0_CH6 0x1582
VF610_PAD_PTB7__FTM0_CH7 0x1582
>;
};
};
qspi0 {
pinctrl_qspi0_1: qspi0grp_1 {
fsl,pins = <
VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b
VF610_PAD_PTD1__QSPI0_A_CS0 0x307f
VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073
VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073
VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073
VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b
VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b
VF610_PAD_PTD8__QSPI0_B_CS0 0x307f
VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073
VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073
VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073
VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b
>;
};
};
sai2 {
pinctrl_sai2_1: sai2grp_1 {
fsl,pins = <
VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp_1 {
fsl,pins = <
VF610_PAD_PTB4__UART1_TX 0x21a2
VF610_PAD_PTB5__UART1_RX 0x21a1
>;
};
};
usbvbus {
pinctrl_usbvbus_1: usbvbusgrp_1 {
fsl,pins = <
VF610_PAD_PTA24__USB1_VBUS_EN 0x219c
VF610_PAD_PTA16__USB0_VBUS_EN 0x219c
>;
};
};
};
gpio1: gpio@40049000 {
compatible = "fsl,vf610-gpio";
reg = <0x40049000 0x1000 0x400ff000 0x40>;
interrupts = <0 107 0x04>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -361,7 +192,7 @@
gpio2: gpio@4004a000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
interrupts = <0 108 0x04>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -372,7 +203,7 @@
gpio3: gpio@4004b000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
interrupts = <0 109 0x04>;
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -383,7 +214,7 @@
gpio4: gpio@4004c000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
interrupts = <0 110 0x04>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -394,7 +225,7 @@
gpio5: gpio@4004d000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
interrupts = <0 111 0x04>;
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -412,7 +243,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
interrupts =<0 71 0x04>;
interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
status = "disabled";
@ -435,7 +266,7 @@
uart4: serial@400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
interrupts = <0 65 0x04>;
interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
@ -444,7 +275,7 @@
uart5: serial@400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
interrupts = <0 66 0x04>;
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
@ -453,7 +284,7 @@
fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
interrupts = <0 78 0x04>;
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
@ -464,7 +295,7 @@
fec1: ethernet@400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
interrupts = <0 79 0x04>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;

33
arch/arm/mach-mxs/mach-mxs.c
View File

@ -157,6 +157,8 @@ enum mac_oui {
OUI_FSL,
OUI_DENX,
OUI_CRYSTALFONTZ,
OUI_I2SE,
OUI_ARMADEUS,
};
static void __init update_fec_mac_prop(enum mac_oui oui)
@ -211,6 +213,16 @@ static void __init update_fec_mac_prop(enum mac_oui oui)
macaddr[1] = 0xb9;
macaddr[2] = 0xe1;
break;
case OUI_I2SE:
macaddr[0] = 0x00;
macaddr[1] = 0x01;
macaddr[2] = 0x87;
break;
case OUI_ARMADEUS:
macaddr[0] = 0x00;
macaddr[1] = 0x1e;
macaddr[2] = 0xac;
break;
}
val = ocotp[i];
macaddr[3] = (val >> 16) & 0xff;
@ -236,6 +248,11 @@ static void __init imx28_evk_init(void)
mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
}
static void __init imx28_apf28_init(void)
{
update_fec_mac_prop(OUI_ARMADEUS);
}
static int apx4devkit_phy_fixup(struct phy_device *phy)
{
phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
@ -330,6 +347,11 @@ static void __init crystalfontz_init(void)
update_fec_mac_prop(OUI_CRYSTALFONTZ);
}
static void __init duckbill_init(void)
{
update_fec_mac_prop(OUI_I2SE);
}
static void __init m28cu3_init(void)
{
update_fec_mac_prop(OUI_DENX);
@ -426,6 +448,11 @@ static int __init mxs_restart_init(void)
return 0;
}
static void __init eukrea_mbmx283lc_init(void)
{
mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
}
static void __init mxs_machine_init(void)
{
struct device_node *root;
@ -458,10 +485,16 @@ static void __init mxs_machine_init(void)
if (of_machine_is_compatible("fsl,imx28-evk"))
imx28_evk_init();
if (of_machine_is_compatible("armadeus,imx28-apf28"))
imx28_apf28_init();
else if (of_machine_is_compatible("bluegiga,apx4devkit"))
apx4devkit_init();
else if (of_machine_is_compatible("crystalfontz,cfa10036"))
crystalfontz_init();
else if (of_machine_is_compatible("eukrea,mbmx283lc"))
eukrea_mbmx283lc_init();
else if (of_machine_is_compatible("i2se,duckbill"))
duckbill_init();
else if (of_machine_is_compatible("msr,m28cu3"))
m28cu3_init();