powerpc/mm: Move radix/hash common data structures to book3s64 headers
Start moving code that is generic between radix and hash to book3s64 specific headers from the book3s64 hash specific one. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
33d336d986
commit
11a6f6abd7
@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_MMU_HASH32_H_
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#define _ASM_POWERPC_MMU_HASH32_H_
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#ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
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#define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
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/*
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* 32-bit hash table MMU support
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*/
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@ -90,4 +90,4 @@ typedef struct {
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#define mmu_virtual_psize MMU_PAGE_4K
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#define mmu_linear_psize MMU_PAGE_256M
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#endif /* _ASM_POWERPC_MMU_HASH32_H_ */
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#endif /* _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ */
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_MMU_HASH64_H_
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#define _ASM_POWERPC_MMU_HASH64_H_
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#ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
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#define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
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/*
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* PowerPC64 memory management structures
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*
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@ -127,24 +127,6 @@ extern struct hash_pte *htab_address;
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extern unsigned long htab_size_bytes;
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extern unsigned long htab_hash_mask;
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/*
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* Page size definition
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* sllp : is a bit mask with the value of SLB L || LP to be or'ed
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* directly to a slbmte "vsid" value
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* penc : is the HPTE encoding mask for the "LP" field:
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*
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*/
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struct mmu_psize_def
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{
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unsigned int shift; /* number of bits */
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int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
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unsigned int tlbiel; /* tlbiel supported for that page size */
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unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
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unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
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};
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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static inline int shift_to_mmu_psize(unsigned int shift)
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{
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@ -210,11 +192,6 @@ static inline int segment_shift(int ssize)
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/*
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* The current system page and segment sizes
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*/
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extern int mmu_linear_psize;
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extern int mmu_virtual_psize;
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extern int mmu_vmalloc_psize;
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extern int mmu_vmemmap_psize;
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extern int mmu_io_psize;
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extern int mmu_kernel_ssize;
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extern int mmu_highuser_ssize;
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extern u16 mmu_slb_size;
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@ -512,38 +489,6 @@ static inline void subpage_prot_free(struct mm_struct *mm) {}
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static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
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#endif /* CONFIG_PPC_SUBPAGE_PROT */
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typedef unsigned long mm_context_id_t;
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struct spinlock;
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typedef struct {
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mm_context_id_t id;
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u16 user_psize; /* page size index */
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#ifdef CONFIG_PPC_MM_SLICES
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u64 low_slices_psize; /* SLB page size encodings */
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unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
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#else
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u16 sllp; /* SLB page size encoding */
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#endif
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unsigned long vdso_base;
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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struct subpage_prot_table spt;
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#endif /* CONFIG_PPC_SUBPAGE_PROT */
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#ifdef CONFIG_PPC_ICSWX
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struct spinlock *cop_lockp; /* guard acop and cop_pid */
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unsigned long acop; /* mask of enabled coprocessor types */
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unsigned int cop_pid; /* pid value used with coprocessors */
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#endif /* CONFIG_PPC_ICSWX */
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#ifdef CONFIG_PPC_64K_PAGES
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/* for 4K PTE fragment support */
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void *pte_frag;
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#endif
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#ifdef CONFIG_SPAPR_TCE_IOMMU
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struct list_head iommu_group_mem_list;
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#endif
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} mm_context_t;
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#if 0
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/*
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* The code below is equivalent to this function for arguments
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@ -613,4 +558,4 @@ unsigned htab_shift_for_mem_size(unsigned long mem_size);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
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#endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */
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72
arch/powerpc/include/asm/book3s/64/mmu.h
Normal file
72
arch/powerpc/include/asm/book3s/64/mmu.h
Normal file
@ -0,0 +1,72 @@
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#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
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#define _ASM_POWERPC_BOOK3S_64_MMU_H_
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#ifndef __ASSEMBLY__
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/*
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* Page size definition
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* sllp : is a bit mask with the value of SLB L || LP to be or'ed
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* directly to a slbmte "vsid" value
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* penc : is the HPTE encoding mask for the "LP" field:
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*
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*/
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struct mmu_psize_def {
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unsigned int shift; /* number of bits */
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int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
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unsigned int tlbiel; /* tlbiel supported for that page size */
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unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
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unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
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};
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_PPC_STD_MMU_64
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/* 64-bit classic hash table MMU */
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#include <asm/book3s/64/mmu-hash.h>
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#endif
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#ifndef __ASSEMBLY__
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typedef unsigned long mm_context_id_t;
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struct spinlock;
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typedef struct {
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mm_context_id_t id;
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u16 user_psize; /* page size index */
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#ifdef CONFIG_PPC_MM_SLICES
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u64 low_slices_psize; /* SLB page size encodings */
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unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
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#else
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u16 sllp; /* SLB page size encoding */
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#endif
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unsigned long vdso_base;
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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struct subpage_prot_table spt;
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#endif /* CONFIG_PPC_SUBPAGE_PROT */
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#ifdef CONFIG_PPC_ICSWX
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struct spinlock *cop_lockp; /* guard acop and cop_pid */
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unsigned long acop; /* mask of enabled coprocessor types */
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unsigned int cop_pid; /* pid value used with coprocessors */
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#endif /* CONFIG_PPC_ICSWX */
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#ifdef CONFIG_PPC_64K_PAGES
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/* for 4K PTE fragment support */
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void *pte_frag;
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#endif
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#ifdef CONFIG_SPAPR_TCE_IOMMU
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struct list_head iommu_group_mem_list;
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#endif
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} mm_context_t;
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/*
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* The current system page and segment sizes
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*/
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extern int mmu_linear_psize;
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extern int mmu_virtual_psize;
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extern int mmu_vmalloc_psize;
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extern int mmu_vmemmap_psize;
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extern int mmu_io_psize;
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
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@ -181,10 +181,13 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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#define MMU_PAGE_COUNT 15
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#if defined(CONFIG_PPC_STD_MMU_64)
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/* 64-bit classic hash table MMU */
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#include <asm/book3s/64/mmu-hash.h>
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#elif defined(CONFIG_PPC_STD_MMU_32)
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#ifdef CONFIG_PPC_BOOK3S_64
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#include <asm/book3s/64/mmu.h>
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#else /* CONFIG_PPC_BOOK3S_64 */
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#endif
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#if defined(CONFIG_PPC_STD_MMU_32)
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/* 32-bit classic hash table MMU */
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#include <asm/book3s/32/mmu-hash.h>
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#elif defined(CONFIG_40x)
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