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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Browse Source 
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (106 commits)
  powerpc/p3060qds: Add support for P3060QDS board
  powerpc/83xx: Add shutdown request support to MCU handling on MPC8349 MITX
  powerpc/85xx: Make kexec to interate over online cpus
  powerpc/fsl_booke: Fix comment in head_fsl_booke.S
  powerpc/85xx: issue 15 EOI after core reset for FSL CoreNet devices
  powerpc/8xxx: Fix interrupt handling in MPC8xxx GPIO driver
  powerpc/85xx: Add 'fsl,pq3-gpio' compatiable for GPIO driver
  powerpc/86xx: Correct Gianfar support for GE boards
  powerpc/cpm: Clear muram before it is in use.
  drivers/virt: add ioctl for 32-bit compat on 64-bit to fsl-hv-manager
  powerpc/fsl_msi: add support for "msi-address-64" property
  powerpc/85xx: Setup secondary cores PIR with hard SMP id
  powerpc/fsl-booke: Fix settlbcam for 64-bit
  powerpc/85xx: Adding DCSR node to dtsi device trees
  powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards
  powerpc/85xx: fix PHYS_64BIT selection for P1022DS
  powerpc/fsl-booke: Fix setup_initial_memory_limit to not blindly map
  powerpc: respect mem= setting for early memory limit setup
  powerpc: Update corenet64_smp_defconfig
  powerpc: Update mpc85xx/corenet 32-bit defconfigs
  ...

Fix up trivial conflicts in:
 - arch/powerpc/configs/40x/hcu4_defconfig
	removed stale file, edited elsewhere
 - arch/powerpc/include/asm/udbg.h, arch/powerpc/kernel/udbg.c:
	added opal and gelic drivers vs added ePAPR driver
 - drivers/tty/serial/8250.c
	moved UPIO_TSI to powerpc vs removed UPIO_DWAPB support
This commit is contained in:
Linus Torvalds 2011-11-06 17:12:03 -08:00
commit 1197ab2942
189 changed files with 9410 additions and 979 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
Documentation/devicetree/bindings/powerpc/fsl/board.txt
View File

@ -1,3 +1,8 @@
Freescale Reference Board Bindings
This document describes device tree bindings for various devices that
exist on some Freescale reference boards.
* Board Control and Status (BCSR)
Required properties:
@ -12,25 +17,26 @@ Example:
reg = <f8000000 8000>;
};
* Freescale on board FPGA
* Freescale on-board FPGA
This is the memory-mapped registers for on board FPGA.
Required properities:
- compatible : should be "fsl,fpga-pixis".
- reg : should contain the address and the length of the FPPGA register
set.
- compatible: should be a board-specific string followed by a string
indicating the type of FPGA. Example:
"fsl,<board>-fpga", "fsl,fpga-pixis"
- reg: should contain the address and the length of the FPGA register set.
- interrupt-parent: should specify phandle for the interrupt controller.
- interrupts : should specify event (wakeup) IRQ.
- interrupts: should specify event (wakeup) IRQ.
Example (MPC8610HPCD):
Example (P1022DS):
board-control@e8000000 {
compatible = "fsl,fpga-pixis";
reg = <0xe8000000 32>;
interrupt-parent = <&mpic>;
interrupts = <8 8>;
};
board-control@3,0 {
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
interrupt-parent = <&mpic>;
interrupts = <8 8 0 0>;
};
* Freescale BCSR GPIO banks

395
Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt Normal file
View File

@ -0,0 +1,395 @@
===================================================================
Debug Control and Status Register (DCSR) Binding
Copyright 2011 Freescale Semiconductor Inc.
NOTE: The bindings described in this document are preliminary and subject
to change. Some of the compatible strings that contain only generic names
may turn out to be inappropriate, or need additional properties to describe
the integration of the block with the rest of the chip.
=====================================================================
Debug Control and Status Register Memory Map
Description
This node defines the base address and range for the
defined DCSR Memory Map. Child nodes will describe the individual
debug blocks defined within this memory space.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,dcsr" and "simple-bus".
The DCSR space exists in the memory-mapped bus.
- #address-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
or representing physical addresses in child nodes.
- #size-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
or representing the size of physical addresses in
child nodes.
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
range of the DCSR space.
EXAMPLE
dcsr: dcsr@f00000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,dcsr", "simple-bus";
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
=====================================================================
Event Processing Unit
This node represents the region of DCSR space allocated to the EPU
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,dcsr-epu"
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by the EPU.
The value of the interrupts property consists of three
interrupt specifiers. The format of the specifier is defined
by the binding document describing the node's interrupt parent.
The EPU counters can be configured to assert the performance
monitor interrupt signal based on either counter overflow or value
match. Which counter asserted the interrupt is captured in an EPU
Counter Interrupt Status Register (EPCPUISR).
The EPU unit can also be configured to assert either or both of
two interrupt signals based on debug event sources within the SoC.
The interrupt signals are epu_xt_int0 and epu_xt_int1.
Which event source asserted the interrupt is captured in an EPU
Interrupt Status Register (EPISR0,EPISR1).
Interrupt numbers are lised in order (perfmon, event0, event1).
- interrupt-parent
Usage: required
Value type: <phandle>
Definition: A single <phandle> value that points
to the interrupt parent to which the child domain
is being mapped. Value must be "&mpic"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
EXAMPLE
dcsr-epu@0 {
compatible = "fsl,dcsr-epu";
interrupts = <52 2 0 0
84 2 0 0
85 2 0 0>;
interrupt-parent = <&mpic>;
reg = <0x0 0x1000>;
};
=======================================================================
Nexus Port Controller
This node represents the region of DCSR space allocated to the NPC
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,dcsr-npc"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
The Nexus Port controller occupies two regions in the DCSR space
with distinct functionality.
The first register range describes the Nexus Port Controller
control and status registers.
The second register range describes the Nexus Port Controller
internal trace buffer. The NPC trace buffer is a small memory buffer
which stages the nexus trace data for transmission via the Aurora port
or to a DDR based trace buffer. In some configurations the NPC trace
buffer can be the only trace buffer used.
EXAMPLE
dcsr-npc {
compatible = "fsl,dcsr-npc";
reg = <0x1000 0x1000 0x1000000 0x8000>;
};
=======================================================================
Nexus Concentrator
This node represents the region of DCSR space allocated to the NXC
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,dcsr-nxc"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
EXAMPLE
dcsr-nxc@2000 {
compatible = "fsl,dcsr-nxc";
reg = <0x2000 0x1000>;
};
=======================================================================
CoreNet Debug Controller
This node represents the region of DCSR space allocated to
the CoreNet Debug controller.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,dcsr-corenet"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
The CoreNet Debug controller occupies two regions in the DCSR space
with distinct functionality.
The first register range describes the CoreNet Debug Controller
functionalty to perform transaction and transaction attribute matches.
The second register range describes the CoreNet Debug Controller
functionalty to trigger event notifications and debug traces.
EXAMPLE
dcsr-corenet {
compatible = "fsl,dcsr-corenet";
reg = <0x8000 0x1000 0xB0000 0x1000>;
};
=======================================================================
Data Path Debug controller
This node represents the region of DCSR space allocated to
the DPAA Debug Controller. This controller controls debug configuration
for the QMAN and FMAN blocks.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include both an identifier specific to the SoC
or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
generic compatible string "fsl,dcsr-dpaa".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
EXAMPLE
dcsr-dpaa@9000 {
compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
reg = <0x9000 0x1000>;
};
=======================================================================
OCeaN Debug controller
This node represents the region of DCSR space allocated to
the OCN Debug Controller.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include both an identifier specific to the SoC
or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
generic compatible string "fsl,dcsr-ocn".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
EXAMPLE
dcsr-ocn@11000 {
compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
reg = <0x11000 0x1000>;
};
=======================================================================
DDR Controller Debug controller
This node represents the region of DCSR space allocated to
the OCN Debug Controller.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,dcsr-ddr"
- dev-handle
Usage: required
Definition: A phandle to associate this debug node with its
component controller.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
EXAMPLE
dcsr-ddr@12000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr1>;
reg = <0x12000 0x1000>;
};
=======================================================================
Nexus Aurora Link Controller
This node represents the region of DCSR space allocated to
the NAL Controller.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include both an identifier specific to the SoC
or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
generic compatible string "fsl,dcsr-nal".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
EXAMPLE
dcsr-nal@18000 {
compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
reg = <0x18000 0x1000>;
};
=======================================================================
Run Control and Power Management
This node represents the region of DCSR space allocated to
the RCPM Debug Controller. This functionlity is limited to the
control the debug operations of the SoC and cores.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include both an identifier specific to the SoC
or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
generic compatible string "fsl,dcsr-rcpm".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
EXAMPLE
dcsr-rcpm@22000 {
compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
reg = <0x22000 0x1000>;
};
=======================================================================
Core Service Bridge Proxy
This node represents the region of DCSR space allocated to
the Core Service Bridge Proxies.
There is one Core Service Bridge Proxy device for each CPU in the system.
This functionlity provides access to the debug operations of the CPU.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include both an identifier specific to the cpu
of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
generic compatible string "fsl,dcsr-cpu-sb-proxy".
- cpu-handle
Usage: required
Definition: A phandle to associate this debug node with its cpu.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
offset and length of the DCSR space registers of the device
configuration block.
EXAMPLE
dcsr-cpu-sb-proxy@40000 {
compatible = "fsl,dcsr-e500mc-sb-proxy",
"fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu0>;
reg = <0x40000 0x1000>;
};
dcsr-cpu-sb-proxy@41000 {
compatible = "fsl,dcsr-e500mc-sb-proxy",
"fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x41000 0x1000>;
};
=======================================================================

42
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
View File

@ -25,6 +25,16 @@ Required properties:
are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
to MPIC.
Optional properties:
- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
is used for MSI messaging. The address of MSIIR in PCI address space is
the MSI message address.
This property may be used in virtualized environments where the hypervisor
has created an alternate mapping for the MSIR block. See below for an
explanation.
Example:
msi@41600 {
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
@ -41,3 +51,35 @@ Example:
0xe7 0>;
interrupt-parent = <&mpic>;
};
The Freescale hypervisor and msi-address-64
-------------------------------------------
Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
Freescale MSI driver calculates the address of MSIIR (in the MSI register
block) and sets that address as the MSI message address.
In a virtualized environment, the hypervisor may need to create an IOMMU
mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement
because of hardware limitations of the Peripheral Access Management Unit
(PAMU), which is currently the only IOMMU that the hypervisor supports.
The ATMU is programmed with the guest physical address, and the PAMU
intercepts transactions and reroutes them to the true physical address.
In the PAMU, each PCI controller is given only one primary window. The
PAMU restricts DMA operations so that they can only occur within a window.
Because PCI devices must be able to DMA to memory, the primary window must
be used to cover all of the guest's memory space.
PAMU primary windows can be divided into 256 subwindows, and each
subwindow can have its own address mapping ("guest physical" to "true
physical"). However, each subwindow has to have the same alignment, which
means they cannot be located at just any address. Because of these
restrictions, it is usually impossible to create a 4KB subwindow that
covers MSIIR where it's normally located.
Therefore, the hypervisor has to create a subwindow inside the same
primary window used for memory, but mapped to the MSIR block (where MSIIR
lives). The first subwindow after the end of guest memory is used for
this. The address specified in the msi-address-64 property is the PCI
address of MSIIR. The hypervisor configures the PAMU to map that address to
the true physical address of MSIIR.

7
arch/powerpc/Kconfig
View File

@ -323,7 +323,7 @@ config SWIOTLB
config HOTPLUG_CPU
bool "Support for enabling/disabling CPUs"
depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || PPC_PMAC)
depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || PPC_PMAC || PPC_POWERNV)
---help---
Say Y here to be able to disable and re-enable individual
CPUs at runtime on SMP machines.
@ -345,7 +345,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
config KEXEC
bool "kexec system call (EXPERIMENTAL)"
depends on (PPC_BOOK3S || FSL_BOOKE) && EXPERIMENTAL
depends on (PPC_BOOK3S || FSL_BOOKE || (44x && !SMP && !47x)) && EXPERIMENTAL
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
@ -429,8 +429,7 @@ config ARCH_POPULATES_NODE_MAP
def_bool y
config SYS_SUPPORTS_HUGETLBFS
def_bool y
depends on PPC_BOOK3S_64
bool
source "mm/Kconfig"

46
arch/powerpc/Kconfig.debug
View File

@ -141,9 +141,6 @@ config BOOTX_TEXT
config PPC_EARLY_DEBUG
bool "Early debugging (dangerous)"
# PPC_EARLY_DEBUG on 440 leaves AS=1 mappings above the TLB high water
# mark, which doesn't work with current 440 KVM.
depends on !KVM
help
Say Y to enable some early debugging facilities that may be available
for your processor/board combination. Those facilities are hacks
@ -222,7 +219,9 @@ config PPC_EARLY_DEBUG_BEAT
config PPC_EARLY_DEBUG_44x
bool "Early serial debugging for IBM/AMCC 44x CPUs"
depends on 44x
# PPC_EARLY_DEBUG on 440 leaves AS=1 mappings above the TLB high water
# mark, which doesn't work with current 440 KVM.
depends on 44x && !KVM
help
Select this to enable early debugging for IBM 44x chips via the
inbuilt serial port. If you enable this, ensure you set
@ -258,8 +257,35 @@ config PPC_EARLY_DEBUG_WSP
depends on PPC_WSP
select PPC_UDBG_16550
config PPC_EARLY_DEBUG_PS3GELIC
bool "Early debugging through the PS3 Ethernet port"
depends on PPC_PS3
select PS3GELIC_UDBG
help
Select this to enable early debugging for the PlayStation3 via
UDP broadcasts sent out through the Ethernet port.
config PPC_EARLY_DEBUG_OPAL_RAW
bool "OPAL raw console"
depends on HVC_OPAL
help
Select this to enable early debugging for the PowerNV platform
using a "raw" console
config PPC_EARLY_DEBUG_OPAL_HVSI
bool "OPAL hvsi console"
depends on HVC_OPAL
help
Select this to enable early debugging for the PowerNV platform
using an "hvsi" console
endchoice
config PPC_EARLY_DEBUG_OPAL
def_bool y
depends on PPC_EARLY_DEBUG_OPAL_RAW || PPC_EARLY_DEBUG_OPAL_HVSI
config PPC_EARLY_DEBUG_HVSI_VTERMNO
hex "vterm number to use with early debug HVSI"
depends on PPC_EARLY_DEBUG_LPAR_HVSI
@ -268,6 +294,18 @@ config PPC_EARLY_DEBUG_HVSI_VTERMNO
You probably want 0x30000000 for your first serial port and
0x30000001 for your second one
config PPC_EARLY_DEBUG_OPAL_VTERMNO
hex "vterm number to use with OPAL early debug"
depends on PPC_EARLY_DEBUG_OPAL
default "0"
help
This correspond to which /dev/hvcN you want to use for early
debug.
On OPAL v1 (takeover) this should always be 0
On OPAL v2, this will be 0 for network console and 1 or 2 for
the machine built-in serial ports.
config PPC_EARLY_DEBUG_44x_PHYSLOW
hex "Low 32 bits of early debug UART physical address"
depends on PPC_EARLY_DEBUG_44x

3
arch/powerpc/boot/Makefile
View File

@ -58,7 +58,7 @@ $(addprefix $(obj)/,$(zlib) cuboot-c2k.o gunzip_util.o main.o prpmc2800.o): \
libfdt := fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c
libfdtheader := fdt.h libfdt.h libfdt_internal.h
$(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o): \
$(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o epapr.o): \
$(addprefix $(obj)/,$(libfdtheader))
src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \
@ -171,6 +171,7 @@ quiet_cmd_wrap = WRAP $@
$(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) vmlinux
image-$(CONFIG_PPC_PSERIES) += zImage.pseries
image-$(CONFIG_PPC_POWERNV) += zImage.pseries
image-$(CONFIG_PPC_MAPLE) += zImage.maple
image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
image-$(CONFIG_PPC_PS3) += dtbImage.ps3

61
arch/powerpc/boot/dts/digsy_mtc.dts
View File

@ -23,19 +23,26 @@
soc5200@f0000000 {
timer@600 { // General Purpose Timer
#gpio-cells = <2>;
fsl,has-wdt;
gpio-controller;
};
timer@610 {
#gpio-cells = <2>;
gpio-controller;
};
rtc@800 {
status = "disabled";
};
can@900 {
status = "disabled";
};
can@980 {
status = "disabled";
spi@f00 {
msp430@0 {
compatible = "spidev";
spi-max-frequency = <32000>;
reg = <0>;
};
};
psc@2000 { // PSC1
@ -73,11 +80,16 @@
};
i2c@3d00 {
rtc@50 {
eeprom@50 {
compatible = "at,24c08";
reg = <0x50>;
};
rtc@56 {
compatible = "mc,rv3029c2";
reg = <0x56>;
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
@ -90,11 +102,22 @@
};
pci@f0000d00 {
status = "disabled";
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
0xc000 0 0 2 &mpc5200_pic 0 0 3
0xc000 0 0 3 &mpc5200_pic 0 0 3
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>;
bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
0x02000000 0 0x90000000 0x90000000 0 0x10000000
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
};
localbus {
ranges = <0 0 0xff000000 0x1000000>;
ranges = <0 0 0xff000000 0x1000000
4 0 0x60000000 0x0001000>;
// 16-bit flash device at LocalPlus Bus CS0
flash@0,0 {
@ -122,5 +145,25 @@
reg = <0x00f00000 0x100000>;
};
};
can@4,0 {
compatible = "nxp,sja1000";
reg = <4 0x000 0x80>;
nxp,external-clock-frequency = <24000000>;
interrupts = <1 2 3>; // Level-low
};
can@4,100 {
compatible = "nxp,sja1000";
reg = <4 0x100 0x80>;
nxp,external-clock-frequency = <24000000>;
interrupts = <1 2 3>; // Level-low
};
serial@4,200 {
compatible = "nxp,sc28l92";
reg = <4 0x200 0x10>;
interrupts = <1 3 3>;
};
};
};

33
arch/powerpc/boot/dts/gef_ppc9a.dts
View File

@ -269,14 +269,16 @@
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
@ -290,25 +292,48 @@
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {

33
arch/powerpc/boot/dts/gef_sbc310.dts
View File

@ -267,14 +267,16 @@
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
@ -288,25 +290,48 @@
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {

33
arch/powerpc/boot/dts/gef_sbc610.dts
View File

@ -267,14 +267,16 @@
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
@ -288,25 +290,48 @@
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {

168
arch/powerpc/boot/dts/hcu4.dts
View File

@ -1,168 +0,0 @@
/*
* Device Tree Source for Netstal Maschinen HCU4
* based on the IBM Walnut
*
* Copyright 2008
* Niklaus Giger <niklaus.giger@member.fsf.org>
*
* Copyright 2007 IBM Corp.
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
model = "netstal,hcu4";
compatible = "netstal,hcu4";
dcr-parent = <0x1>;
aliases {
ethernet0 = "/plb/opb/ethernet@ef600800";
serial0 = "/plb/opb/serial@ef600300";
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC,405GPr";
reg = <0x0>;
clock-frequency = <0>; /* Filled in by U-Boot */
timebase-frequency = <0x0>; /* Filled in by U-Boot */
i-cache-line-size = <0x20>;
d-cache-line-size = <0x20>;
i-cache-size = <0x4000>;
d-cache-size = <0x4000>;
dcr-controller;
dcr-access-method = "native";
linux,phandle = <0x1>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>; /* Filled in by U-Boot */
};
UIC0: interrupt-controller {
compatible = "ibm,uic";
interrupt-controller;
cell-index = <0x0>;
dcr-reg = <0xc0 0x9>;
#address-cells = <0x0>;
#size-cells = <0x0>;
#interrupt-cells = <0x2>;
linux,phandle = <0x2>;
};
plb {
compatible = "ibm,plb3";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
clock-frequency = <0x0>; /* Filled in by U-Boot */
SDRAM0: memory-controller {
compatible = "ibm,sdram-405gp";
dcr-reg = <0x10 0x2>;
};
MAL: mcmal {
compatible = "ibm,mcmal-405gp", "ibm,mcmal";
dcr-reg = <0x180 0x62>;
num-tx-chans = <0x1>;
num-rx-chans = <0x1>;
interrupt-parent = <0x2>;
interrupts = <0xb 0x4 0xc 0x4 0xa 0x4 0xd 0x4 0xe 0x4>;
linux,phandle = <0x3>;
};
POB0: opb {
compatible = "ibm,opb-405gp", "ibm,opb";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0xef600000 0xef600000 0xa00000>;
dcr-reg = <0xa0 0x5>;
clock-frequency = <0x0>; /* Filled in by U-Boot */
UART0: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <0xef600300 0x8>;
virtual-reg = <0xef600300>;
clock-frequency = <0x0>;/* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <0x2>;
interrupts = <0x0 0x4>;
};
IIC: i2c@ef600500 {
compatible = "ibm,iic-405gp", "ibm,iic";
reg = <0xef600500 0x11>;
interrupt-parent = <0x2>;
interrupts = <0x2 0x4>;
};
GPIO: gpio@ef600700 {
compatible = "ibm,gpio-405gp";
reg = <0xef600700 0x20>;
};
EMAC: ethernet@ef600800 {
device_type = "network";
compatible = "ibm,emac-405gp", "ibm,emac";
interrupt-parent = <0x2>;
interrupts = <0xf 0x4 0x9 0x4>;
local-mac-address = [00 00 00 00 00 00];
reg = <0xef600800 0x70>;
mal-device = <0x3>;
mal-tx-channel = <0x0>;
mal-rx-channel = <0x0>;
cell-index = <0x0>;
max-frame-size = <0x5dc>;
rx-fifo-size = <0x1000>;
tx-fifo-size = <0x800>;
phy-mode = "rmii";
phy-map = <0x1>;
};
};
EBC0: ebc {
compatible = "ibm,ebc-405gp", "ibm,ebc";
dcr-reg = <0x12 0x2>;
#address-cells = <0x2>;
#size-cells = <0x1>;
clock-frequency = <0x0>; /* Filled in by U-Boot */
sram@0,0 {
reg = <0x0 0x0 0x80000>;
};
flash@0,80000 {
compatible = "jedec-flash";
bank-width = <0x1>;
reg = <0x0 0x80000 0x80000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
partition@0 {
label = "OpenBIOS";
reg = <0x0 0x80000>;
read-only;
};
};
};
};
chosen {
linux,stdout-path = "/plb/opb/serial@ef600300";
};
};

2
arch/powerpc/boot/dts/ksi8560.dts
View File

@ -306,7 +306,7 @@
localbus@fdf05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8560-localbus";
compatible = "fsl,mpc8560-localbus", "simple-bus";
reg = <0xfdf05000 0x68>;
ranges = <0x0 0x0 0xe0000000 0x00800000

9
arch/powerpc/boot/dts/mgcoge.dts
View File

@ -213,6 +213,15 @@
linux,network-index = <2>;
fsl,cpm-command = <0x16200300>;
};
usb@11b60 {
compatible = "fsl,mpc8272-cpm-usb";
mode = "peripheral";
reg = <0x11b60 0x40 0x8b00 0x100>;
interrupts = <11 8>;
interrupt-parent = <&PIC>;
usb-clock = <5>;
};
};
cpm2_pio_c: gpio-controller@10d40 {

2
arch/powerpc/boot/dts/mpc5200b.dtsi
View File

@ -147,6 +147,8 @@
};
spi@f00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;

3
arch/powerpc/boot/dts/mpc8349emitx.dts
View File

@ -390,7 +390,8 @@
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8349e-localbus",
"fsl,pq2pro-localbus";
"fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
ranges = <0x0 0x0 0xfe000000 0x1000000 /* flash */
0x1 0x0 0xf8000000 0x20000 /* VSC 7385 */

2
arch/powerpc/boot/dts/p1022ds.dts
View File

@ -150,7 +150,7 @@
};
board-control@3,0 {
compatible = "fsl,p1022ds-pixis";
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
interrupt-parent = <&mpic>;
/*

5
arch/powerpc/boot/dts/p2020ds.dts
View File

@ -118,6 +118,11 @@
};
};
board-control@3,0 {
compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
reg = <0x3 0x0 0x30>;
};
nand@4,0 {
compatible = "fsl,elbc-fcm-nand";
reg = <0x4 0x0 0x40000>;

17
arch/powerpc/boot/dts/p2040rdb.dts → arch/powerpc/boot/dts/p2041rdb.dts
View File

@ -1,5 +1,5 @@
/*
* P2040RDB Device Tree Source
* P2041RDB Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
@ -32,11 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "p2040si.dtsi"
/include/ "p2041si.dtsi"
/ {
model = "fsl,P2040RDB";
compatible = "fsl,P2040RDB";
model = "fsl,P2041RDB";
compatible = "fsl,P2041RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
@ -45,6 +45,10 @@
device_type = "memory";
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
soc: soc@ffe000000 {
spi@110000 {
flash@0 {
@ -97,13 +101,8 @@
};
};
usb0: usb@210000 {
phy_type = "utmi";
};
usb1: usb@211000 {
dr_mode = "host";
phy_type = "utmi";
};
};

135
arch/powerpc/boot/dts/p2040si.dtsi → arch/powerpc/boot/dts/p2041si.dtsi
View File

@ -1,5 +1,5 @@
/*
* P2040 Silicon Device Tree Source
* P2041 Silicon Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
@ -35,13 +35,14 @@
/dts-v1/;
/ {
compatible = "fsl,P2040";
compatible = "fsl,P2041";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
@ -109,6 +110,74 @@
};
};
dcsr: dcsr@f00000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,dcsr", "simple-bus";
dcsr-epu@0 {
compatible = "fsl,dcsr-epu";
interrupts = <52 2 0 0
84 2 0 0
85 2 0 0>;
interrupt-parent = <&mpic>;
reg = <0x0 0x1000>;
};
dcsr-npc {
compatible = "fsl,dcsr-npc";
reg = <0x1000 0x1000 0x1000000 0x8000>;
};
dcsr-nxc@2000 {
compatible = "fsl,dcsr-nxc";
reg = <0x2000 0x1000>;
};
dcsr-corenet {
compatible = "fsl,dcsr-corenet";
reg = <0x8000 0x1000 0xB0000 0x1000>;
};
dcsr-dpaa@9000 {
compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
reg = <0x9000 0x1000>;
};
dcsr-ocn@11000 {
compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
reg = <0x11000 0x1000>;
};
dcsr-ddr@12000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr>;
reg = <0x12000 0x1000>;
};
dcsr-nal@18000 {
compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
reg = <0x18000 0x1000>;
};
dcsr-rcpm@22000 {
compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
reg = <0x22000 0x1000>;
};
dcsr-cpu-sb-proxy@40000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu0>;
reg = <0x40000 0x1000>;
};
dcsr-cpu-sb-proxy@41000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x41000 0x1000>;
};
dcsr-cpu-sb-proxy@42000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu2>;
reg = <0x42000 0x1000>;
};
dcsr-cpu-sb-proxy@43000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu3>;
reg = <0x43000 0x1000>;
};
};
soc: soc@ffe000000 {
#address-cells = <1>;
#size-cells = <1>;
@ -128,14 +197,14 @@
fsl,num-laws = <32>;
};
memory-controller@8000 {
ddr: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
cpc: l3-cache-controller@10000 {
compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
reg = <0x10000 0x1000>;
interrupts = <16 2 1 27>;
};
@ -226,7 +295,7 @@
};
clockgen: global-utilities@e1000 {
compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
};
@ -238,45 +307,45 @@
};
sfp: sfp@e8000 {
compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
reg = <0xe8000 0x1000>;
};
serdes: serdes@ea000 {
compatible = "fsl,p2040-serdes";
compatible = "fsl,p2041-serdes";
reg = <0xea000 0x1000>;
};
dma0: dma@100300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
reg = <0x100300 0x4>;
ranges = <0x0 0x100100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupts = <28 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <29 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <30 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
@ -287,33 +356,33 @@
dma1: dma@101300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
reg = <0x101300 0x4>;
ranges = <0x0 0x101100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupts = <32 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <33 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <34 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
@ -324,22 +393,20 @@
spi@110000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
reg = <0x110000 0x1000>;
interrupts = <53 0x2 0 0>;
fsl,espi-num-chipselects = <4>;
};
sdhc: sdhc@114000 {
compatible = "fsl,p2040-esdhc", "fsl,esdhc";
compatible = "fsl,p2041-esdhc", "fsl,esdhc";
reg = <0x114000 0x1000>;
interrupts = <48 2 0 0>;
sdhci,auto-cmd12;
clock-frequency = <0>;
};
i2c@118000 {
#address-cells = <1>;
#size-cells = <0>;
@ -417,7 +484,7 @@
};
gpio0: gpio@130000 {
compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
reg = <0x130000 0x1000>;
interrupts = <55 2 0 0>;
#gpio-cells = <2>;
@ -425,32 +492,34 @@
};
usb0: usb@210000 {
compatible = "fsl,p2040-usb2-mph",
compatible = "fsl,p2041-usb2-mph",
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
reg = <0x210000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <44 0x2 0 0>;
phy_type = "utmi";
port0;
};
usb1: usb@211000 {
compatible = "fsl,p2040-usb2-dr",
compatible = "fsl,p2041-usb2-dr",
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
reg = <0x211000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <45 0x2 0 0>;
phy_type = "utmi";
};
sata@220000 {
compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
reg = <0x220000 0x1000>;
interrupts = <68 0x2 0 0>;
};
sata@221000 {
compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
reg = <0x221000 0x1000>;
interrupts = <69 0x2 0 0>;
};
@ -534,19 +603,19 @@
};
localbus@ffe124000 {
compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
#address-cells = <2>;
#size-cells = <1>;
};
pci0: pcie@ffe200000 {
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <0x1fca055>;
clock-frequency = <33333333>;
fsl,msi = <&msi0>;
interrupts = <16 2 1 15>;
pcie@0 {
@ -568,12 +637,12 @@
};
pci1: pcie@ffe201000 {
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0 0xff>;
clock-frequency = <0x1fca055>;
clock-frequency = <33333333>;
fsl,msi = <&msi1>;
interrupts = <16 2 1 14>;
pcie@0 {
@ -595,12 +664,12 @@
};
pci2: pcie@ffe202000 {
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <0x1fca055>;
clock-frequency = <33333333>;
fsl,msi = <&msi2>;
interrupts = <16 2 1 13>;
pcie@0 {

8
arch/powerpc/boot/dts/p3041ds.dts
View File

@ -45,6 +45,10 @@
device_type = "memory";
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
soc: soc@ffe000000 {
spi@110000 {
flash@0 {
@ -147,8 +151,8 @@
};
board-control@3,0 {
compatible = "fsl,p3041ds-pixis";
reg = <3 0 0x20>;
compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
};
};

71
arch/powerpc/boot/dts/p3041si.dtsi
View File

@ -42,6 +42,7 @@
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
@ -114,6 +115,74 @@
};
};
dcsr: dcsr@f00000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,dcsr", "simple-bus";
dcsr-epu@0 {
compatible = "fsl,dcsr-epu";
interrupts = <52 2 0 0
84 2 0 0
85 2 0 0>;
interrupt-parent = <&mpic>;
reg = <0x0 0x1000>;
};
dcsr-npc {
compatible = "fsl,dcsr-npc";
reg = <0x1000 0x1000 0x1000000 0x8000>;
};
dcsr-nxc@2000 {
compatible = "fsl,dcsr-nxc";
reg = <0x2000 0x1000>;
};
dcsr-corenet {
compatible = "fsl,dcsr-corenet";
reg = <0x8000 0x1000 0xB0000 0x1000>;
};
dcsr-dpaa@9000 {
compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa";
reg = <0x9000 0x1000>;
};
dcsr-ocn@11000 {
compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn";
reg = <0x11000 0x1000>;
};
dcsr-ddr@12000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr>;
reg = <0x12000 0x1000>;
};
dcsr-nal@18000 {
compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal";
reg = <0x18000 0x1000>;
};
dcsr-rcpm@22000 {
compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm";
reg = <0x22000 0x1000>;
};
dcsr-cpu-sb-proxy@40000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu0>;
reg = <0x40000 0x1000>;
};
dcsr-cpu-sb-proxy@41000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x41000 0x1000>;
};
dcsr-cpu-sb-proxy@42000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu2>;
reg = <0x42000 0x1000>;
};
dcsr-cpu-sb-proxy@43000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu3>;
reg = <0x43000 0x1000>;
};
};
soc: soc@ffe000000 {
#address-cells = <1>;
#size-cells = <1>;
@ -133,7 +202,7 @@
fsl,num-laws = <32>;
};
memory-controller@8000 {
ddr: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;

238
arch/powerpc/boot/dts/p3060qds.dts Normal file
View File

@ -0,0 +1,238 @@
/*
* P3060QDS Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "p3060si.dtsi"
/ {
model = "fsl,P3060QDS";
compatible = "fsl,P3060QDS";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
memory {
device_type = "memory";
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
soc: soc@ffe000000 {
spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
label = "u-boot";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@kernel {
label = "kernel";
reg = <0x00100000 0x00500000>;
read-only;
};
partition@dtb {
label = "dtb";
reg = <0x00600000 0x00100000>;
read-only;
};
partition@fs {
label = "file system";
reg = <0x00700000 0x00900000>;
};
};
flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,en25q32b";
reg = <1>;
spi-max-frequency = <40000000>; /* input clock */
partition@spi1 {
label = "spi1";
reg = <0x00000000 0x00400000>;
};
};
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db081d";
reg = <2>;
spi-max-frequency = <40000000>; /* input clock */
partition@spi1 {
label = "spi2";
reg = <0x00000000 0x00100000>;
};
};
flash@3 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,sst25wf040";
reg = <3>;
spi-max-frequency = <40000000>; /* input clock */
partition@spi3 {
label = "spi3";
reg = <0x00000000 0x00080000>;
};
};
};
i2c@118000 {
eeprom@51 {
compatible = "at24,24c256";
reg = <0x51>;
};
eeprom@53 {
compatible = "at24,24c256";
reg = <0x53>;
};
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
interrupts = <0x1 0x1 0 0>;
};
};
usb0: usb@210000 {
phy_type = "ulpi";
};
usb1: usb@211000 {
dr_mode = "host";
phy_type = "ulpi";
};
};
rapidio@ffe0c0000 {
reg = <0xf 0xfe0c0000 0 0x11000>;
port1 {
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
};
port2 {
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
};
};
localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x1000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
2 0 0xf 0xffa00000 0x00040000
3 0 0xf 0xffdf0000 0x00008000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x08000000>;
bank-width = <2>;
device-width = <2>;
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
partition@0 {
label = "NAND U-Boot Image";
reg = <0x0 0x02000000>;
read-only;
};
partition@2000000 {
label = "NAND Root File System";
reg = <0x02000000 0x10000000>;
};
partition@12000000 {
label = "NAND Compressed RFS Image";
reg = <0x12000000 0x08000000>;
};
partition@1a000000 {
label = "NAND Linux Kernel Image";
reg = <0x1a000000 0x04000000>;
};
partition@1e000000 {
label = "NAND DTB Image";
reg = <0x1e000000 0x01000000>;
};
partition@1f000000 {
label = "NAND Writable User area";
reg = <0x1f000000 0x21000000>;
};
};
board-control@3,0 {
compatible = "fsl,p3060qds-fpga", "fsl,fpga-qixis";
reg = <3 0 0x100>;
};
};
pci0: pcie@ffe200000 {
reg = <0xf 0xfe200000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci1: pcie@ffe201000 {
reg = <0xf 0xfe201000 0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
};

719
arch/powerpc/boot/dts/p3060si.dtsi Normal file
View File

@ -0,0 +1,719 @@
/*
* P3060 Silicon Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
/ {
compatible = "fsl,P3060";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
pci0 = &pci0;
pci1 = &pci1;
usb0 = &usb0;
usb1 = &usb1;
dma0 = &dma0;
dma1 = &dma1;
msi0 = &msi0;
msi1 = &msi1;
msi2 = &msi2;
crypto = &crypto;
sec_jr0 = &sec_jr0;
sec_jr1 = &sec_jr1;
sec_jr2 = &sec_jr2;
sec_jr3 = &sec_jr3;
rtic_a = &rtic_a;
rtic_b = &rtic_b;
rtic_c = &rtic_c;
rtic_d = &rtic_d;
sec_mon = &sec_mon;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu4: PowerPC,e500mc@4 {
device_type = "cpu";
reg = <4>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu5: PowerPC,e500mc@5 {
device_type = "cpu";
reg = <5>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu6: PowerPC,e500mc@6 {
device_type = "cpu";
reg = <6>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu7: PowerPC,e500mc@7 {
device_type = "cpu";
reg = <7>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
next-level-cache = <&cpc>;
};
};
};
dcsr: dcsr@f00000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,dcsr", "simple-bus";
dcsr-epu@0 {
compatible = "fsl,dcsr-epu";
interrupts = <52 2 0 0
84 2 0 0
85 2 0 0>;
interrupt-parent = <&mpic>;
reg = <0x0 0x1000>;
};
dcsr-npc {
compatible = "fsl,dcsr-npc";
reg = <0x1000 0x1000 0x1000000 0x8000>;
};
dcsr-nxc@2000 {
compatible = "fsl,dcsr-nxc";
reg = <0x2000 0x1000>;
};
dcsr-corenet {
compatible = "fsl,dcsr-corenet";
reg = <0x8000 0x1000 0xB0000 0x1000>;
};
dcsr-dpaa@9000 {
compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
reg = <0x9000 0x1000>;
};
dcsr-ocn@11000 {
compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
reg = <0x11000 0x1000>;
};
dcsr-ddr@12000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr>;
reg = <0x12000 0x1000>;
};
dcsr-nal@18000 {
compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
reg = <0x18000 0x1000>;
};
dcsr-rcpm@22000 {
compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
reg = <0x22000 0x1000>;
};
dcsr-cpu-sb-proxy@40000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu0>;
reg = <0x40000 0x1000>;
};
dcsr-cpu-sb-proxy@41000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x41000 0x1000>;
};
dcsr-cpu-sb-proxy@44000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu4>;
reg = <0x44000 0x1000>;
};
dcsr-cpu-sb-proxy@45000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu5>;
reg = <0x45000 0x1000>;
};
dcsr-cpu-sb-proxy@46000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu6>;
reg = <0x46000 0x1000>;
};
dcsr-cpu-sb-proxy@47000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu7>;
reg = <0x47000 0x1000>;
};
};
soc: soc@ffe000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
soc-sram-error {
compatible = "fsl,soc-sram-error";
interrupts = <16 2 1 29>;
};
corenet-law@0 {
compatible = "fsl,corenet-law";
reg = <0x0 0x1000>;
fsl,num-laws = <32>;
};
ddr: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
cpc: l3-cache-controller@10000 {
compatible = "fsl,p3060-l3-cache-controller", "cache";
reg = <0x10000 0x1000
0x11000 0x1000>;
interrupts = <16 2 1 27>;
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
fsl,ccf-num-snoopids = <32>;
};
iommu@20000 {
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x5000>;
interrupts = <
24 2 0 0
16 2 1 30>;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic", "chrp,open-pic";
device_type = "open-pic";
};
msi0: msi@41600 {
compatible = "fsl,mpic-msi";
reg = <0x41600 0x200>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0
0xe4 0 0 0
0xe5 0 0 0
0xe6 0 0 0
0xe7 0 0 0>;
};
msi1: msi@41800 {
compatible = "fsl,mpic-msi";
reg = <0x41800 0x200>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe8 0 0 0
0xe9 0 0 0
0xea 0 0 0
0xeb 0 0 0
0xec 0 0 0
0xed 0 0 0
0xee 0 0 0
0xef 0 0 0>;
};
msi2: msi@41a00 {
compatible = "fsl,mpic-msi";
reg = <0x41a00 0x200>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xf0 0 0 0
0xf1 0 0 0
0xf2 0 0 0
0xf3 0 0 0
0xf4 0 0 0
0xf5 0 0 0
0xf6 0 0 0
0xf7 0 0 0>;
};
rmu: rmu@d3000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,srio-rmu";
reg = <0xd3000 0x500>;
ranges = <0x0 0xd3000 0x500>;
message-unit@0 {
compatible = "fsl,srio-msg-unit";
reg = <0x0 0x100>;
interrupts = <
60 2 0 0 /* msg1_tx_irq */
61 2 0 0>;/* msg1_rx_irq */
};
message-unit@100 {
compatible = "fsl,srio-msg-unit";
reg = <0x100 0x100>;
interrupts = <
62 2 0 0 /* msg2_tx_irq */
63 2 0 0>;/* msg2_rx_irq */
};
doorbell-unit@400 {
compatible = "fsl,srio-dbell-unit";
reg = <0x400 0x80>;
interrupts = <
56 2 0 0 /* bell_outb_irq */
57 2 0 0>;/* bell_inb_irq */
};
port-write-unit@4e0 {
compatible = "fsl,srio-port-write-unit";
reg = <0x4e0 0x20>;
interrupts = <16 2 1 11>;
};
};
guts: global-utilities@e0000 {
compatible = "fsl,qoriq-device-config-1.0";
reg = <0xe0000 0xe00>;
fsl,has-rstcr;
#sleep-cells = <1>;
fsl,liodn-bits = <12>;
};
pins: global-utilities@e0e00 {
compatible = "fsl,qoriq-pin-control-1.0";
reg = <0xe0e00 0x200>;
#sleep-cells = <2>;
};
clockgen: global-utilities@e1000 {
compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
};
rcpm: global-utilities@e2000 {
compatible = "fsl,qoriq-rcpm-1.0";
reg = <0xe2000 0x1000>;
#sleep-cells = <1>;
};
sfp: sfp@e8000 {
compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
reg = <0xe8000 0x1000>;
};
serdes: serdes@ea000 {
compatible = "fsl,p3060-serdes";
reg = <0xea000 0x1000>;
};
dma0: dma@100300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p3060-dma", "fsl,eloplus-dma";
reg = <0x100300 0x4>;
ranges = <0x0 0x100100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,p3060-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupts = <28 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,p3060-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <29 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,p3060-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <30 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,p3060-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupts = <31 2 0 0>;
};
};
dma1: dma@101300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p3060-dma", "fsl,eloplus-dma";
reg = <0x101300 0x4>;
ranges = <0x0 0x101100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,p3060-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupts = <32 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,p3060-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <33 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,p3060-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <34 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,p3060-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupts = <35 2 0 0>;
};
};
spi@110000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,p3060-espi", "fsl,mpc8536-espi";
reg = <0x110000 0x1000>;
interrupts = <53 0x2 0 0>;
fsl,espi-num-chipselects = <4>;
};
i2c@118000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x118000 0x100>;
interrupts = <38 2 0 0>;
dfsrr;
};
i2c@118100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x118100 0x100>;
interrupts = <38 2 0 0>;
dfsrr;
};
i2c@119000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
compatible = "fsl-i2c";
reg = <0x119000 0x100>;
interrupts = <39 2 0 0>;
dfsrr;
};
i2c@119100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <3>;
compatible = "fsl-i2c";
reg = <0x119100 0x100>;
interrupts = <39 2 0 0>;
dfsrr;
};
serial0: serial@11c500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x11c500 0x100>;
clock-frequency = <0>;
interrupts = <36 2 0 0>;
};
serial1: serial@11c600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x11c600 0x100>;
clock-frequency = <0>;
interrupts = <36 2 0 0>;
};
serial2: serial@11d500 {
cell-index = <2>;
device_type = "serial";
compatible = "ns16550";
reg = <0x11d500 0x100>;
clock-frequency = <0>;
interrupts = <37 2 0 0>;
};
serial3: serial@11d600 {
cell-index = <3>;
device_type = "serial";
compatible = "ns16550";
reg = <0x11d600 0x100>;
clock-frequency = <0>;
interrupts = <37 2 0 0>;
};
gpio0: gpio@130000 {
compatible = "fsl,p3060-gpio", "fsl,qoriq-gpio";
reg = <0x130000 0x1000>;
interrupts = <55 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
};
usb0: usb@210000 {
compatible = "fsl,p3060-usb2-mph",
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
reg = <0x210000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <44 0x2 0 0>;
};
usb1: usb@211000 {
compatible = "fsl,p3060-usb2-dr",
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
reg = <0x211000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <45 0x2 0 0>;
};
crypto: crypto@300000 {
compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2 0 0>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <88 2 0 0>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <89 2 0 0>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <90 2 0 0>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <91 2 0 0>;
};
rtic@6000 {
compatible = "fsl,sec-v4.1-rtic", "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <93 2 0 0>;
};
};
rapidio@ffe0c0000 {
compatible = "fsl,srio";
interrupts = <16 2 1 11>;
#address-cells = <2>;
#size-cells = <2>;
fsl,srio-rmu-handle = <&rmu>;
ranges;
port1 {
#address-cells = <2>;
#size-cells = <2>;
cell-index = <1>;
};
port2 {
#address-cells = <2>;
#size-cells = <2>;
cell-index = <2>;
};
};
localbus@ffe124000 {
compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
#address-cells = <2>;
#size-cells = <1>;
};
pci0: pcie@ffe200000 {
compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <33333333>;
fsl,msi = <&msi0>;
interrupts = <16 2 1 15>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <16 2 1 15>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 40 1 0 0
0000 0 0 2 &mpic 1 1 0 0
0000 0 0 3 &mpic 2 1 0 0
0000 0 0 4 &mpic 3 1 0 0
>;
};
};
pci1: pcie@ffe201000 {
compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0 0xff>;
clock-frequency = <33333333>;
fsl,msi = <&msi1>;
interrupts = <16 2 1 14>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <16 2 1 14>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 41 1 0 0
0000 0 0 2 &mpic 5 1 0 0
0000 0 0 3 &mpic 6 1 0 0
0000 0 0 4 &mpic 7 1 0 0
>;
};
};
};

12
arch/powerpc/boot/dts/p4080ds.dts
View File

@ -45,6 +45,10 @@
device_type = "memory";
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
soc: soc@ffe000000 {
spi@110000 {
flash@0 {
@ -108,7 +112,8 @@
localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x1000>;
ranges = <0 0 0xf 0xe8000000 0x08000000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
3 0 0xf 0xffdf0000 0x00008000>;
flash@0,0 {
compatible = "cfi-flash";
@ -116,6 +121,11 @@
bank-width = <2>;
device-width = <2>;
};
board-control@3,0 {
compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
};
};
pci0: pcie@ffe200000 {

114
arch/powerpc/boot/dts/p4080si.dtsi
View File

@ -42,6 +42,7 @@
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
@ -77,7 +78,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,4080@0 {
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2_0>;
@ -85,7 +86,7 @@
next-level-cache = <&cpc>;
};
};
cpu1: PowerPC,4080@1 {
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2_1>;
@ -93,7 +94,7 @@
next-level-cache = <&cpc>;
};
};
cpu2: PowerPC,4080@2 {
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2_2>;
@ -101,7 +102,7 @@
next-level-cache = <&cpc>;
};
};
cpu3: PowerPC,4080@3 {
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2_3>;
@ -109,7 +110,7 @@
next-level-cache = <&cpc>;
};
};
cpu4: PowerPC,4080@4 {
cpu4: PowerPC,e500mc@4 {
device_type = "cpu";
reg = <4>;
next-level-cache = <&L2_4>;
@ -117,7 +118,7 @@
next-level-cache = <&cpc>;
};
};
cpu5: PowerPC,4080@5 {
cpu5: PowerPC,e500mc@5 {
device_type = "cpu";
reg = <5>;
next-level-cache = <&L2_5>;
@ -125,7 +126,7 @@
next-level-cache = <&cpc>;
};
};
cpu6: PowerPC,4080@6 {
cpu6: PowerPC,e500mc@6 {
device_type = "cpu";
reg = <6>;
next-level-cache = <&L2_6>;
@ -133,7 +134,7 @@
next-level-cache = <&cpc>;
};
};
cpu7: PowerPC,4080@7 {
cpu7: PowerPC,e500mc@7 {
device_type = "cpu";
reg = <7>;
next-level-cache = <&L2_7>;
@ -143,6 +144,99 @@
};
};
dcsr: dcsr@f00000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,dcsr", "simple-bus";
dcsr-epu@0 {
compatible = "fsl,dcsr-epu";
interrupts = <52 2 0 0
84 2 0 0
85 2 0 0>;
interrupt-parent = <&mpic>;
reg = <0x0 0x1000>;
};
dcsr-npc {
compatible = "fsl,dcsr-npc";
reg = <0x1000 0x1000 0x1000000 0x8000>;
};
dcsr-nxc@2000 {
compatible = "fsl,dcsr-nxc";
reg = <0x2000 0x1000>;
};
dcsr-corenet {
compatible = "fsl,dcsr-corenet";
reg = <0x8000 0x1000 0xB0000 0x1000>;
};
dcsr-dpaa@9000 {
compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
reg = <0x9000 0x1000>;
};
dcsr-ocn@11000 {
compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
reg = <0x11000 0x1000>;
};
dcsr-ddr@12000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr1>;
reg = <0x12000 0x1000>;
};
dcsr-ddr@13000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr2>;
reg = <0x13000 0x1000>;
};
dcsr-nal@18000 {
compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
reg = <0x18000 0x1000>;
};
dcsr-rcpm@22000 {
compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
reg = <0x22000 0x1000>;
};
dcsr-cpu-sb-proxy@40000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu0>;
reg = <0x40000 0x1000>;
};
dcsr-cpu-sb-proxy@41000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x41000 0x1000>;
};
dcsr-cpu-sb-proxy@42000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu2>;
reg = <0x42000 0x1000>;
};
dcsr-cpu-sb-proxy@43000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu3>;
reg = <0x43000 0x1000>;
};
dcsr-cpu-sb-proxy@44000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu4>;
reg = <0x44000 0x1000>;
};
dcsr-cpu-sb-proxy@45000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu5>;
reg = <0x45000 0x1000>;
};
dcsr-cpu-sb-proxy@46000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu6>;
reg = <0x46000 0x1000>;
};
dcsr-cpu-sb-proxy@47000 {
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu7>;
reg = <0x47000 0x1000>;
};
};
soc: soc@ffe000000 {
#address-cells = <1>;
#size-cells = <1>;
@ -162,13 +256,13 @@
fsl,num-laws = <32>;
};
memory-controller@8000 {
ddr1: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
memory-controller@9000 {
ddr2: memory-controller@9000 {
compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
reg = <0x9000 0x1000>;
interrupts = <16 2 1 22>;

8
arch/powerpc/boot/dts/p5020ds.dts
View File

@ -45,6 +45,10 @@
device_type = "memory";
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
soc: soc@ffe000000 {
spi@110000 {
flash@0 {
@ -147,8 +151,8 @@
};
board-control@3,0 {
compatible = "fsl,p5020ds-pixis";
reg = <3 0 0x20>;
compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
};
};

68
arch/powerpc/boot/dts/p5020si.dtsi
View File

@ -42,6 +42,7 @@
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
@ -98,6 +99,69 @@
};
};
dcsr: dcsr@f00000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,dcsr", "simple-bus";
dcsr-epu@0 {
compatible = "fsl,dcsr-epu";
interrupts = <52 2 0 0
84 2 0 0
85 2 0 0>;
interrupt-parent = <&mpic>;
reg = <0x0 0x1000>;
};
dcsr-npc {
compatible = "fsl,dcsr-npc";
reg = <0x1000 0x1000 0x1000000 0x8000>;
};
dcsr-nxc@2000 {
compatible = "fsl,dcsr-nxc";
reg = <0x2000 0x1000>;
};
dcsr-corenet {
compatible = "fsl,dcsr-corenet";
reg = <0x8000 0x1000 0xB0000 0x1000>;
};
dcsr-dpaa@9000 {
compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
reg = <0x9000 0x1000>;
};
dcsr-ocn@11000 {
compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
reg = <0x11000 0x1000>;
};
dcsr-ddr@12000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr1>;
reg = <0x12000 0x1000>;
};
dcsr-ddr@13000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr2>;
reg = <0x13000 0x1000>;
};
dcsr-nal@18000 {
compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
reg = <0x18000 0x1000>;
};
dcsr-rcpm@22000 {
compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
reg = <0x22000 0x1000>;
};
dcsr-cpu-sb-proxy@40000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu0>;
reg = <0x40000 0x1000>;
};
dcsr-cpu-sb-proxy@41000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x41000 0x1000>;
};
};
soc: soc@ffe000000 {
#address-cells = <1>;
#size-cells = <1>;
@ -117,13 +181,13 @@
fsl,num-laws = <32>;
};
memory-controller@8000 {
ddr1: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
memory-controller@9000 {
ddr2: memory-controller@9000 {
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
reg = <0x9000 0x1000>;
interrupts = <16 2 1 22>;

2
arch/powerpc/boot/dts/sbc8560.dts
View File

@ -331,7 +331,7 @@
};
localbus@ff705000 {
compatible = "fsl,mpc8560-localbus";
compatible = "fsl,mpc8560-localbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xff705000 0x100>; // BRx, ORx, etc.

36
arch/powerpc/boot/dts/yosemite.dts
View File

@ -138,6 +138,42 @@
clock-frequency = <0>; /* Filled in by zImage */
interrupts = <0x5 0x1>;
interrupt-parent = <&UIC1>;
nor_flash@0,0 {
compatible = "amd,s29gl256n", "cfi-flash";
bank-width = <2>;
reg = <0x00000000 0x00000000 0x04000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x001e0000>;
};
partition@1e0000 {
label = "dtb";
reg = <0x001e0000 0x00020000>;
};
partition@200000 {
label = "ramdisk";
reg = <0x00200000 0x01400000>;
};
partition@1600000 {
label = "jffs2";
reg = <0x01600000 0x00400000>;
};
partition@1a00000 {
label = "user";
reg = <0x01a00000 0x02540000>;
};
partition@3f40000 {
label = "env";
reg = <0x03f40000 0x00040000>;
};
partition@3f80000 {
label = "u-boot";
reg = <0x03f80000 0x00080000>;
};
};
};
UART0: serial@ef600300 {

81
arch/powerpc/configs/40x/hcu4_defconfig
View File

@ -1,81 +0,0 @@
CONFIG_40x=y
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_HCU4=y
# CONFIG_WALNUT is not set
CONFIG_SPARSE_IRQ=y
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_CONNECTOR=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=m
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_NETDEVICES=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_INOTIFY=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_CRYPTO=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

2
arch/powerpc/configs/85xx/p1023rds_defconfig
View File

@ -24,7 +24,7 @@ CONFIG_P1023_RDS=y
CONFIG_QUICC_ENGINE=y
CONFIG_QE_GPIO=y
CONFIG_CPM2=y
CONFIG_MPC8xxx_GPIO=y
CONFIG_GPIO_MPC8XXX=y
CONFIG_HIGHMEM=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

2
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
View File

@ -20,7 +20,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_XES_MPC85xx=y
CONFIG_MPC8xxx_GPIO=y
CONFIG_GPIO_MPC8XXX=y
CONFIG_HIGHMEM=y
CONFIG_MATH_EMULATION=y
CONFIG_SPARSE_IRQ=y

11
arch/powerpc/configs/corenet32_smp_defconfig
View File

@ -12,9 +12,7 @@ CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
@ -23,8 +21,9 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_P2040_RDB=y
CONFIG_P2041_RDB=y
CONFIG_P3041_DS=y
CONFIG_P3060_QDS=y
CONFIG_P4080_DS=y
CONFIG_P5020_DS=y
CONFIG_HIGHMEM=y
@ -69,7 +68,6 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
@ -107,7 +105,6 @@ CONFIG_FSL_PQ_MDIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_PPC_EPAPR_HV_BYTECHAN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
@ -136,8 +133,6 @@ CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_OF=y
CONFIG_MMC_SDHCI_OF_ESDHC=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_MPC85XX=y
@ -146,7 +141,6 @@ CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_UIO=y
CONFIG_STAGING=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_FSL_HV_MANAGER=y
CONFIG_EXT2_FS=y
@ -173,7 +167,6 @@ CONFIG_MAC_PARTITION=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=m
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y

5
arch/powerpc/configs/corenet64_smp_defconfig
View File

@ -11,10 +11,8 @@ CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
@ -25,7 +23,6 @@ CONFIG_P5020_DS=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BINFMT_MISC=m
# CONFIG_PCI is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -93,10 +90,8 @@ CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=m
CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_VIRQ_DEBUG=y
CONFIG_CRYPTO_PCBC=m

27
arch/powerpc/configs/mgcoge_defconfig
View File

@ -1,15 +1,22 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_SPARSE_IRQ=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_RD_GZIP is not set
CONFIG_KALLSYMS_ALL=y
# CONFIG_PCSPKR_PLATFORM is not set
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_82xx=y
CONFIG_MGCOGE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BINFMT_MISC=y
# CONFIG_SECCOMP is not set
CONFIG_NET=y
@ -24,11 +31,10 @@ CONFIG_SYN_COOKIES=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
CONFIG_TIPC=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
@ -42,7 +48,6 @@ CONFIG_MTD_PHYSMAP_OF=y
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
# CONFIG_MACINTOSH_DRIVERS is not set
CONFIG_NETDEVICES=y
CONFIG_FIXED_PHY=y
CONFIG_NET_ETHERNET=y
@ -50,6 +55,7 @@ CONFIG_FS_ENET=y
CONFIG_FS_ENET_MDIO_FCC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
@ -57,24 +63,24 @@ CONFIG_SERIAL_CPM=y
CONFIG_SERIAL_CPM_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_POWERMAC is not set
CONFIG_I2C_CPM=y
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB_GADGET=y
CONFIG_USB_FSL_USB2=y
CONFIG_USB_G_SERIAL=y
CONFIG_UIO=y
CONFIG_UIO_PDRV=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_AUTOFS4_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_SQUASHFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_MAC_PARTITION is not set
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
@ -82,7 +88,6 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_DEBUG_INFO=y
CONFIG_SYSCTL_SYSCALL_CHECK=y

19
arch/powerpc/configs/mpc512x_defconfig
View File

@ -1,9 +1,9 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_SPARSE_IRQ=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
@ -13,10 +13,11 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_PPC_CHRP is not set
CONFIG_PPC_MPC512x=y
CONFIG_MPC5121_ADS=y
CONFIG_MPC5121_GENERIC=y
CONFIG_PDM360NG=y
# CONFIG_PPC_PMAC is not set
CONFIG_NO_HZ=y
CONFIG_HZ_1000=y
CONFIG_SPARSE_IRQ=y
# CONFIG_MIGRATION is not set
# CONFIG_SECCOMP is not set
# CONFIG_PCI is not set
@ -35,18 +36,16 @@ CONFIG_CAN=y
CONFIG_CAN_RAW=y
CONFIG_CAN_BCM=y
CONFIG_CAN_VCAN=y
CONFIG_CAN_DEV=y
CONFIG_CAN_MSCAN=y
CONFIG_CAN_DEBUG_DEVICES=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
@ -63,6 +62,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_XIP=y
CONFIG_MISC_DEVICES=y
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
@ -99,10 +99,14 @@ CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD=115200
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_SPI=y
CONFIG_SPI_MPC512x_PSC=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MPC8XXX=y
# CONFIG_HWMON is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
# CONFIG_VIDEO_ALLOW_V4L1 is not set
CONFIG_VIDEO_ADV_DEBUG=y
# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
CONFIG_VIDEO_SAA711X=y
@ -132,6 +136,5 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set

12
arch/powerpc/configs/mpc5200_defconfig
View File

@ -88,6 +88,18 @@ CONFIG_FB_RADEON=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_PCI is not set
# CONFIG_SND_PPC is not set
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_MPC5200_I2S=y
CONFIG_SND_MPC52xx_SOC_PCM030=y
CONFIG_SND_MPC52xx_SOC_EFIKA=y
CONFIG_HID_DRAGONRISE=y
CONFIG_HID_GYRATION=y
CONFIG_HID_TWINHAN=y

5
arch/powerpc/configs/mpc85xx_defconfig
View File

@ -10,10 +10,8 @@ CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
@ -41,7 +39,6 @@ CONFIG_TQM8560=y
CONFIG_SBC8548=y
CONFIG_QUICC_ENGINE=y
CONFIG_QE_GPIO=y
CONFIG_MPC8xxx_GPIO=y
CONFIG_HIGHMEM=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@ -123,6 +120,7 @@ CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_CPM=m
CONFIG_I2C_MPC=y
CONFIG_GPIO_MPC8XXX=y
# CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_FB=y
@ -206,7 +204,6 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
CONFIG_CRC_T10DIF=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
CONFIG_SYSCTL_SYSCALL_CHECK=y

6
arch/powerpc/configs/mpc85xx_smp_defconfig
View File

@ -12,10 +12,8 @@ CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
@ -42,7 +40,6 @@ CONFIG_TQM8560=y
CONFIG_SBC8548=y
CONFIG_QUICC_ENGINE=y
CONFIG_QE_GPIO=y
CONFIG_MPC8xxx_GPIO=y
CONFIG_HIGHMEM=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@ -124,6 +121,7 @@ CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_CPM=m
CONFIG_I2C_MPC=y
CONFIG_GPIO_MPC8XXX=y
# CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_FB=y
@ -207,10 +205,8 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
CONFIG_CRC_T10DIF=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_VIRQ_DEBUG=y
CONFIG_CRYPTO_PCBC=m

1
arch/powerpc/configs/ppc40x_defconfig
View File

@ -14,7 +14,6 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_PPC4xx_GPIO=y
CONFIG_ACADIA=y
CONFIG_EP405=y
CONFIG_HCU4=y
CONFIG_HOTFOOT=y
CONFIG_KILAUEA=y
CONFIG_MAKALU=y

2
arch/powerpc/configs/ppc6xx_defconfig
View File

@ -70,7 +70,7 @@ CONFIG_TAU_AVERAGE=y
CONFIG_QUICC_ENGINE=y
CONFIG_QE_GPIO=y
CONFIG_PPC_BESTCOMM=y
CONFIG_MPC8xxx_GPIO=y
CONFIG_GPIO_MPC8XXX=y
CONFIG_MCU_MPC8349EMITX=m
CONFIG_HIGHMEM=y
CONFIG_NO_HZ=y

2
arch/powerpc/include/asm/device.h
View File

@ -37,4 +37,6 @@ struct pdev_archdata {
u64 dma_mask;
};
#define ARCH_HAS_DMA_GET_REQUIRED_MASK
#endif /* _ASM_POWERPC_DEVICE_H */

10
arch/powerpc/include/asm/firmware.h
View File

@ -48,6 +48,8 @@
#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
#define FW_FEATURE_OPAL ASM_CONST(0x0000000010000000)
#define FW_FEATURE_OPALv2 ASM_CONST(0x0000000020000000)
#ifndef __ASSEMBLY__
@ -65,6 +67,8 @@ enum {
FW_FEATURE_PSERIES_ALWAYS = 0,
FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2,
FW_FEATURE_POWERNV_ALWAYS = 0,
FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
@ -78,6 +82,9 @@ enum {
#ifdef CONFIG_PPC_ISERIES
FW_FEATURE_ISERIES_POSSIBLE |
#endif
#ifdef CONFIG_PPC_POWERNV
FW_FEATURE_POWERNV_POSSIBLE |
#endif
#ifdef CONFIG_PPC_PS3
FW_FEATURE_PS3_POSSIBLE |
#endif
@ -95,6 +102,9 @@ enum {
#ifdef CONFIG_PPC_ISERIES
FW_FEATURE_ISERIES_ALWAYS &
#endif
#ifdef CONFIG_PPC_POWERNV
FW_FEATURE_POWERNV_ALWAYS &
#endif
#ifdef CONFIG_PPC_PS3
FW_FEATURE_PS3_ALWAYS &
#endif

63
arch/powerpc/include/asm/hugetlb.h
View File

@ -1,15 +1,60 @@
#ifndef _ASM_POWERPC_HUGETLB_H
#define _ASM_POWERPC_HUGETLB_H
#ifdef CONFIG_HUGETLB_PAGE
#include <asm/page.h>
extern struct kmem_cache *hugepte_cache;
extern void __init reserve_hugetlb_gpages(void);
static inline pte_t *hugepd_page(hugepd_t hpd)
{
BUG_ON(!hugepd_ok(hpd));
return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
}
static inline unsigned int hugepd_shift(hugepd_t hpd)
{
return hpd.pd & HUGEPD_SHIFT_MASK;
}
static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
unsigned pdshift)
{
/*
* On 32-bit, we have multiple higher-level table entries that point to
* the same hugepte. Just use the first one since they're all
* identical. So for that case, idx=0.
*/
unsigned long idx = 0;
pte_t *dir = hugepd_page(*hpdp);
#ifdef CONFIG_PPC64
idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
#endif
return dir + idx;
}
pte_t *huge_pte_offset_and_shift(struct mm_struct *mm,
unsigned long addr, unsigned *shift);
void flush_dcache_icache_hugepage(struct page *page);
#if defined(CONFIG_PPC_MM_SLICES) || defined(CONFIG_PPC_SUBPAGE_PROT)
int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
unsigned long len);
#else
static inline int is_hugepage_only_range(struct mm_struct *mm,
unsigned long addr,
unsigned long len)
{
return 0;
}
#endif
void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte);
void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
unsigned long end, unsigned long floor,
@ -50,8 +95,11 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
unsigned long old = pte_update(mm, addr, ptep, ~0UL, 1);
return __pte(old);
#ifdef CONFIG_PPC64
return __pte(pte_update(mm, addr, ptep, ~0UL, 1));
#else
return __pte(pte_update(ptep, ~0UL, 0));
#endif
}
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
@ -93,4 +141,15 @@ static inline void arch_release_hugepage(struct page *page)
{
}
#else /* ! CONFIG_HUGETLB_PAGE */
static inline void reserve_hugetlb_gpages(void)
{
pr_err("Cannot reserve gpages without hugetlb enabled\n");
}
static inline void flush_hugetlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
}
#endif
#endif /* _ASM_POWERPC_HUGETLB_H */

2
arch/powerpc/include/asm/kexec.h
View File

@ -2,7 +2,7 @@
#define _ASM_POWERPC_KEXEC_H
#ifdef __KERNEL__
#ifdef CONFIG_FSL_BOOKE
#if defined(CONFIG_FSL_BOOKE) || defined(CONFIG_44x)
/*
* On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory

3
arch/powerpc/include/asm/machdep.h
View File

@ -85,8 +85,9 @@ struct machdep_calls {
void (*pci_dma_dev_setup)(struct pci_dev *dev);
void (*pci_dma_bus_setup)(struct pci_bus *bus);
/* Platform set_dma_mask override */
/* Platform set_dma_mask and dma_get_required_mask overrides */
int (*dma_set_mask)(struct device *dev, u64 dma_mask);
u64 (*dma_get_required_mask)(struct device *dev);
int (*probe)(void);
void (*setup_arch)(void); /* Optional, may be NULL */

7
arch/powerpc/include/asm/mmu-book3e.h
View File

@ -66,6 +66,7 @@
#define MAS2_M 0x00000004
#define MAS2_G 0x00000002
#define MAS2_E 0x00000001
#define MAS2_WIMGE_MASK 0x0000001f
#define MAS2_EPN_MASK(size) (~0 << (size + 10))
#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
@ -80,6 +81,7 @@
#define MAS3_SW 0x00000004
#define MAS3_UR 0x00000002
#define MAS3_SR 0x00000001
#define MAS3_BAP_MASK 0x0000003f
#define MAS3_SPSIZE 0x0000003e
#define MAS3_SPSIZE_SHIFT 1
@ -212,6 +214,11 @@ typedef struct {
unsigned int id;
unsigned int active;
unsigned long vdso_base;
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
u64 high_slices_psize; /* 4 bits per slice for now */
u16 user_psize; /* page size index */
#endif
} mm_context_t;
/* Page size definitions, common between 32 and 64-bit

3
arch/powerpc/include/asm/mmu-hash64.h
View File

@ -262,8 +262,7 @@ extern void hash_failure_debug(unsigned long ea, unsigned long access,
extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
unsigned long pstart, unsigned long prot,
int psize, int ssize);
extern void add_gpage(unsigned long addr, unsigned long page_size,
unsigned long number_of_pages);
extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
extern void hpte_init_native(void);

16
arch/powerpc/include/asm/mmu.h
View File

@ -175,14 +175,16 @@ extern u64 ppc64_rma_size;
#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
#define MMU_PAGE_256K 4
#define MMU_PAGE_1M 5
#define MMU_PAGE_8M 6
#define MMU_PAGE_16M 7
#define MMU_PAGE_256M 8
#define MMU_PAGE_1G 9
#define MMU_PAGE_16G 10
#define MMU_PAGE_64G 11
#define MMU_PAGE_COUNT 12
#define MMU_PAGE_4M 6
#define MMU_PAGE_8M 7
#define MMU_PAGE_16M 8
#define MMU_PAGE_64M 9
#define MMU_PAGE_256M 10
#define MMU_PAGE_1G 11
#define MMU_PAGE_16G 12
#define MMU_PAGE_64G 13
#define MMU_PAGE_COUNT 14
#if defined(CONFIG_PPC_STD_MMU_64)
/* 64-bit classic hash table MMU */

2
arch/powerpc/include/asm/mpic.h
View File

@ -273,8 +273,6 @@ struct mpic
unsigned int irq_count;
/* Number of sources */
unsigned int num_sources;
/* Number of CPUs */
unsigned int num_cpus;
/* default senses array */
unsigned char *senses;
unsigned int senses_count;

443
arch/powerpc/include/asm/opal.h Normal file
View File

@ -0,0 +1,443 @@
/*
* PowerNV OPAL definitions.
*
* Copyright 2011 IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __OPAL_H
#define __OPAL_H
/****** Takeover interface ********/
/* PAPR H-Call used to querty the HAL existence and/or instanciate
* it from within pHyp (tech preview only).
*
* This is exclusively used in prom_init.c
*/
#ifndef __ASSEMBLY__
struct opal_takeover_args {
u64 k_image; /* r4 */
u64 k_size; /* r5 */
u64 k_entry; /* r6 */
u64 k_entry2; /* r7 */
u64 hal_addr; /* r8 */
u64 rd_image; /* r9 */
u64 rd_size; /* r10 */
u64 rd_loc; /* r11 */
};
extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
extern long opal_do_takeover(struct opal_takeover_args *args);
struct rtas_args;
extern int opal_enter_rtas(struct rtas_args *args,
unsigned long data,
unsigned long entry);
#endif /* __ASSEMBLY__ */
/****** OPAL APIs ******/
/* Return codes */
#define OPAL_SUCCESS 0
#define OPAL_PARAMETER -1
#define OPAL_BUSY -2
#define OPAL_PARTIAL -3
#define OPAL_CONSTRAINED -4
#define OPAL_CLOSED -5
#define OPAL_HARDWARE -6
#define OPAL_UNSUPPORTED -7
#define OPAL_PERMISSION -8
#define OPAL_NO_MEM -9
#define OPAL_RESOURCE -10
#define OPAL_INTERNAL_ERROR -11
#define OPAL_BUSY_EVENT -12
#define OPAL_HARDWARE_FROZEN -13
/* API Tokens (in r0) */
#define OPAL_CONSOLE_WRITE 1
#define OPAL_CONSOLE_READ 2
#define OPAL_RTC_READ 3
#define OPAL_RTC_WRITE 4
#define OPAL_CEC_POWER_DOWN 5
#define OPAL_CEC_REBOOT 6
#define OPAL_READ_NVRAM 7
#define OPAL_WRITE_NVRAM 8
#define OPAL_HANDLE_INTERRUPT 9
#define OPAL_POLL_EVENTS 10
#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
#define OPAL_PCI_CONFIG_READ_BYTE 13
#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
#define OPAL_PCI_CONFIG_READ_WORD 15
#define OPAL_PCI_CONFIG_WRITE_BYTE 16
#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
#define OPAL_PCI_CONFIG_WRITE_WORD 18
#define OPAL_SET_XIVE 19
#define OPAL_GET_XIVE 20
#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
#define OPAL_PCI_EEH_FREEZE_STATUS 23
#define OPAL_PCI_SHPC 24
#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
#define OPAL_PCI_EEH_FREEZE_CLEAR 26
#define OPAL_PCI_PHB_MMIO_ENABLE 27
#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
#define OPAL_PCI_SET_PE 31
#define OPAL_PCI_SET_PELTV 32
#define OPAL_PCI_SET_MVE 33
#define OPAL_PCI_SET_MVE_ENABLE 34
#define OPAL_PCI_GET_XIVE_REISSUE 35
#define OPAL_PCI_SET_XIVE_REISSUE 36
#define OPAL_PCI_SET_XIVE_PE 37
#define OPAL_GET_XIVE_SOURCE 38
#define OPAL_GET_MSI_32 39
#define OPAL_GET_MSI_64 40
#define OPAL_START_CPU 41
#define OPAL_QUERY_CPU_STATUS 42
#define OPAL_WRITE_OPPANEL 43
#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
#define OPAL_PCI_RESET 49
#ifndef __ASSEMBLY__
/* Other enums */
enum OpalVendorApiTokens {
OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
};
enum OpalFreezeState {
OPAL_EEH_STOPPED_NOT_FROZEN = 0,
OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
OPAL_EEH_STOPPED_DMA_FREEZE = 2,
OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
OPAL_EEH_STOPPED_RESET = 4,
OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
};
enum OpalEehFreezeActionToken {
OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
};
enum OpalPciStatusToken {
OPAL_EEH_PHB_NO_ERROR = 0,
OPAL_EEH_PHB_FATAL = 1,
OPAL_EEH_PHB_RECOVERABLE = 2,
OPAL_EEH_PHB_BUS_ERROR = 3,
OPAL_EEH_PCI_NO_DEVSEL = 4,
OPAL_EEH_PCI_TA = 5,
OPAL_EEH_PCIEX_UR = 6,
OPAL_EEH_PCIEX_CA = 7,
OPAL_EEH_PCI_MMIO_ERROR = 8,
OPAL_EEH_PCI_DMA_ERROR = 9
};
enum OpalShpcAction {
OPAL_SHPC_GET_LINK_STATE = 0,
OPAL_SHPC_GET_SLOT_STATE = 1
};
enum OpalShpcLinkState {
OPAL_SHPC_LINK_DOWN = 0,
OPAL_SHPC_LINK_UP = 1
};
enum OpalMmioWindowType {
OPAL_M32_WINDOW_TYPE = 1,
OPAL_M64_WINDOW_TYPE = 2,
OPAL_IO_WINDOW_TYPE = 3
};
enum OpalShpcSlotState {
OPAL_SHPC_DEV_NOT_PRESENT = 0,
OPAL_SHPC_DEV_PRESENT = 1
};
enum OpalExceptionHandler {
OPAL_MACHINE_CHECK_HANDLER = 1,
OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
OPAL_SOFTPATCH_HANDLER = 3
};
enum OpalPendingState {
OPAL_EVENT_OPAL_INTERNAL = 0x1,
OPAL_EVENT_NVRAM = 0x2,
OPAL_EVENT_RTC = 0x4,
OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
OPAL_EVENT_CONSOLE_INPUT = 0x10
};
/* Machine check related definitions */
enum OpalMCE_Version {
OpalMCE_V1 = 1,
};
enum OpalMCE_Severity {
OpalMCE_SEV_NO_ERROR = 0,
OpalMCE_SEV_WARNING = 1,
OpalMCE_SEV_ERROR_SYNC = 2,
OpalMCE_SEV_FATAL = 3,
};
enum OpalMCE_Disposition {
OpalMCE_DISPOSITION_RECOVERED = 0,
OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
};
enum OpalMCE_Initiator {
OpalMCE_INITIATOR_UNKNOWN = 0,
OpalMCE_INITIATOR_CPU = 1,
};
enum OpalMCE_ErrorType {
OpalMCE_ERROR_TYPE_UNKNOWN = 0,
OpalMCE_ERROR_TYPE_UE = 1,
OpalMCE_ERROR_TYPE_SLB = 2,
OpalMCE_ERROR_TYPE_ERAT = 3,
OpalMCE_ERROR_TYPE_TLB = 4,
};
enum OpalMCE_UeErrorType {
OpalMCE_UE_ERROR_INDETERMINATE = 0,
OpalMCE_UE_ERROR_IFETCH = 1,
OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
OpalMCE_UE_ERROR_LOAD_STORE = 3,
OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
};
enum OpalMCE_SlbErrorType {
OpalMCE_SLB_ERROR_INDETERMINATE = 0,
OpalMCE_SLB_ERROR_PARITY = 1,
OpalMCE_SLB_ERROR_MULTIHIT = 2,
};
enum OpalMCE_EratErrorType {
OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
OpalMCE_ERAT_ERROR_PARITY = 1,
OpalMCE_ERAT_ERROR_MULTIHIT = 2,
};
enum OpalMCE_TlbErrorType {
OpalMCE_TLB_ERROR_INDETERMINATE = 0,
OpalMCE_TLB_ERROR_PARITY = 1,
OpalMCE_TLB_ERROR_MULTIHIT = 2,
};
enum OpalThreadStatus {
OPAL_THREAD_INACTIVE = 0x0,
OPAL_THREAD_STARTED = 0x1
};
enum OpalPciBusCompare {
OpalPciBusAny = 0, /* Any bus number match */
OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
OpalPciBusAll = 7, /* Match bus number exactly */
};
enum OpalDeviceCompare {
OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
OPAL_COMPARE_RID_DEVICE_NUMBER = 1
};
enum OpalFuncCompare {
OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
};
enum OpalPeAction {
OPAL_UNMAP_PE = 0,
OPAL_MAP_PE = 1
};
enum OpalPciResetAndReinitScope {
OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
OPAL_PCI_IODA_RESET = 6,
};
enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };
struct opal_machine_check_event {
enum OpalMCE_Version version:8; /* 0x00 */
uint8_t in_use; /* 0x01 */
enum OpalMCE_Severity severity:8; /* 0x02 */
enum OpalMCE_Initiator initiator:8; /* 0x03 */
enum OpalMCE_ErrorType error_type:8; /* 0x04 */
enum OpalMCE_Disposition disposition:8; /* 0x05 */
uint8_t reserved_1[2]; /* 0x06 */
uint64_t gpr3; /* 0x08 */
uint64_t srr0; /* 0x10 */
uint64_t srr1; /* 0x18 */
union { /* 0x20 */
struct {
enum OpalMCE_UeErrorType ue_error_type:8;
uint8_t effective_address_provided;
uint8_t physical_address_provided;
uint8_t reserved_1[5];
uint64_t effective_address;
uint64_t physical_address;
uint8_t reserved_2[8];
} ue_error;
struct {
enum OpalMCE_SlbErrorType slb_error_type:8;
uint8_t effective_address_provided;
uint8_t reserved_1[6];
uint64_t effective_address;
uint8_t reserved_2[16];
} slb_error;
struct {
enum OpalMCE_EratErrorType erat_error_type:8;
uint8_t effective_address_provided;
uint8_t reserved_1[6];
uint64_t effective_address;
uint8_t reserved_2[16];
} erat_error;
struct {
enum OpalMCE_TlbErrorType tlb_error_type:8;
uint8_t effective_address_provided;
uint8_t reserved_1[6];
uint64_t effective_address;
uint8_t reserved_2[16];
} tlb_error;
} u;
};
typedef struct oppanel_line {
/* XXX */
} oppanel_line_t;
/* API functions */
int64_t opal_console_write(int64_t term_number, int64_t *length,
const uint8_t *buffer);
int64_t opal_console_read(int64_t term_number, int64_t *length,
uint8_t *buffer);
int64_t opal_console_write_buffer_space(int64_t term_number,
int64_t *length);
int64_t opal_rtc_read(uint32_t *year_month_day,
uint64_t *hour_minute_second_millisecond);
int64_t opal_rtc_write(uint32_t year_month_day,
uint64_t hour_minute_second_millisecond);
int64_t opal_cec_power_down(uint64_t request);
int64_t opal_cec_reboot(void);
int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
int64_t opal_poll_events(uint64_t *outstanding_event_mask);
int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
uint64_t tce_mem_size);
int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
uint64_t tce_mem_size);
int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
uint64_t offset, uint8_t *data);
int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
uint64_t offset, uint16_t *data);
int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
uint64_t offset, uint32_t *data);
int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
uint64_t offset, uint8_t data);
int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
uint64_t offset, uint16_t data);
int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
uint64_t offset, uint32_t data);
int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
int64_t opal_register_exception_handler(uint64_t opal_exception,
uint64_t handler_address,
uint64_t glue_cache_line);
int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
uint8_t *freeze_state,
uint16_t *pci_error_type,
uint64_t *phb_status);
int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
uint64_t eeh_action_token);
int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
uint16_t window_num, uint16_t enable);
int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
uint16_t window_num,
uint64_t starting_real_address,
uint64_t starting_pci_address,
uint16_t segment_size);
int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
uint16_t window_type, uint16_t window_num,
uint16_t segment_num);
int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
uint64_t ivt_addr, uint64_t ivt_len,
uint64_t reject_array_addr,
uint64_t peltv_addr);
int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
uint8_t pe_action);
int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
uint8_t state);
int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
uint32_t state);
int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
uint8_t *p_bit, uint8_t *q_bit);
int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
uint8_t p_bit, uint8_t q_bit);
int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
uint32_t xive_num);
int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
int32_t *interrupt_source_number);
int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
uint8_t msi_range, uint32_t *msi_address,
uint32_t *message_data);
int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
uint32_t xive_num, uint8_t msi_range,
uint64_t *msi_address, uint32_t *message_data);
int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
uint16_t tce_levels, uint64_t tce_table_addr,
uint64_t tce_table_size, uint64_t tce_page_size);
int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
uint16_t dma_window_number, uint64_t pci_start_addr,
uint64_t pci_mem_size);
int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
extern void hvc_opal_init_early(void);
/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
int depth, void *data);
extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
extern void hvc_opal_init_early(void);
struct rtc_time;
extern int opal_set_rtc_time(struct rtc_time *tm);
extern void opal_get_rtc_time(struct rtc_time *tm);
extern unsigned long opal_get_boot_time(void);
extern void opal_nvram_init(void);
extern int opal_machine_check(struct pt_regs *regs);
#endif /* __ASSEMBLY__ */
#endif /* __OPAL_H */

8
arch/powerpc/include/asm/paca.h
View File

@ -43,6 +43,7 @@ extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
struct task_struct;
struct opal_machine_check_event;
/*
* Defines the layout of the paca.
@ -135,6 +136,13 @@ struct paca_struct {
u8 io_sync; /* writel() needs spin_unlock sync */
u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
#ifdef CONFIG_PPC_POWERNV
/* Pointer to OPAL machine check event structure set by the
* early exception handler for use by high level C handler
*/
struct opal_machine_check_event *opal_mc_evt;
#endif
/* Stuff for accurate time accounting */
u64 user_time; /* accumulated usermode TB ticks */
u64 system_time; /* accumulated system TB ticks */

31
arch/powerpc/include/asm/page.h
View File

@ -36,6 +36,18 @@
#define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT)
#ifndef __ASSEMBLY__
#ifdef CONFIG_HUGETLB_PAGE
extern unsigned int HPAGE_SHIFT;
#else
#define HPAGE_SHIFT PAGE_SHIFT
#endif
#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
#define HUGE_MAX_HSTATE (MMU_PAGE_COUNT-1)
#endif
/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
#define __HAVE_ARCH_GATE_AREA 1
@ -158,6 +170,24 @@ extern phys_addr_t kernstart_addr;
#define is_kernel_addr(x) ((x) >= PAGE_OFFSET)
#endif
/*
* Use the top bit of the higher-level page table entries to indicate whether
* the entries we point to contain hugepages. This works because we know that
* the page tables live in kernel space. If we ever decide to support having
* page tables at arbitrary addresses, this breaks and will have to change.
*/
#ifdef CONFIG_PPC64
#define PD_HUGE 0x8000000000000000
#else
#define PD_HUGE 0x80000000
#endif
/*
* Some number of bits at the level of the page table that points to
* a hugepte are used to encode the size. This masks those bits.
*/
#define HUGEPD_SHIFT_MASK 0x3f
#ifndef __ASSEMBLY__
#undef STRICT_MM_TYPECHECKS
@ -243,7 +273,6 @@ typedef unsigned long pgprot_t;
#endif
typedef struct { signed long pd; } hugepd_t;
#define HUGEPD_SHIFT_MASK 0x3f
#ifdef CONFIG_HUGETLB_PAGE
static inline int hugepd_ok(hugepd_t hpd)

11
arch/powerpc/include/asm/page_64.h
View File

@ -64,17 +64,6 @@ extern void copy_page(void *to, void *from);
/* Log 2 of page table size */
extern u64 ppc64_pft_size;
/* Large pages size */
#ifdef CONFIG_HUGETLB_PAGE
extern unsigned int HPAGE_SHIFT;
#else
#define HPAGE_SHIFT PAGE_SHIFT
#endif
#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
#define HUGE_MAX_HSTATE (MMU_PAGE_COUNT-1)
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_PPC_MM_SLICES

3
arch/powerpc/include/asm/pte-book3e.h
View File

@ -72,6 +72,9 @@
#define PTE_RPN_SHIFT (24)
#endif
#define PTE_WIMGE_SHIFT (19)
#define PTE_BAP_SHIFT (2)
/* On 32-bit, we never clear the top part of the PTE */
#ifdef CONFIG_PPC32
#define _PTE_NONE_MASK 0xffffffff00000000ULL

3
arch/powerpc/include/asm/reg_booke.h
View File

@ -548,6 +548,9 @@
#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
/* Bit definitions for L1CSR2. */
#define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */
/* Bit definitions for L2CSR0. */
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */

6
arch/powerpc/include/asm/rtas.h
View File

@ -249,10 +249,12 @@ extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
#define ERR_FLAG_ALREADY_LOGGED 0x0
#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */
#define ERR_TYPE_RTAS_LOG 0x2 /* from rtas event-scan */
#define ERR_TYPE_KERNEL_PANIC 0x4 /* from panic() */
#define ERR_TYPE_KERNEL_PANIC 0x4 /* from die()/panic() */
#define ERR_TYPE_KERNEL_PANIC_GZ 0x8 /* ditto, compressed */
/* All the types and not flags */
#define ERR_TYPE_MASK (ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC)
#define ERR_TYPE_MASK \
(ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC | ERR_TYPE_KERNEL_PANIC_GZ)
#define RTAS_DEBUG KERN_DEBUG "RTAS: "

1
arch/powerpc/include/asm/smp.h
View File

@ -65,6 +65,7 @@ int generic_cpu_disable(void);
void generic_cpu_die(unsigned int cpu);
void generic_mach_cpu_die(void);
void generic_set_cpu_dead(unsigned int cpu);
int generic_check_cpu_restart(unsigned int cpu);
#endif
#ifdef CONFIG_PPC64

2
arch/powerpc/include/asm/sparsemem.h
View File

@ -16,7 +16,7 @@
#endif /* CONFIG_SPARSEMEM */
#ifdef CONFIG_MEMORY_HOTPLUG
extern void create_section_mapping(unsigned long start, unsigned long end);
extern int create_section_mapping(unsigned long start, unsigned long end);
extern int remove_section_mapping(unsigned long start, unsigned long end);
#ifdef CONFIG_NUMA
extern int hot_add_scn_to_nid(unsigned long scn_addr);

14
arch/powerpc/include/asm/topology.h
View File

@ -19,14 +19,10 @@ struct device_node;
#define RECLAIM_DISTANCE 10
/*
* Before going off node we want the VM to try and reclaim from the local
* node. It does this if the remote distance is larger than RECLAIM_DISTANCE.
* With the default REMOTE_DISTANCE of 20 and the default RECLAIM_DISTANCE of
* 20, we never reclaim and go off node straight away.
*
* To fix this we choose a smaller value of RECLAIM_DISTANCE.
* Avoid creating an extra level of balancing (SD_ALLNODES) on the largest
* POWER7 boxes which have a maximum of 32 nodes.
*/
#define RECLAIM_DISTANCE 10
#define SD_NODES_PER_DOMAIN 32
#include <asm/mmzone.h>
@ -69,11 +65,11 @@ static inline int pcibus_to_node(struct pci_bus *bus)
.forkexec_idx = 0, \
\
.flags = 1*SD_LOAD_BALANCE \
| 1*SD_BALANCE_NEWIDLE \
| 0*SD_BALANCE_NEWIDLE \
| 1*SD_BALANCE_EXEC \
| 1*SD_BALANCE_FORK \
| 0*SD_BALANCE_WAKE \
| 0*SD_WAKE_AFFINE \
| 1*SD_WAKE_AFFINE \
| 0*SD_PREFER_LOCAL \
| 0*SD_SHARE_CPUPOWER \
| 0*SD_POWERSAVINGS_BALANCE \

3
arch/powerpc/include/asm/udbg.h
View File

@ -55,6 +55,9 @@ extern void __init udbg_init_cpm(void);
extern void __init udbg_init_usbgecko(void);
extern void __init udbg_init_wsp(void);
extern void __init udbg_init_ehv_bc(void);
extern void __init udbg_init_ps3gelic(void);
extern void __init udbg_init_debug_opal_raw(void);
extern void __init udbg_init_debug_opal_hvsi(void);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_UDBG_H */

19
arch/powerpc/include/asm/xics.h
View File

@ -27,10 +27,18 @@
#define MAX_NUM_PRIORITIES 3
/* Native ICP */
#ifdef CONFIG_PPC_ICP_NATIVE
extern int icp_native_init(void);
#else
static inline int icp_native_init(void) { return -ENODEV; }
#endif
/* PAPR ICP */
#ifdef CONFIG_PPC_ICP_HV
extern int icp_hv_init(void);
#else
static inline int icp_hv_init(void) { return -ENODEV; }
#endif
/* ICP ops */
struct icp_ops {
@ -51,7 +59,18 @@ extern const struct icp_ops *icp_ops;
extern int ics_native_init(void);
/* RTAS ICS */
#ifdef CONFIG_PPC_ICS_RTAS
extern int ics_rtas_init(void);
#else
static inline int ics_rtas_init(void) { return -ENODEV; }
#endif
/* HAL ICS */
#ifdef CONFIG_PPC_POWERNV
extern int ics_opal_init(void);
#else
static inline int ics_opal_init(void) { return -ENODEV; }
#endif
/* ICS instance, hooked up to chip_data of an irq */
struct ics {

10
arch/powerpc/kernel/asm-offsets.c
View File

@ -49,6 +49,9 @@
#ifdef CONFIG_PPC_ISERIES
#include <asm/iseries/alpaca.h>
#endif
#ifdef CONFIG_PPC_POWERNV
#include <asm/opal.h>
#endif
#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
#include <linux/kvm_host.h>
#endif
@ -610,5 +613,12 @@ int main(void)
arch.timing_last_enter.tv32.tbl));
#endif
#ifdef CONFIG_PPC_POWERNV
DEFINE(OPAL_MC_GPR3, offsetof(struct opal_machine_check_event, gpr3));
DEFINE(OPAL_MC_SRR0, offsetof(struct opal_machine_check_event, srr0));
DEFINE(OPAL_MC_SRR1, offsetof(struct opal_machine_check_event, srr1));
DEFINE(PACA_OPAL_MC_EVT, offsetof(struct paca_struct, opal_mc_evt));
#endif
return 0;
}

28
arch/powerpc/kernel/dma-iommu.c
View File

@ -90,13 +90,27 @@ static int dma_iommu_dma_supported(struct device *dev, u64 mask)
return 1;
}
static u64 dma_iommu_get_required_mask(struct device *dev)
{
struct iommu_table *tbl = get_iommu_table_base(dev);
u64 mask;
if (!tbl)
return 0;
mask = 1ULL < (fls_long(tbl->it_offset + tbl->it_size) - 1);
mask += mask - 1;
return mask;
}
struct dma_map_ops dma_iommu_ops = {
.alloc_coherent = dma_iommu_alloc_coherent,
.free_coherent = dma_iommu_free_coherent,
.map_sg = dma_iommu_map_sg,
.unmap_sg = dma_iommu_unmap_sg,
.dma_supported = dma_iommu_dma_supported,
.map_page = dma_iommu_map_page,
.unmap_page = dma_iommu_unmap_page,
.alloc_coherent = dma_iommu_alloc_coherent,
.free_coherent = dma_iommu_free_coherent,
.map_sg = dma_iommu_map_sg,
.unmap_sg = dma_iommu_unmap_sg,
.dma_supported = dma_iommu_dma_supported,
.map_page = dma_iommu_map_page,
.unmap_page = dma_iommu_unmap_page,
.get_required_mask = dma_iommu_get_required_mask,
};
EXPORT_SYMBOL(dma_iommu_ops);

16
arch/powerpc/kernel/dma-swiotlb.c
View File

@ -24,6 +24,21 @@
unsigned int ppc_swiotlb_enable;
static u64 swiotlb_powerpc_get_required(struct device *dev)
{
u64 end, mask, max_direct_dma_addr = dev->archdata.max_direct_dma_addr;
end = memblock_end_of_DRAM();
if (max_direct_dma_addr && end > max_direct_dma_addr)
end = max_direct_dma_addr;
end += get_dma_offset(dev);
mask = 1ULL << (fls64(end) - 1);
mask += mask - 1;
return mask;
}
/*
* At the moment, all platforms that use this code only require
* swiotlb to be used if we're operating on HIGHMEM. Since
@ -44,6 +59,7 @@ struct dma_map_ops swiotlb_dma_ops = {
.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
.sync_sg_for_device = swiotlb_sync_sg_for_device,
.mapping_error = swiotlb_dma_mapping_error,
.get_required_mask = swiotlb_powerpc_get_required,
};
void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev)

44
arch/powerpc/kernel/dma.c
View File

@ -96,6 +96,18 @@ static int dma_direct_dma_supported(struct device *dev, u64 mask)
#endif
}
static u64 dma_direct_get_required_mask(struct device *dev)
{
u64 end, mask;
end = memblock_end_of_DRAM() + get_dma_offset(dev);
mask = 1ULL << (fls64(end) - 1);
mask += mask - 1;
return mask;
}
static inline dma_addr_t dma_direct_map_page(struct device *dev,
struct page *page,
unsigned long offset,
@ -137,13 +149,14 @@ static inline void dma_direct_sync_single(struct device *dev,
#endif
struct dma_map_ops dma_direct_ops = {
.alloc_coherent = dma_direct_alloc_coherent,
.free_coherent = dma_direct_free_coherent,
.map_sg = dma_direct_map_sg,
.unmap_sg = dma_direct_unmap_sg,
.dma_supported = dma_direct_dma_supported,
.map_page = dma_direct_map_page,
.unmap_page = dma_direct_unmap_page,
.alloc_coherent = dma_direct_alloc_coherent,
.free_coherent = dma_direct_free_coherent,
.map_sg = dma_direct_map_sg,
.unmap_sg = dma_direct_unmap_sg,
.dma_supported = dma_direct_dma_supported,
.map_page = dma_direct_map_page,
.unmap_page = dma_direct_unmap_page,
.get_required_mask = dma_direct_get_required_mask,
#ifdef CONFIG_NOT_COHERENT_CACHE
.sync_single_for_cpu = dma_direct_sync_single,
.sync_single_for_device = dma_direct_sync_single,
@ -170,6 +183,23 @@ int dma_set_mask(struct device *dev, u64 dma_mask)
}
EXPORT_SYMBOL(dma_set_mask);
u64 dma_get_required_mask(struct device *dev)
{
struct dma_map_ops *dma_ops = get_dma_ops(dev);
if (ppc_md.dma_get_required_mask)
return ppc_md.dma_get_required_mask(dev);
if (unlikely(dma_ops == NULL))
return 0;
if (dma_ops->get_required_mask)
return dma_ops->get_required_mask(dev);
return DMA_BIT_MASK(8 * sizeof(dma_addr_t));
}
EXPORT_SYMBOL_GPL(dma_get_required_mask);
static int __init dma_init(void)
{
dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);

27
arch/powerpc/kernel/exceptions-64s.S
View File

@ -1133,7 +1133,7 @@ _GLOBAL(do_stab_bolted)
rfid
b . /* prevent speculative execution */
#ifdef CONFIG_PPC_PSERIES
#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
/*
* Data area reserved for FWNMI option.
* This address (0x7000) is fixed by the RPA.
@ -1141,7 +1141,7 @@ _GLOBAL(do_stab_bolted)
.= 0x7000
.globl fwnmi_data_area
fwnmi_data_area:
#endif /* CONFIG_PPC_PSERIES */
#endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */
/* iSeries does not use the FWNMI stuff, so it is safe to put
* this here, even if we later allow kernels that will boot on
@ -1166,9 +1166,12 @@ xLparMap:
#endif /* CONFIG_PPC_ISERIES */
#ifdef CONFIG_PPC_PSERIES
#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
/* pseries and powernv need to keep the whole page from
* 0x7000 to 0x8000 free for use by the firmware
*/
. = 0x8000
#endif /* CONFIG_PPC_PSERIES */
#endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */
/*
* Space for CPU0's segment table.
@ -1183,3 +1186,19 @@ xLparMap:
.globl initial_stab
initial_stab:
.space 4096
#ifdef CONFIG_PPC_POWERNV
_GLOBAL(opal_mc_secondary_handler)
HMT_MEDIUM
SET_SCRATCH0(r13)
GET_PACA(r13)
clrldi r3,r3,2
tovirt(r3,r3)
std r3,PACA_OPAL_MC_EVT(r13)
ld r13,OPAL_MC_SRR0(r3)
mtspr SPRN_SRR0,r13
ld r13,OPAL_MC_SRR1(r3)
mtspr SPRN_SRR1,r13
ld r3,OPAL_MC_GPR3(r3)
GET_SCRATCH0(r13)
b machine_check_pSeries
#endif /* CONFIG_PPC_POWERNV */

7
arch/powerpc/kernel/head_32.S
View File

@ -139,8 +139,7 @@ __start:
trap
#endif /* CONFIG_PPC_PMAC */
1: mr r31,r3 /* save parameters */
mr r30,r4
1: mr r31,r3 /* save device tree ptr */
li r24,0 /* cpu # */
/*
@ -964,8 +963,8 @@ start_here:
* Do early platform-specific initialization,
* and set up the MMU.
*/
mr r3,r31
mr r4,r30
li r3,0
mr r4,r31
bl machine_init
bl __save_cpu_setup
bl MMU_init

15
arch/powerpc/kernel/head_40x.S
View File

@ -58,13 +58,7 @@
_ENTRY(_stext);
_ENTRY(_start);
/* Save parameters we are passed.
*/
mr r31,r3
mr r30,r4
mr r29,r5
mr r28,r6
mr r27,r7
mr r31,r3 /* save device tree ptr */
/* We have to turn on the MMU right away so we get cache modes
* set correctly.
@ -849,11 +843,8 @@ start_here:
/*
* Decide what sort of machine this is and initialize the MMU.
*/
mr r3,r31
mr r4,r30
mr r5,r29
mr r6,r28
mr r7,r27
li r3,0
mr r4,r31
bl machine_init
bl MMU_init

16
arch/powerpc/kernel/head_44x.S
View File

@ -61,14 +61,7 @@ _ENTRY(_start);
* of abatron_pteptrs
*/
nop
/*
* Save parameters we are passed
*/
mr r31,r3
mr r30,r4
mr r29,r5
mr r28,r6
mr r27,r7
mr r31,r3 /* save device tree ptr */
li r24,0 /* CPU number */
bl init_cpu_state
@ -120,11 +113,8 @@ _ENTRY(_start);
/*
* Decide what sort of machine this is and initialize the MMU.
*/
mr r3,r31
mr r4,r30
mr r5,r29
mr r6,r28
mr r7,r27
li r3,0
mr r4,r31
bl machine_init
bl MMU_init

22
arch/powerpc/kernel/head_64.S
View File

@ -51,6 +51,11 @@
* For pSeries or server processors:
* 1. The MMU is off & open firmware is running in real mode.
* 2. The kernel is entered at __start
* -or- For OPAL entry:
* 1. The MMU is off, processor in HV mode, primary CPU enters at 0
* with device-tree in gpr3. We also get OPAL base in r8 and
* entry in r9 for debugging purposes
* 2. Secondary processors enter at 0x60 with PIR in gpr3
*
* For iSeries:
* 1. The MMU is on (as it always is for iSeries)
@ -331,6 +336,11 @@ _GLOBAL(__start_initialization_multiplatform)
/* Save parameters */
mr r31,r3
mr r30,r4
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
/* Save OPAL entry */
mr r28,r8
mr r29,r9
#endif
#ifdef CONFIG_PPC_BOOK3E
bl .start_initialization_book3e
@ -674,9 +684,9 @@ _GLOBAL(enable_64b_mode)
_GLOBAL(relative_toc)
mflr r0
bcl 20,31,$+4
0: mflr r9
ld r2,(p_toc - 0b)(r9)
add r2,r2,r9
0: mflr r11
ld r2,(p_toc - 0b)(r11)
add r2,r2,r11
mtlr r0
blr
@ -707,6 +717,12 @@ _INIT_STATIC(start_here_multiplatform)
bdnz 3b
4:
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
/* Setup OPAL entry */
std r28,0(r11);
std r29,8(r11);
#endif
#ifndef CONFIG_PPC_BOOK3E
mfmsr r6
ori r6,r6,MSR_RI

13
arch/powerpc/kernel/head_8xx.S
View File

@ -76,11 +76,7 @@ _ENTRY(_start);
*/
.globl __start
__start:
mr r31,r3 /* save parameters */
mr r30,r4
mr r29,r5
mr r28,r6
mr r27,r7
mr r31,r3 /* save device tree ptr */
/* We have to turn on the MMU right away so we get cache modes
* set correctly.
@ -723,11 +719,8 @@ start_here:
/*
* Decide what sort of machine this is and initialize the MMU.
*/
mr r3,r31
mr r4,r30
mr r5,r29
mr r6,r28
mr r7,r27
li r3,0
mr r4,r31
bl machine_init
bl MMU_init

175
arch/powerpc/kernel/head_fsl_booke.S
View File

@ -63,17 +63,30 @@ _ENTRY(_start);
* of abatron_pteptrs
*/
nop
/*
* Save parameters we are passed
*/
mr r31,r3
mr r30,r4
mr r29,r5
mr r28,r6
mr r27,r7
li r25,0 /* phys kernel start (low) */
li r24,0 /* CPU number */
li r23,0 /* phys kernel start (high) */
/* Translate device tree address to physical, save in r30/r31 */
mfmsr r16
mfspr r17,SPRN_PID
rlwinm r17,r17,16,0x3fff0000 /* turn PID into MAS6[SPID] */
rlwimi r17,r16,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
mtspr SPRN_MAS6,r17
tlbsx 0,r3 /* must succeed */
mfspr r16,SPRN_MAS1
mfspr r20,SPRN_MAS3
rlwinm r17,r16,25,0x1f /* r17 = log2(page size) */
li r18,1024
slw r18,r18,r17 /* r18 = page size */
addi r18,r18,-1
and r19,r3,r18 /* r19 = page offset */
andc r31,r20,r18 /* r31 = page base */
or r31,r31,r19 /* r31 = devtree phys addr */
mfspr r30,SPRN_MAS7
li r25,0 /* phys kernel start (low) */
li r24,0 /* CPU number */
li r23,0 /* phys kernel start (high) */
/* We try to not make any assumptions about how the boot loader
* setup or used the TLBs. We invalidate all mappings from the
@ -198,11 +211,8 @@ _ENTRY(__early_start)
/*
* Decide what sort of machine this is and initialize the MMU.
*/
mr r3,r31
mr r4,r30
mr r5,r29
mr r6,r28
mr r7,r27
mr r3,r30
mr r4,r31
bl machine_init
bl MMU_init
@ -236,8 +246,24 @@ _ENTRY(__early_start)
* if we find the pte (fall through):
* r11 is low pte word
* r12 is pointer to the pte
* r10 is the pshift from the PGD, if we're a hugepage
*/
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_HUGETLB_PAGE
#define FIND_PTE \
rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
blt 1000f; /* Normal non-huge page */ \
beq 2f; /* Bail if no table */ \
oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
xor r12, r10, r11; /* drop size bits from pointer */ \
b 1001f; \
1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
li r10, 0; /* clear r10 */ \
1001: lwz r11, 4(r12); /* Get pte entry */
#else
#define FIND_PTE \
rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
@ -245,7 +271,8 @@ _ENTRY(__early_start)
beq 2f; /* Bail if no table */ \
rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
lwz r11, 4(r12); /* Get pte entry */
#else
#endif /* HUGEPAGE */
#else /* !PTE_64BIT */
#define FIND_PTE \
rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
lwz r11, 0(r11); /* Get L1 entry */ \
@ -402,8 +429,8 @@ interrupt_base:
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_SMP
subf r10,r11,r12 /* create false data dep */
lwzx r13,r11,r10 /* Get upper pte bits */
subf r13,r11,r12 /* create false data dep */
lwzx r13,r11,r13 /* Get upper pte bits */
#else
lwz r13,0(r12) /* Get upper pte bits */
#endif
@ -483,8 +510,8 @@ interrupt_base:
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_SMP
subf r10,r11,r12 /* create false data dep */
lwzx r13,r11,r10 /* Get upper pte bits */
subf r13,r11,r12 /* create false data dep */
lwzx r13,r11,r13 /* Get upper pte bits */
#else
lwz r13,0(r12) /* Get upper pte bits */
#endif
@ -548,7 +575,7 @@ interrupt_base:
/*
* Both the instruction and data TLB miss get to this
* point to load the TLB.
* r10 - available to use
* r10 - tsize encoding (if HUGETLB_PAGE) or available to use
* r11 - TLB (info from Linux PTE)
* r12 - available to use
* r13 - upper bits of PTE (if PTE_64BIT) or available to use
@ -558,21 +585,73 @@ interrupt_base:
* Upon exit, we reload everything and RFI.
*/
finish_tlb_load:
#ifdef CONFIG_HUGETLB_PAGE
cmpwi 6, r10, 0 /* check for huge page */
beq 6, finish_tlb_load_cont /* !huge */
/* Alas, we need more scratch registers for hugepages */
mfspr r12, SPRN_SPRG_THREAD
stw r14, THREAD_NORMSAVE(4)(r12)
stw r15, THREAD_NORMSAVE(5)(r12)
stw r16, THREAD_NORMSAVE(6)(r12)
stw r17, THREAD_NORMSAVE(7)(r12)
/* Get the next_tlbcam_idx percpu var */
#ifdef CONFIG_SMP
lwz r12, THREAD_INFO-THREAD(r12)
lwz r15, TI_CPU(r12)
lis r14, __per_cpu_offset@h
ori r14, r14, __per_cpu_offset@l
rlwinm r15, r15, 2, 0, 29
lwzx r16, r14, r15
#else
li r16, 0
#endif
lis r17, next_tlbcam_idx@h
ori r17, r17, next_tlbcam_idx@l
add r17, r17, r16 /* r17 = *next_tlbcam_idx */
lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
mtspr SPRN_MAS0, r14
/* Extract TLB1CFG(NENTRY) */
mfspr r16, SPRN_TLB1CFG
andi. r16, r16, 0xfff
/* Update next_tlbcam_idx, wrapping when necessary */
addi r15, r15, 1
cmpw r15, r16
blt 100f
lis r14, tlbcam_index@h
ori r14, r14, tlbcam_index@l
lwz r15, 0(r14)
100: stw r15, 0(r17)
/*
* Calc MAS1_TSIZE from r10 (which has pshift encoded)
* tlb_enc = (pshift - 10).
*/
subi r15, r10, 10
mfspr r16, SPRN_MAS1
rlwimi r16, r15, 7, 20, 24
mtspr SPRN_MAS1, r16
/* copy the pshift for use later */
mr r14, r10
/* fall through */
#endif /* CONFIG_HUGETLB_PAGE */
/*
* We set execute, because we don't have the granularity to
* properly set this at the page level (Linux problem).
* Many of these bits are software only. Bits we don't set
* here we (properly should) assume have the appropriate value.
*/
mfspr r12, SPRN_MAS2
#ifdef CONFIG_PTE_64BIT
rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
#else
rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
#endif
mtspr SPRN_MAS2, r12
finish_tlb_load_cont:
#ifdef CONFIG_PTE_64BIT
rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
andi. r10, r11, _PAGE_DIRTY
@ -581,22 +660,40 @@ finish_tlb_load:
andc r12, r12, r10
1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
mtspr SPRN_MAS3, r12
2: mtspr SPRN_MAS3, r12
BEGIN_MMU_FTR_SECTION
srwi r10, r13, 12 /* grab RPN[12:31] */
mtspr SPRN_MAS7, r10
END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
#else
li r10, (_PAGE_EXEC | _PAGE_PRESENT)
mr r13, r11
rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
and r12, r11, r10
andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
slwi r10, r12, 1
or r10, r10, r12
iseleq r12, r12, r10
rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
mtspr SPRN_MAS3, r11
rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
mtspr SPRN_MAS3, r13
#endif
mfspr r12, SPRN_MAS2
#ifdef CONFIG_PTE_64BIT
rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
#else
rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
#endif
#ifdef CONFIG_HUGETLB_PAGE
beq 6, 3f /* don't mask if page isn't huge */
li r13, 1
slw r13, r13, r14
subi r13, r13, 1
rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
andc r12, r12, r13 /* mask off ea bits within the page */
#endif
3: mtspr SPRN_MAS2, r12
#ifdef CONFIG_E200
/* Round robin TLB1 entries assignment */
mfspr r12, SPRN_MAS0
@ -622,11 +719,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
mtspr SPRN_MAS0,r12
#endif /* CONFIG_E200 */
tlb_write_entry:
tlbwe
/* Done...restore registers and get out of here. */
mfspr r10, SPRN_SPRG_THREAD
lwz r11, THREAD_NORMSAVE(3)(r10)
#ifdef CONFIG_HUGETLB_PAGE
beq 6, 8f /* skip restore for 4k page faults */
lwz r14, THREAD_NORMSAVE(4)(r10)
lwz r15, THREAD_NORMSAVE(5)(r10)
lwz r16, THREAD_NORMSAVE(6)(r10)
lwz r17, THREAD_NORMSAVE(7)(r10)
#endif
8: lwz r11, THREAD_NORMSAVE(3)(r10)
mtcr r11
lwz r13, THREAD_NORMSAVE(2)(r10)
lwz r12, THREAD_NORMSAVE(1)(r10)

22
arch/powerpc/kernel/ibmebus.c
View File

@ -125,17 +125,23 @@ static void ibmebus_unmap_sg(struct device *dev,
static int ibmebus_dma_supported(struct device *dev, u64 mask)
{
return 1;
return mask == DMA_BIT_MASK(64);
}
static u64 ibmebus_dma_get_required_mask(struct device *dev)
{
return DMA_BIT_MASK(64);
}
static struct dma_map_ops ibmebus_dma_ops = {
.alloc_coherent = ibmebus_alloc_coherent,
.free_coherent = ibmebus_free_coherent,
.map_sg = ibmebus_map_sg,
.unmap_sg = ibmebus_unmap_sg,
.dma_supported = ibmebus_dma_supported,
.map_page = ibmebus_map_page,
.unmap_page = ibmebus_unmap_page,
.alloc_coherent = ibmebus_alloc_coherent,
.free_coherent = ibmebus_free_coherent,
.map_sg = ibmebus_map_sg,
.unmap_sg = ibmebus_unmap_sg,
.dma_supported = ibmebus_dma_supported,
.get_required_mask = ibmebus_dma_get_required_mask,
.map_page = ibmebus_map_page,
.unmap_page = ibmebus_unmap_page,
};
static int ibmebus_match_path(struct device *dev, void *data)

2
arch/powerpc/kernel/idle_e500.S
View File

@ -26,7 +26,7 @@ _GLOBAL(e500_idle)
ori r4,r4,_TLF_NAPPING /* so when we take an exception */
stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */
#ifdef CONFIG_E500MC
#ifdef CONFIG_PPC_E500MC
wrteei 1
1: wait

8
arch/powerpc/kernel/iommu.c
View File

@ -501,6 +501,14 @@ struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
tbl->it_map = page_address(page);
memset(tbl->it_map, 0, sz);
/*
* Reserve page 0 so it will not be used for any mappings.
* This avoids buggy drivers that consider page 0 to be invalid
* to crash the machine or even lose data.
*/
if (tbl->it_offset == 0)
set_bit(0, tbl->it_map);
tbl->it_hint = 0;
tbl->it_largehint = tbl->it_halfpoint;
spin_lock_init(&tbl->it_lock);

25
arch/powerpc/kernel/legacy_serial.c
View File

@ -6,6 +6,7 @@
#include <linux/pci.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/serial_reg.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/prom.h>
@ -47,6 +48,24 @@ static struct __initdata of_device_id legacy_serial_parents[] = {
static unsigned int legacy_serial_count;
static int legacy_serial_console = -1;
static unsigned int tsi_serial_in(struct uart_port *p, int offset)
{
unsigned int tmp;
offset = offset << p->regshift;
if (offset == UART_IIR) {
tmp = readl(p->membase + (UART_IIR & ~3));
return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
} else
return readb(p->membase + offset);
}
static void tsi_serial_out(struct uart_port *p, int offset, int value)
{
offset = offset << p->regshift;
if (!((offset == UART_IER) && (value & UART_IER_UUE)))
writeb(value, p->membase + offset);
}
static int __init add_legacy_port(struct device_node *np, int want_index,
int iotype, phys_addr_t base,
phys_addr_t taddr, unsigned long irq,
@ -102,6 +121,7 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
legacy_serial_ports[index].iobase = base;
else
legacy_serial_ports[index].mapbase = base;
legacy_serial_ports[index].iotype = iotype;
legacy_serial_ports[index].uartclk = clock;
legacy_serial_ports[index].irq = irq;
@ -112,6 +132,11 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
legacy_serial_infos[index].speed = spd ? be32_to_cpup(spd) : 0;
legacy_serial_infos[index].irq_check_parent = irq_check_parent;
if (iotype == UPIO_TSI) {
legacy_serial_ports[index].serial_in = tsi_serial_in;
legacy_serial_ports[index].serial_out = tsi_serial_out;
}
printk(KERN_DEBUG "Found legacy serial port %d for %s\n",
index, np->full_name);
printk(KERN_DEBUG " %s=%llx, taddr=%llx, irq=%lx, clk=%d, speed=%d\n",

3
arch/powerpc/kernel/machine_kexec_64.c
View File

@ -74,8 +74,7 @@ int default_machine_kexec_prepare(struct kimage *image)
}
/* We also should not overwrite the tce tables */
for (node = of_find_node_by_type(NULL, "pci"); node != NULL;
node = of_find_node_by_type(node, "pci")) {
for_each_node_by_type(node, "pci") {
basep = of_get_property(node, "linux,tce-base", NULL);
sizep = of_get_property(node, "linux,tce-size", NULL);
if (basep == NULL || sizep == NULL)

171
arch/powerpc/kernel/misc_32.S
View File

@ -8,6 +8,8 @@
* kexec bits:
* Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
* GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
* PPC44x port. Copyright (C) 2011, IBM Corporation
* Author: Suzuki Poulose <suzuki@in.ibm.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -735,6 +737,175 @@ relocate_new_kernel:
mr r4, r30
mr r5, r31
li r0, 0
#elif defined(CONFIG_44x) && !defined(CONFIG_47x)
/*
* Code for setting up 1:1 mapping for PPC440x for KEXEC
*
* We cannot switch off the MMU on PPC44x.
* So we:
* 1) Invalidate all the mappings except the one we are running from.
* 2) Create a tmp mapping for our code in the other address space(TS) and
* jump to it. Invalidate the entry we started in.
* 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
* 4) Jump to the 1:1 mapping in original TS.
* 5) Invalidate the tmp mapping.
*
* - Based on the kexec support code for FSL BookE
* - Doesn't support 47x yet.
*
*/
/* Save our parameters */
mr r29, r3
mr r30, r4
mr r31, r5
/* Load our MSR_IS and TID to MMUCR for TLB search */
mfspr r3,SPRN_PID
mfmsr r4
andi. r4,r4,MSR_IS@l
beq wmmucr
oris r3,r3,PPC44x_MMUCR_STS@h
wmmucr:
mtspr SPRN_MMUCR,r3
sync
/*
* Invalidate all the TLB entries except the current entry
* where we are running from
*/
bl 0f /* Find our address */
0: mflr r5 /* Make it accessible */
tlbsx r23,0,r5 /* Find entry we are in */
li r4,0 /* Start at TLB entry 0 */
li r3,0 /* Set PAGEID inval value */
1: cmpw r23,r4 /* Is this our entry? */
beq skip /* If so, skip the inval */
tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
skip:
addi r4,r4,1 /* Increment */
cmpwi r4,64 /* Are we done? */
bne 1b /* If not, repeat */
isync
/* Create a temp mapping and jump to it */
andi. r6, r23, 1 /* Find the index to use */
addi r24, r6, 1 /* r24 will contain 1 or 2 */
mfmsr r9 /* get the MSR */
rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
xori r7, r5, 1 /* Use the other address space */
/* Read the current mapping entries */
tlbre r3, r23, PPC44x_TLB_PAGEID
tlbre r4, r23, PPC44x_TLB_XLAT
tlbre r5, r23, PPC44x_TLB_ATTRIB
/* Save our current XLAT entry */
mr r25, r4
/* Extract the TLB PageSize */
li r10, 1 /* r10 will hold PageSize */
rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
/* XXX: As of now we use 256M, 4K pages */
cmpwi r11, PPC44x_TLB_256M
bne tlb_4k
rotlwi r10, r10, 28 /* r10 = 256M */
b write_out
tlb_4k:
cmpwi r11, PPC44x_TLB_4K
bne default
rotlwi r10, r10, 12 /* r10 = 4K */
b write_out
default:
rotlwi r10, r10, 10 /* r10 = 1K */
write_out:
/*
* Write out the tmp 1:1 mapping for this code in other address space
* Fixup EPN = RPN , TS=other address space
*/
insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
/* Write out the tmp mapping entries */
tlbwe r3, r24, PPC44x_TLB_PAGEID
tlbwe r4, r24, PPC44x_TLB_XLAT
tlbwe r5, r24, PPC44x_TLB_ATTRIB
subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
not r10, r11 /* Mask for PageNum */
/* Switch to other address space in MSR */
insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
bl 1f
1: mflr r8
addi r8, r8, (2f-1b) /* Find the target offset */
/* Jump to the tmp mapping */
mtspr SPRN_SRR0, r8
mtspr SPRN_SRR1, r9
rfi
2:
/* Invalidate the entry we were executing from */
li r3, 0
tlbwe r3, r23, PPC44x_TLB_PAGEID
/* attribute fields. rwx for SUPERVISOR mode */
li r5, 0
ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
/* Create 1:1 mapping in 256M pages */
xori r7, r7, 1 /* Revert back to Original TS */
li r8, 0 /* PageNumber */
li r6, 3 /* TLB Index, start at 3 */
next_tlb:
rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
mr r4, r3 /* RPN = EPN */
ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
insrwi r3, r7, 1, 23 /* Set TS from r7 */
tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
addi r8, r8, 1 /* Increment PN */
addi r6, r6, 1 /* Increment TLB Index */
cmpwi r8, 8 /* Are we done ? */
bne next_tlb
isync
/* Jump to the new mapping 1:1 */
li r9,0
insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
bl 1f
1: mflr r8
and r8, r8, r11 /* Get our offset within page */
addi r8, r8, (2f-1b)
and r5, r25, r10 /* Get our target PageNum */
or r8, r8, r5 /* Target jump address */
mtspr SPRN_SRR0, r8
mtspr SPRN_SRR1, r9
rfi
2:
/* Invalidate the tmp entry we used */
li r3, 0
tlbwe r3, r24, PPC44x_TLB_PAGEID
sync
/* Restore the parameters */
mr r3, r29
mr r4, r30
mr r5, r31
li r0, 0
#else
li r0, 0

11
arch/powerpc/kernel/pci-common.c
View File

@ -1730,6 +1730,17 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
if (mode == PCI_PROBE_NORMAL)
hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
/* Configure PCI Express settings */
if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
struct pci_bus *child;
list_for_each_entry(child, &bus->children, node) {
struct pci_dev *self = child->self;
if (!self)
continue;
pcie_bus_configure_settings(child, self->pcie_mpss);
}
}
}
static void fixup_hide_host_resource_fsl(struct pci_dev *dev)

4
arch/powerpc/kernel/power6-pmu.c
View File

@ -487,8 +487,8 @@ static int power6_generic_events[] = {
*/
static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x80082, 0x80080 },
[C(OP_WRITE)] = { 0x80086, 0x80088 },
[C(OP_READ)] = { 0x280030, 0x80080 },
[C(OP_WRITE)] = { 0x180032, 0x80088 },
[C(OP_PREFETCH)] = { 0x810a4, 0 },
},
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */

2
arch/powerpc/kernel/power7-pmu.c
View File

@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
static int power7_generic_events[] = {
[PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */
[PERF_COUNT_HW_INSTRUCTIONS] = 2,
[PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/
[PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */

19
arch/powerpc/kernel/prom.c
View File

@ -54,6 +54,8 @@
#include <asm/pci-bridge.h>
#include <asm/phyp_dump.h>
#include <asm/kexec.h>
#include <asm/opal.h>
#include <mm/mmu_decl.h>
#ifdef DEBUG
@ -707,11 +709,23 @@ void __init early_init_devtree(void *params)
of_scan_flat_dt(early_init_dt_scan_rtas, NULL);
#endif
#ifdef CONFIG_PPC_POWERNV
/* Some machines might need OPAL info for debugging, grab it now. */
of_scan_flat_dt(early_init_dt_scan_opal, NULL);
#endif
#ifdef CONFIG_PHYP_DUMP
/* scan tree to see if dump occurred during last boot */
of_scan_flat_dt(early_init_dt_scan_phyp_dump, NULL);
#endif
/* Pre-initialize the cmd_line with the content of boot_commmand_line,
* which will be empty except when the content of the variable has
* been overriden by a bootloading mechanism. This happens typically
* with HAL takeover
*/
strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
/* Retrieve various informations from the /chosen node of the
* device-tree, including the platform type, initrd location and
* size, TCE reserve, and more ...
@ -723,12 +737,15 @@ void __init early_init_devtree(void *params)
of_scan_flat_dt(early_init_dt_scan_root, NULL);
of_scan_flat_dt(early_init_dt_scan_memory_ppc, NULL);
setup_initial_memory_limit(memstart_addr, first_memblock_size);
/* Save command line for /proc/cmdline and then parse parameters */
strlcpy(boot_command_line, cmd_line, COMMAND_LINE_SIZE);
parse_early_param();
/* make sure we've parsed cmdline for mem= before this */
if (memory_limit)
first_memblock_size = min(first_memblock_size, memory_limit);
setup_initial_memory_limit(memstart_addr, first_memblock_size);
/* Reserve MEMBLOCK regions used by kernel, initrd, dt, etc... */
memblock_reserve(PHYSICAL_START, __pa(klimit) - PHYSICAL_START);
/* If relocatable, reserve first 32k for interrupt vectors etc. */

383
arch/powerpc/kernel/prom_init.c
View File

@ -43,6 +43,7 @@
#include <asm/btext.h>
#include <asm/sections.h>
#include <asm/machdep.h>
#include <asm/opal.h>
#include <linux/linux_logo.h>
@ -139,7 +140,9 @@ struct mem_map_entry {
typedef u32 cell_t;
extern void __start(unsigned long r3, unsigned long r4, unsigned long r5);
extern void __start(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7, unsigned long r8,
unsigned long r9);
#ifdef CONFIG_PPC64
extern int enter_prom(struct prom_args *args, unsigned long entry);
@ -185,6 +188,7 @@ static unsigned long __initdata prom_tce_alloc_end;
#define PLATFORM_LPAR 0x0001
#define PLATFORM_POWERMAC 0x0400
#define PLATFORM_GENERIC 0x0500
#define PLATFORM_OPAL 0x0600
static int __initdata of_platform;
@ -644,7 +648,7 @@ static void __init early_cmdline_parse(void)
}
}
#ifdef CONFIG_PPC_PSERIES
#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
/*
* There are two methods for telling firmware what our capabilities are.
* Newer machines have an "ibm,client-architecture-support" method on the
@ -1274,6 +1278,284 @@ static void __init prom_init_mem(void)
prom_printf(" ram_top : %x\n", RELOC(ram_top));
}
static void __init prom_close_stdin(void)
{
struct prom_t *_prom = &RELOC(prom);
ihandle val;
if (prom_getprop(_prom->chosen, "stdin", &val, sizeof(val)) > 0)
call_prom("close", 1, 0, val);
}
#ifdef CONFIG_PPC_POWERNV
static u64 __initdata prom_opal_size;
static u64 __initdata prom_opal_align;
static int __initdata prom_rtas_start_cpu;
static u64 __initdata prom_rtas_data;
static u64 __initdata prom_rtas_entry;
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
static u64 __initdata prom_opal_base;
static u64 __initdata prom_opal_entry;
#endif
/* XXX Don't change this structure without updating opal-takeover.S */
static struct opal_secondary_data {
s64 ack; /* 0 */
u64 go; /* 8 */
struct opal_takeover_args args; /* 16 */
} opal_secondary_data;
extern char opal_secondary_entry;
static void prom_query_opal(void)
{
long rc;
/* We must not query for OPAL presence on a machine that
* supports TNK takeover (970 blades), as this uses the same
* h-call with different arguments and will crash
*/
if (PHANDLE_VALID(call_prom("finddevice", 1, 1,
ADDR("/tnk-memory-map")))) {
prom_printf("TNK takeover detected, skipping OPAL check\n");
return;
}
prom_printf("Querying for OPAL presence... ");
rc = opal_query_takeover(&RELOC(prom_opal_size),
&RELOC(prom_opal_align));
prom_debug("(rc = %ld) ", rc);
if (rc != 0) {
prom_printf("not there.\n");
return;
}
RELOC(of_platform) = PLATFORM_OPAL;
prom_printf(" there !\n");
prom_debug(" opal_size = 0x%lx\n", RELOC(prom_opal_size));
prom_debug(" opal_align = 0x%lx\n", RELOC(prom_opal_align));
if (RELOC(prom_opal_align) < 0x10000)
RELOC(prom_opal_align) = 0x10000;
}
static int prom_rtas_call(int token, int nargs, int nret, int *outputs, ...)
{
struct rtas_args rtas_args;
va_list list;
int i;
rtas_args.token = token;
rtas_args.nargs = nargs;
rtas_args.nret = nret;
rtas_args.rets = (rtas_arg_t *)&(rtas_args.args[nargs]);
va_start(list, outputs);
for (i = 0; i < nargs; ++i)
rtas_args.args[i] = va_arg(list, rtas_arg_t);
va_end(list);
for (i = 0; i < nret; ++i)
rtas_args.rets[i] = 0;
opal_enter_rtas(&rtas_args, RELOC(prom_rtas_data),
RELOC(prom_rtas_entry));
if (nret > 1 && outputs != NULL)
for (i = 0; i < nret-1; ++i)
outputs[i] = rtas_args.rets[i+1];
return (nret > 0)? rtas_args.rets[0]: 0;
}
static void __init prom_opal_hold_cpus(void)
{
int i, cnt, cpu, rc;
long j;
phandle node;
char type[64];
u32 servers[8];
struct prom_t *_prom = &RELOC(prom);
void *entry = (unsigned long *)&RELOC(opal_secondary_entry);
struct opal_secondary_data *data = &RELOC(opal_secondary_data);
prom_debug("prom_opal_hold_cpus: start...\n");
prom_debug(" - entry = 0x%x\n", entry);
prom_debug(" - data = 0x%x\n", data);
data->ack = -1;
data->go = 0;
/* look for cpus */
for (node = 0; prom_next_node(&node); ) {
type[0] = 0;
prom_getprop(node, "device_type", type, sizeof(type));
if (strcmp(type, RELOC("cpu")) != 0)
continue;
/* Skip non-configured cpus. */
if (prom_getprop(node, "status", type, sizeof(type)) > 0)
if (strcmp(type, RELOC("okay")) != 0)
continue;
cnt = prom_getprop(node, "ibm,ppc-interrupt-server#s", servers,
sizeof(servers));
if (cnt == PROM_ERROR)
break;
cnt >>= 2;
for (i = 0; i < cnt; i++) {
cpu = servers[i];
prom_debug("CPU %d ... ", cpu);
if (cpu == _prom->cpu) {
prom_debug("booted !\n");
continue;
}
prom_debug("starting ... ");
/* Init the acknowledge var which will be reset by
* the secondary cpu when it awakens from its OF
* spinloop.
*/
data->ack = -1;
rc = prom_rtas_call(RELOC(prom_rtas_start_cpu), 3, 1,
NULL, cpu, entry, data);
prom_debug("rtas rc=%d ...", rc);
for (j = 0; j < 100000000 && data->ack == -1; j++) {
HMT_low();
mb();
}
HMT_medium();
if (data->ack != -1)
prom_debug("done, PIR=0x%x\n", data->ack);
else
prom_debug("timeout !\n");
}
}
prom_debug("prom_opal_hold_cpus: end...\n");
}
static void prom_opal_takeover(void)
{
struct opal_secondary_data *data = &RELOC(opal_secondary_data);
struct opal_takeover_args *args = &data->args;
u64 align = RELOC(prom_opal_align);
u64 top_addr, opal_addr;
args->k_image = (u64)RELOC(_stext);
args->k_size = _end - _stext;
args->k_entry = 0;
args->k_entry2 = 0x60;
top_addr = _ALIGN_UP(args->k_size, align);
if (RELOC(prom_initrd_start) != 0) {
args->rd_image = RELOC(prom_initrd_start);
args->rd_size = RELOC(prom_initrd_end) - args->rd_image;
args->rd_loc = top_addr;
top_addr = _ALIGN_UP(args->rd_loc + args->rd_size, align);
}
/* Pickup an address for the HAL. We want to go really high
* up to avoid problem with future kexecs. On the other hand
* we don't want to be all over the TCEs on P5IOC2 machines
* which are going to be up there too. We assume the machine
* has plenty of memory, and we ask for the HAL for now to
* be just below the 1G point, or above the initrd
*/
opal_addr = _ALIGN_DOWN(0x40000000 - RELOC(prom_opal_size), align);
if (opal_addr < top_addr)
opal_addr = top_addr;
args->hal_addr = opal_addr;
/* Copy the command line to the kernel image */
strlcpy(RELOC(boot_command_line), RELOC(prom_cmd_line),
COMMAND_LINE_SIZE);
prom_debug(" k_image = 0x%lx\n", args->k_image);
prom_debug(" k_size = 0x%lx\n", args->k_size);
prom_debug(" k_entry = 0x%lx\n", args->k_entry);
prom_debug(" k_entry2 = 0x%lx\n", args->k_entry2);
prom_debug(" hal_addr = 0x%lx\n", args->hal_addr);
prom_debug(" rd_image = 0x%lx\n", args->rd_image);
prom_debug(" rd_size = 0x%lx\n", args->rd_size);
prom_debug(" rd_loc = 0x%lx\n", args->rd_loc);
prom_printf("Performing OPAL takeover,this can take a few minutes..\n");
prom_close_stdin();
mb();
data->go = 1;
for (;;)
opal_do_takeover(args);
}
/*
* Allocate room for and instantiate OPAL
*/
static void __init prom_instantiate_opal(void)
{
phandle opal_node;
ihandle opal_inst;
u64 base, entry;
u64 size = 0, align = 0x10000;
u32 rets[2];
prom_debug("prom_instantiate_opal: start...\n");
opal_node = call_prom("finddevice", 1, 1, ADDR("/ibm,opal"));
prom_debug("opal_node: %x\n", opal_node);
if (!PHANDLE_VALID(opal_node))
return;
prom_getprop(opal_node, "opal-runtime-size", &size, sizeof(size));
if (size == 0)
return;
prom_getprop(opal_node, "opal-runtime-alignment", &align,
sizeof(align));
base = alloc_down(size, align, 0);
if (base == 0) {
prom_printf("OPAL allocation failed !\n");
return;
}
opal_inst = call_prom("open", 1, 1, ADDR("/ibm,opal"));
if (!IHANDLE_VALID(opal_inst)) {
prom_printf("opening opal package failed (%x)\n", opal_inst);
return;
}
prom_printf("instantiating opal at 0x%x...", base);
if (call_prom_ret("call-method", 4, 3, rets,
ADDR("load-opal-runtime"),
opal_inst,
base >> 32, base & 0xffffffff) != 0
|| (rets[0] == 0 && rets[1] == 0)) {
prom_printf(" failed\n");
return;
}
entry = (((u64)rets[0]) << 32) | rets[1];
prom_printf(" done\n");
reserve_mem(base, size);
prom_debug("opal base = 0x%x\n", base);
prom_debug("opal align = 0x%x\n", align);
prom_debug("opal entry = 0x%x\n", entry);
prom_debug("opal size = 0x%x\n", (long)size);
prom_setprop(opal_node, "/ibm,opal", "opal-base-address",
&base, sizeof(base));
prom_setprop(opal_node, "/ibm,opal", "opal-entry-address",
&entry, sizeof(entry));
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
RELOC(prom_opal_base) = base;
RELOC(prom_opal_entry) = entry;
#endif
prom_debug("prom_instantiate_opal: end...\n");
}
#endif /* CONFIG_PPC_POWERNV */
/*
* Allocate room for and instantiate RTAS
@ -1326,6 +1608,12 @@ static void __init prom_instantiate_rtas(void)
prom_setprop(rtas_node, "/rtas", "linux,rtas-entry",
&entry, sizeof(entry));
#ifdef CONFIG_PPC_POWERNV
/* PowerVN takeover hack */
RELOC(prom_rtas_data) = base;
RELOC(prom_rtas_entry) = entry;
prom_getprop(rtas_node, "start-cpu", &RELOC(prom_rtas_start_cpu), 4);
#endif
prom_debug("rtas base = 0x%x\n", base);
prom_debug("rtas entry = 0x%x\n", entry);
prom_debug("rtas size = 0x%x\n", (long)size);
@ -1543,7 +1831,7 @@ static void __init prom_hold_cpus(void)
*acknowledge = (unsigned long)-1;
if (reg != _prom->cpu) {
/* Primary Thread of non-boot cpu */
/* Primary Thread of non-boot cpu or any thread */
prom_printf("starting cpu hw idx %lu... ", reg);
call_prom("start-cpu", 3, 0, node,
secondary_hold, reg);
@ -1652,15 +1940,6 @@ static void __init prom_init_stdout(void)
prom_setprop(val, path, "linux,boot-display", NULL, 0);
}
static void __init prom_close_stdin(void)
{
struct prom_t *_prom = &RELOC(prom);
ihandle val;
if (prom_getprop(_prom->chosen, "stdin", &val, sizeof(val)) > 0)
call_prom("close", 1, 0, val);
}
static int __init prom_find_machine_type(void)
{
struct prom_t *_prom = &RELOC(prom);
@ -1671,7 +1950,7 @@ static int __init prom_find_machine_type(void)
int x;
#endif
/* Look for a PowerMac */
/* Look for a PowerMac or a Cell */
len = prom_getprop(_prom->root, "compatible",
compat, sizeof(compat)-1);
if (len > 0) {
@ -1697,7 +1976,11 @@ static int __init prom_find_machine_type(void)
}
}
#ifdef CONFIG_PPC64
/* If not a mac, try to figure out if it's an IBM pSeries or any other
/* Try to detect OPAL */
if (PHANDLE_VALID(call_prom("finddevice", 1, 1, ADDR("/ibm,opal"))))
return PLATFORM_OPAL;
/* Try to figure out if it's an IBM pSeries or any other
* PAPR compliant platform. We assume it is if :
* - /device_type is "chrp" (please, do NOT use that for future
* non-IBM designs !
@ -1924,7 +2207,7 @@ static void __init scan_dt_build_struct(phandle node, unsigned long *mem_start,
unsigned long soff;
unsigned char *valp;
static char pname[MAX_PROPERTY_NAME];
int l, room;
int l, room, has_phandle = 0;
dt_push_token(OF_DT_BEGIN_NODE, mem_start, mem_end);
@ -2008,19 +2291,26 @@ static void __init scan_dt_build_struct(phandle node, unsigned long *mem_start,
valp = make_room(mem_start, mem_end, l, 4);
call_prom("getprop", 4, 1, node, RELOC(pname), valp, l);
*mem_start = _ALIGN(*mem_start, 4);
if (!strcmp(RELOC(pname), RELOC("phandle")))
has_phandle = 1;
}
/* Add a "linux,phandle" property. */
soff = dt_find_string(RELOC("linux,phandle"));
if (soff == 0)
prom_printf("WARNING: Can't find string index for"
" <linux-phandle> node %s\n", path);
else {
dt_push_token(OF_DT_PROP, mem_start, mem_end);
dt_push_token(4, mem_start, mem_end);
dt_push_token(soff, mem_start, mem_end);
valp = make_room(mem_start, mem_end, 4, 4);
*(u32 *)valp = node;
/* Add a "linux,phandle" property if no "phandle" property already
* existed (can happen with OPAL)
*/
if (!has_phandle) {
soff = dt_find_string(RELOC("linux,phandle"));
if (soff == 0)
prom_printf("WARNING: Can't find string index for"
" <linux-phandle> node %s\n", path);
else {
dt_push_token(OF_DT_PROP, mem_start, mem_end);
dt_push_token(4, mem_start, mem_end);
dt_push_token(soff, mem_start, mem_end);
valp = make_room(mem_start, mem_end, 4, 4);
*(u32 *)valp = node;
}
}
/* do all our children */
@ -2504,6 +2794,7 @@ static void __init prom_check_initrd(unsigned long r3, unsigned long r4)
#endif /* CONFIG_BLK_DEV_INITRD */
}
/*
* We enter here early on, when the Open Firmware prom is still
* handling exceptions and the MMU hash table for us.
@ -2553,6 +2844,7 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
* between pSeries SMP and pSeries LPAR
*/
RELOC(of_platform) = prom_find_machine_type();
prom_printf("Detected machine type: %x\n", RELOC(of_platform));
#ifndef CONFIG_RELOCATABLE
/* Bail if this is a kdump kernel. */
@ -2565,7 +2857,7 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
*/
prom_check_initrd(r3, r4);
#ifdef CONFIG_PPC_PSERIES
#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
/*
* On pSeries, inform the firmware about our capabilities
*/
@ -2611,14 +2903,33 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
#endif
/*
* On non-powermacs, try to instantiate RTAS and puts all CPUs
* in spin-loops. PowerMacs don't have a working RTAS and use
* a different way to spin CPUs
* On non-powermacs, try to instantiate RTAS. PowerMacs don't
* have a usable RTAS implementation.
*/
if (RELOC(of_platform) != PLATFORM_POWERMAC) {
if (RELOC(of_platform) != PLATFORM_POWERMAC &&
RELOC(of_platform) != PLATFORM_OPAL)
prom_instantiate_rtas();
#ifdef CONFIG_PPC_POWERNV
/* Detect HAL and try instanciating it & doing takeover */
if (RELOC(of_platform) == PLATFORM_PSERIES_LPAR) {
prom_query_opal();
if (RELOC(of_platform) == PLATFORM_OPAL) {
prom_opal_hold_cpus();
prom_opal_takeover();
}
} else if (RELOC(of_platform) == PLATFORM_OPAL)
prom_instantiate_opal();
#endif
/*
* On non-powermacs, put all CPUs in spin-loops.
*
* PowerMacs use a different mechanism to spin CPUs
*/
if (RELOC(of_platform) != PLATFORM_POWERMAC &&
RELOC(of_platform) != PLATFORM_OPAL)
prom_hold_cpus();
}
/*
* Fill in some infos for use by the kernel later on
@ -2685,7 +2996,13 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
reloc_got2(-offset);
#endif
__start(hdr, kbase, 0);
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
/* OPAL early debug gets the OPAL base & entry in r8 and r9 */
__start(hdr, kbase, 0, 0, 0,
RELOC(prom_opal_base), RELOC(prom_opal_entry));
#else
__start(hdr, kbase, 0, 0, 0, 0, 0);
#endif
return 0;
}

4
arch/powerpc/kernel/prom_init_check.sh
View File

@ -20,7 +20,9 @@ WHITELIST="add_reloc_offset __bss_start __bss_stop copy_and_flush
_end enter_prom memcpy memset reloc_offset __secondary_hold
__secondary_hold_acknowledge __secondary_hold_spinloop __start
strcmp strcpy strlcpy strlen strncmp strstr logo_linux_clut224
reloc_got2 kernstart_addr memstart_addr linux_banner"
reloc_got2 kernstart_addr memstart_addr linux_banner _stext
opal_query_takeover opal_do_takeover opal_enter_rtas opal_secondary_entry
boot_command_line"
NM="$1"
OBJ="$2"

18
arch/powerpc/kernel/ptrace.c
View File

@ -1497,9 +1497,14 @@ long arch_ptrace(struct task_struct *child, long request,
if (index < PT_FPR0) {
tmp = ptrace_get_reg(child, (int) index);
} else {
unsigned int fpidx = index - PT_FPR0;
flush_fp_to_thread(child);
tmp = ((unsigned long *)child->thread.fpr)
[TS_FPRWIDTH * (index - PT_FPR0)];
if (fpidx < (PT_FPSCR - PT_FPR0))
tmp = ((unsigned long *)child->thread.fpr)
[fpidx * TS_FPRWIDTH];
else
tmp = child->thread.fpscr.val;
}
ret = put_user(tmp, datalp);
break;
@ -1525,9 +1530,14 @@ long arch_ptrace(struct task_struct *child, long request,
if (index < PT_FPR0) {
ret = ptrace_put_reg(child, index, data);
} else {
unsigned int fpidx = index - PT_FPR0;
flush_fp_to_thread(child);
((unsigned long *)child->thread.fpr)
[TS_FPRWIDTH * (index - PT_FPR0)] = data;
if (fpidx < (PT_FPSCR - PT_FPR0))
((unsigned long *)child->thread.fpr)
[fpidx * TS_FPRWIDTH] = data;
else
child->thread.fpscr.val = data;
ret = 0;
}
break;

2
arch/powerpc/kernel/setup_32.c
View File

@ -117,7 +117,7 @@ notrace unsigned long __init early_init(unsigned long dt_ptr)
* This is called very early on the boot process, after a minimal
* MMU environment has been set up but before MMU_init is called.
*/
notrace void __init machine_init(unsigned long dt_ptr)
notrace void __init machine_init(u64 dt_ptr)
{
lockdep_init();

22
arch/powerpc/kernel/setup_64.c
View File

@ -278,14 +278,14 @@ static void __init initialize_cache_info(void)
DBG(" -> initialize_cache_info()\n");
for (np = NULL; (np = of_find_node_by_type(np, "cpu"));) {
for_each_node_by_type(np, "cpu") {
num_cpus += 1;
/* We're assuming *all* of the CPUs have the same
/*
* We're assuming *all* of the CPUs have the same
* d-cache and i-cache sizes... -Peter
*/
if ( num_cpus == 1 ) {
if (num_cpus == 1) {
const u32 *sizep, *lsizep;
u32 size, lsize;
@ -294,10 +294,13 @@ static void __init initialize_cache_info(void)
sizep = of_get_property(np, "d-cache-size", NULL);
if (sizep != NULL)
size = *sizep;
lsizep = of_get_property(np, "d-cache-block-size", NULL);
lsizep = of_get_property(np, "d-cache-block-size",
NULL);
/* fallback if block size missing */
if (lsizep == NULL)
lsizep = of_get_property(np, "d-cache-line-size", NULL);
lsizep = of_get_property(np,
"d-cache-line-size",
NULL);
if (lsizep != NULL)
lsize = *lsizep;
if (sizep == 0 || lsizep == 0)
@ -314,9 +317,12 @@ static void __init initialize_cache_info(void)
sizep = of_get_property(np, "i-cache-size", NULL);
if (sizep != NULL)
size = *sizep;
lsizep = of_get_property(np, "i-cache-block-size", NULL);
lsizep = of_get_property(np, "i-cache-block-size",
NULL);
if (lsizep == NULL)
lsizep = of_get_property(np, "i-cache-line-size", NULL);
lsizep = of_get_property(np,
"i-cache-line-size",
NULL);
if (lsizep != NULL)
lsize = *lsizep;
if (sizep == 0 || lsizep == 0)

30
arch/powerpc/kernel/smp.c
View File

@ -70,6 +70,10 @@
static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
#define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
#define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
/* State of each CPU during hotplug phases */
static DEFINE_PER_CPU(int, cpu_state) = { 0 };
#else
static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
#define get_idle_for_cpu(x) (idle_thread_array[(x)])
@ -104,12 +108,25 @@ int __devinit smp_generic_kick_cpu(int nr)
* cpu_start field to become non-zero After we set cpu_start,
* the processor will continue on to secondary_start
*/
paca[nr].cpu_start = 1;
smp_mb();
if (!paca[nr].cpu_start) {
paca[nr].cpu_start = 1;
smp_mb();
return 0;
}
#ifdef CONFIG_HOTPLUG_CPU
/*
* Ok it's not there, so it might be soft-unplugged, let's
* try to bring it back
*/
per_cpu(cpu_state, nr) = CPU_UP_PREPARE;
smp_wmb();
smp_send_reschedule(nr);
#endif /* CONFIG_HOTPLUG_CPU */
return 0;
}
#endif
#endif /* CONFIG_PPC64 */
static irqreturn_t call_function_action(int irq, void *data)
{
@ -357,8 +374,6 @@ void __devinit smp_prepare_boot_cpu(void)
}
#ifdef CONFIG_HOTPLUG_CPU
/* State of each CPU during hotplug phases */
static DEFINE_PER_CPU(int, cpu_state) = { 0 };
int generic_cpu_disable(void)
{
@ -406,6 +421,11 @@ void generic_set_cpu_dead(unsigned int cpu)
{
per_cpu(cpu_state, cpu) = CPU_DEAD;
}
int generic_check_cpu_restart(unsigned int cpu)
{
return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
}
#endif
struct create_idle {

2
arch/powerpc/kernel/swsusp.c
View File

@ -33,6 +33,6 @@ void save_processor_state(void)
void restore_processor_state(void)
{
#ifdef CONFIG_PPC32
switch_mmu_context(NULL, current->active_mm);
switch_mmu_context(current->active_mm, current->active_mm);
#endif
}

9
arch/powerpc/kernel/traps.c
View File

@ -457,7 +457,14 @@ int machine_check_e500mc(struct pt_regs *regs)
if (reason & MCSR_DCPERR_MC) {
printk("Data Cache Parity Error\n");
recoverable = 0;
/*
* In write shadow mode we auto-recover from the error, but it
* may still get logged and cause a machine check. We should
* only treat the non-write shadow case as non-recoverable.
*/
if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
recoverable = 0;
}
if (reason & MCSR_L2MMU_MHIT) {

6
arch/powerpc/kernel/udbg.c
View File

@ -69,6 +69,12 @@ void __init udbg_early_init(void)
udbg_init_wsp();
#elif defined(CONFIG_PPC_EARLY_DEBUG_EHV_BC)
udbg_init_ehv_bc();
#elif defined(CONFIG_PPC_EARLY_DEBUG_PS3GELIC)
udbg_init_ps3gelic();
#elif defined(CONFIG_PPC_EARLY_DEBUG_OPAL_RAW)
udbg_init_debug_opal_raw();
#elif defined(CONFIG_PPC_EARLY_DEBUG_OPAL_HVSI)
udbg_init_debug_opal_hvsi();
#endif
#ifdef CONFIG_PPC_EARLY_DEBUG

21
arch/powerpc/kernel/vio.c
View File

@ -605,15 +605,20 @@ static int vio_dma_iommu_dma_supported(struct device *dev, u64 mask)
return dma_iommu_ops.dma_supported(dev, mask);
}
struct dma_map_ops vio_dma_mapping_ops = {
.alloc_coherent = vio_dma_iommu_alloc_coherent,
.free_coherent = vio_dma_iommu_free_coherent,
.map_sg = vio_dma_iommu_map_sg,
.unmap_sg = vio_dma_iommu_unmap_sg,
.map_page = vio_dma_iommu_map_page,
.unmap_page = vio_dma_iommu_unmap_page,
.dma_supported = vio_dma_iommu_dma_supported,
static u64 vio_dma_get_required_mask(struct device *dev)
{
return dma_iommu_ops.get_required_mask(dev);
}
struct dma_map_ops vio_dma_mapping_ops = {
.alloc_coherent = vio_dma_iommu_alloc_coherent,
.free_coherent = vio_dma_iommu_free_coherent,
.map_sg = vio_dma_iommu_map_sg,
.unmap_sg = vio_dma_iommu_unmap_sg,
.map_page = vio_dma_iommu_map_page,
.unmap_page = vio_dma_iommu_unmap_page,
.dma_supported = vio_dma_iommu_dma_supported,
.get_required_mask = vio_dma_get_required_mask,
};
/**

100
arch/powerpc/math-emu/math_efp.c
View File

@ -171,10 +171,6 @@ static unsigned long insn_type(unsigned long speinsn)
case EFDNABS: ret = XA; break;
case EFDNEG: ret = XA; break;
case EFDSUB: ret = AB; break;
default:
printk(KERN_ERR "\nOoops! SPE instruction no type found.");
printk(KERN_ERR "\ninst code: %08lx\n", speinsn);
}
return ret;
@ -195,7 +191,7 @@ int do_spe_mathemu(struct pt_regs *regs)
type = insn_type(speinsn);
if (type == NOTYPE)
return -ENOSYS;
goto illegal;
func = speinsn & 0x7ff;
fc = (speinsn >> 21) & 0x1f;
@ -212,12 +208,10 @@ int do_spe_mathemu(struct pt_regs *regs)
__FPU_FPSCR = mfspr(SPRN_SPEFSCR);
#ifdef DEBUG
printk("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
printk("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
printk("va: %08x %08x\n", va.wp[0], va.wp[1]);
printk("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
#endif
pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);
pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
switch (src) {
case SPFP: {
@ -235,10 +229,8 @@ int do_spe_mathemu(struct pt_regs *regs)
break;
}
#ifdef DEBUG
printk("SA: %ld %08lx %ld (%ld)\n", SA_s, SA_f, SA_e, SA_c);
printk("SB: %ld %08lx %ld (%ld)\n", SB_s, SB_f, SB_e, SB_c);
#endif
pr_debug("SA: %ld %08lx %ld (%ld)\n", SA_s, SA_f, SA_e, SA_c);
pr_debug("SB: %ld %08lx %ld (%ld)\n", SB_s, SB_f, SB_e, SB_c);
switch (func) {
case EFSABS:
@ -305,10 +297,10 @@ int do_spe_mathemu(struct pt_regs *regs)
FP_DECL_D(DB);
FP_CLEAR_EXCEPTIONS;
FP_UNPACK_DP(DB, vb.dp);
#ifdef DEBUG
printk("DB: %ld %08lx %08lx %ld (%ld)\n",
pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n",
DB_s, DB_f1, DB_f0, DB_e, DB_c);
#endif
FP_CONV(S, D, 1, 2, SR, DB);
goto pack_s;
}
@ -332,9 +324,8 @@ int do_spe_mathemu(struct pt_regs *regs)
break;
pack_s:
#ifdef DEBUG
printk("SR: %ld %08lx %ld (%ld)\n", SR_s, SR_f, SR_e, SR_c);
#endif
pr_debug("SR: %ld %08lx %ld (%ld)\n", SR_s, SR_f, SR_e, SR_c);
FP_PACK_SP(vc.wp + 1, SR);
goto update_regs;
@ -365,12 +356,10 @@ cmp_s:
break;
}
#ifdef DEBUG
printk("DA: %ld %08lx %08lx %ld (%ld)\n",
pr_debug("DA: %ld %08lx %08lx %ld (%ld)\n",
DA_s, DA_f1, DA_f0, DA_e, DA_c);
printk("DB: %ld %08lx %08lx %ld (%ld)\n",
pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n",
DB_s, DB_f1, DB_f0, DB_e, DB_c);
#endif
switch (func) {
case EFDABS:
@ -438,10 +427,10 @@ cmp_s:
FP_DECL_S(SB);
FP_CLEAR_EXCEPTIONS;
FP_UNPACK_SP(SB, vb.wp + 1);
#ifdef DEBUG
printk("SB: %ld %08lx %ld (%ld)\n",
pr_debug("SB: %ld %08lx %ld (%ld)\n",
SB_s, SB_f, SB_e, SB_c);
#endif
FP_CONV(D, S, 2, 1, DR, SB);
goto pack_d;
}
@ -471,10 +460,9 @@ cmp_s:
break;
pack_d:
#ifdef DEBUG
printk("DR: %ld %08lx %08lx %ld (%ld)\n",
pr_debug("DR: %ld %08lx %08lx %ld (%ld)\n",
DR_s, DR_f1, DR_f0, DR_e, DR_c);
#endif
FP_PACK_DP(vc.dp, DR);
goto update_regs;
@ -511,12 +499,14 @@ cmp_d:
break;
}
#ifdef DEBUG
printk("SA0: %ld %08lx %ld (%ld)\n", SA0_s, SA0_f, SA0_e, SA0_c);
printk("SA1: %ld %08lx %ld (%ld)\n", SA1_s, SA1_f, SA1_e, SA1_c);
printk("SB0: %ld %08lx %ld (%ld)\n", SB0_s, SB0_f, SB0_e, SB0_c);
printk("SB1: %ld %08lx %ld (%ld)\n", SB1_s, SB1_f, SB1_e, SB1_c);
#endif
pr_debug("SA0: %ld %08lx %ld (%ld)\n",
SA0_s, SA0_f, SA0_e, SA0_c);
pr_debug("SA1: %ld %08lx %ld (%ld)\n",
SA1_s, SA1_f, SA1_e, SA1_c);
pr_debug("SB0: %ld %08lx %ld (%ld)\n",
SB0_s, SB0_f, SB0_e, SB0_c);
pr_debug("SB1: %ld %08lx %ld (%ld)\n",
SB1_s, SB1_f, SB1_e, SB1_c);
switch (func) {
case EVFSABS:
@ -605,10 +595,11 @@ cmp_d:
break;
pack_vs:
#ifdef DEBUG
printk("SR0: %ld %08lx %ld (%ld)\n", SR0_s, SR0_f, SR0_e, SR0_c);
printk("SR1: %ld %08lx %ld (%ld)\n", SR1_s, SR1_f, SR1_e, SR1_c);
#endif
pr_debug("SR0: %ld %08lx %ld (%ld)\n",
SR0_s, SR0_f, SR0_e, SR0_c);
pr_debug("SR1: %ld %08lx %ld (%ld)\n",
SR1_s, SR1_f, SR1_e, SR1_c);
FP_PACK_SP(vc.wp, SR0);
FP_PACK_SP(vc.wp + 1, SR1);
goto update_regs;
@ -646,14 +637,12 @@ update_regs:
current->thread.evr[fc] = vc.wp[0];
regs->gpr[fc] = vc.wp[1];
#ifdef DEBUG
printk("ccr = %08lx\n", regs->ccr);
printk("cur exceptions = %08x spefscr = %08lx\n",
pr_debug("ccr = %08lx\n", regs->ccr);
pr_debug("cur exceptions = %08x spefscr = %08lx\n",
FP_CUR_EXCEPTIONS, __FPU_FPSCR);
printk("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
printk("va: %08x %08x\n", va.wp[0], va.wp[1]);
printk("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
#endif
pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);
pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
return 0;
@ -661,9 +650,7 @@ illegal:
if (have_e500_cpu_a005_erratum) {
/* according to e500 cpu a005 erratum, reissue efp inst */
regs->nip -= 4;
#ifdef DEBUG
printk(KERN_DEBUG "re-issue efp inst: %08lx\n", speinsn);
#endif
pr_debug("re-issue efp inst: %08lx\n", speinsn);
return 0;
}
@ -685,13 +672,20 @@ int speround_handler(struct pt_regs *regs)
type = insn_type(speinsn & 0x7ff);
if (type == XCR) return -ENOSYS;
__FPU_FPSCR = mfspr(SPRN_SPEFSCR);
pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
/* No need to round if the result is exact */
if (!(__FPU_FPSCR & FP_EX_INEXACT))
return 0;
fc = (speinsn >> 21) & 0x1f;
s_lo = regs->gpr[fc] & SIGN_BIT_S;
s_hi = current->thread.evr[fc] & SIGN_BIT_S;
fgpr.wp[0] = current->thread.evr[fc];
fgpr.wp[1] = regs->gpr[fc];
__FPU_FPSCR = mfspr(SPRN_SPEFSCR);
pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);
switch ((speinsn >> 5) & 0x7) {
/* Since SPE instructions on E500 core can handle round to nearest
@ -731,6 +725,8 @@ int speround_handler(struct pt_regs *regs)
current->thread.evr[fc] = fgpr.wp[0];
regs->gpr[fc] = fgpr.wp[1];
pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);
return 0;
}

1
arch/powerpc/mm/Makefile
View File

@ -29,6 +29,7 @@ obj-$(CONFIG_PPC_MM_SLICES) += slice.o
ifeq ($(CONFIG_HUGETLB_PAGE),y)
obj-y += hugetlbpage.o
obj-$(CONFIG_PPC_STD_MMU_64) += hugetlbpage-hash64.o
obj-$(CONFIG_PPC_BOOK3E_MMU) += hugetlbpage-book3e.o
endif
obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o
obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o

43
arch/powerpc/mm/fsl_booke_mmu.c
View File

@ -101,17 +101,17 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
/*
* Set up a variable-size TLB entry (tlbcam). The parameters are not checked;
* in particular size must be a power of 4 between 4k and 256M (or 1G, for cpus
* that support extended page sizes). Note that while some cpus support a
* page size of 4G, we don't allow its use here.
* in particular size must be a power of 4 between 4k and the max supported by
* an implementation; max may further be limited by what can be represented in
* an unsigned long (for example, 32-bit implementations cannot support a 4GB
* size).
*/
static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
unsigned long size, unsigned long flags, unsigned int pid)
{
unsigned int tsize, lz;
unsigned int tsize;
asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (size));
tsize = 21 - lz;
tsize = __ilog2(size) - 10;
#ifdef CONFIG_SMP
if ((flags & _PAGE_NO_CACHE) == 0)
@ -146,29 +146,36 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
loadcam_entry(index);
}
unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
phys_addr_t phys)
{
unsigned int camsize = __ilog2(ram) & ~1U;
unsigned int align = __ffs(virt | phys) & ~1U;
unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
/* Convert (4^max) kB to (2^max) bytes */
max_cam = max_cam * 2 + 10;
if (camsize > align)
camsize = align;
if (camsize > max_cam)
camsize = max_cam;
return 1UL << camsize;
}
unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
{
int i;
unsigned long virt = PAGE_OFFSET;
phys_addr_t phys = memstart_addr;
unsigned long amount_mapped = 0;
unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
/* Convert (4^max) kB to (2^max) bytes */
max_cam = max_cam * 2 + 10;
/* Calculate CAM values */
for (i = 0; ram && i < max_cam_idx; i++) {
unsigned int camsize = __ilog2(ram) & ~1U;
unsigned int align = __ffs(virt | phys) & ~1U;
unsigned long cam_sz;
if (camsize > align)
camsize = align;
if (camsize > max_cam)
camsize = max_cam;
cam_sz = 1UL << camsize;
cam_sz = calc_cam_sz(ram, virt, phys);
settlbcam(i, virt, phys, cam_sz, PAGE_KERNEL_X, 0);
ram -= cam_sz;

9
arch/powerpc/mm/hash_utils_64.c
View File

@ -105,9 +105,6 @@ int mmu_kernel_ssize = MMU_SEGSIZE_256M;
int mmu_highuser_ssize = MMU_SEGSIZE_256M;
u16 mmu_slb_size = 64;
EXPORT_SYMBOL_GPL(mmu_slb_size);
#ifdef CONFIG_HUGETLB_PAGE
unsigned int HPAGE_SHIFT;
#endif
#ifdef CONFIG_PPC_64K_PAGES
int mmu_ci_restrictions;
#endif
@ -534,11 +531,11 @@ static unsigned long __init htab_get_table_size(void)
}
#ifdef CONFIG_MEMORY_HOTPLUG
void create_section_mapping(unsigned long start, unsigned long end)
int create_section_mapping(unsigned long start, unsigned long end)
{
BUG_ON(htab_bolt_mapping(start, end, __pa(start),
return htab_bolt_mapping(start, end, __pa(start),
pgprot_val(PAGE_KERNEL), mmu_linear_psize,
mmu_kernel_ssize));
mmu_kernel_ssize);
}
int remove_section_mapping(unsigned long start, unsigned long end)

121
arch/powerpc/mm/hugetlbpage-book3e.c Normal file
View File

@ -0,0 +1,121 @@
/*
* PPC Huge TLB Page Support for Book3E MMU
*
* Copyright (C) 2009 David Gibson, IBM Corporation.
* Copyright (C) 2011 Becky Bruce, Freescale Semiconductor
*
*/
#include <linux/mm.h>
#include <linux/hugetlb.h>
static inline int mmu_get_tsize(int psize)
{
return mmu_psize_defs[psize].enc;
}
static inline int book3e_tlb_exists(unsigned long ea, unsigned long pid)
{
int found = 0;
mtspr(SPRN_MAS6, pid << 16);
if (mmu_has_feature(MMU_FTR_USE_TLBRSRV)) {
asm volatile(
"li %0,0\n"
"tlbsx. 0,%1\n"
"bne 1f\n"
"li %0,1\n"
"1:\n"
: "=&r"(found) : "r"(ea));
} else {
asm volatile(
"tlbsx 0,%1\n"
"mfspr %0,0x271\n"
"srwi %0,%0,31\n"
: "=&r"(found) : "r"(ea));
}
return found;
}
void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte)
{
unsigned long mas1, mas2;
u64 mas7_3;
unsigned long psize, tsize, shift;
unsigned long flags;
#ifdef CONFIG_PPC_FSL_BOOK3E
int index, lz, ncams;
struct vm_area_struct *vma;
#endif
if (unlikely(is_kernel_addr(ea)))
return;
#ifdef CONFIG_PPC_MM_SLICES
psize = mmu_get_tsize(get_slice_psize(mm, ea));
tsize = mmu_get_psize(psize);
shift = mmu_psize_defs[psize].shift;
#else
vma = find_vma(mm, ea);
psize = vma_mmu_pagesize(vma); /* returns actual size in bytes */
asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (psize));
shift = 31 - lz;
tsize = 21 - lz;
#endif
/*
* We can't be interrupted while we're setting up the MAS
* regusters or after we've confirmed that no tlb exists.
*/
local_irq_save(flags);
if (unlikely(book3e_tlb_exists(ea, mm->context.id))) {
local_irq_restore(flags);
return;
}
#ifdef CONFIG_PPC_FSL_BOOK3E
ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
/* We have to use the CAM(TLB1) on FSL parts for hugepages */
index = __get_cpu_var(next_tlbcam_idx);
mtspr(SPRN_MAS0, MAS0_ESEL(index) | MAS0_TLBSEL(1));
/* Just round-robin the entries and wrap when we hit the end */
if (unlikely(index == ncams - 1))
__get_cpu_var(next_tlbcam_idx) = tlbcam_index;
else
__get_cpu_var(next_tlbcam_idx)++;
#endif
mas1 = MAS1_VALID | MAS1_TID(mm->context.id) | MAS1_TSIZE(tsize);
mas2 = ea & ~((1UL << shift) - 1);
mas2 |= (pte_val(pte) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
mas7_3 = (u64)pte_pfn(pte) << PAGE_SHIFT;
mas7_3 |= (pte_val(pte) >> PTE_BAP_SHIFT) & MAS3_BAP_MASK;
if (!pte_dirty(pte))
mas7_3 &= ~(MAS3_SW|MAS3_UW);
mtspr(SPRN_MAS1, mas1);
mtspr(SPRN_MAS2, mas2);
if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS)) {
mtspr(SPRN_MAS7_MAS3, mas7_3);
} else {
mtspr(SPRN_MAS7, upper_32_bits(mas7_3));
mtspr(SPRN_MAS3, lower_32_bits(mas7_3));
}
asm volatile ("tlbwe");
local_irq_restore(flags);
}
void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
{
struct hstate *hstate = hstate_file(vma->vm_file);
unsigned long tsize = huge_page_shift(hstate) - 10;
__flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, tsize, 0);
}

379
arch/powerpc/mm/hugetlbpage.c
View File

@ -1,7 +1,8 @@
/*
* PPC64 (POWER4) Huge TLB Page Support for Kernel.
* PPC Huge TLB Page Support for Kernel.
*
* Copyright (C) 2003 David Gibson, IBM Corporation.
* Copyright (C) 2011 Becky Bruce, Freescale Semiconductor
*
* Based on the IA-32 version:
* Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
@ -11,24 +12,39 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/hugetlb.h>
#include <linux/of_fdt.h>
#include <linux/memblock.h>
#include <linux/bootmem.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/tlb.h>
#include <asm/setup.h>
#define PAGE_SHIFT_64K 16
#define PAGE_SHIFT_16M 24
#define PAGE_SHIFT_16G 34
unsigned int HPAGE_SHIFT;
/*
* Tracks gpages after the device tree is scanned and before the
* huge_boot_pages list is ready. On 64-bit implementations, this is
* just used to track 16G pages and so is a single array. 32-bit
* implementations may have more than one gpage size due to limitations
* of the memory allocators, so we need multiple arrays
*/
#ifdef CONFIG_PPC64
#define MAX_NUMBER_GPAGES 1024
/* Tracks the 16G pages after the device tree is scanned and before the
* huge_boot_pages list is ready. */
static unsigned long gpage_freearray[MAX_NUMBER_GPAGES];
static u64 gpage_freearray[MAX_NUMBER_GPAGES];
static unsigned nr_gpages;
/* Flag to mark huge PD pointers. This means pmd_bad() and pud_bad()
* will choke on pointers to hugepte tables, which is handy for
* catching screwups early. */
#else
#define MAX_NUMBER_GPAGES 128
struct psize_gpages {
u64 gpage_list[MAX_NUMBER_GPAGES];
unsigned int nr_gpages;
};
static struct psize_gpages gpage_freearray[MMU_PAGE_COUNT];
#endif
static inline int shift_to_mmu_psize(unsigned int shift)
{
@ -49,25 +65,6 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
#define hugepd_none(hpd) ((hpd).pd == 0)
static inline pte_t *hugepd_page(hugepd_t hpd)
{
BUG_ON(!hugepd_ok(hpd));
return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | 0xc000000000000000);
}
static inline unsigned int hugepd_shift(hugepd_t hpd)
{
return hpd.pd & HUGEPD_SHIFT_MASK;
}
static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr, unsigned pdshift)
{
unsigned long idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
pte_t *dir = hugepd_page(*hpdp);
return dir + idx;
}
pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift)
{
pgd_t *pg;
@ -93,7 +90,7 @@ pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift
if (is_hugepd(pm))
hpdp = (hugepd_t *)pm;
else if (!pmd_none(*pm)) {
return pte_offset_map(pm, ea);
return pte_offset_kernel(pm, ea);
}
}
}
@ -114,8 +111,18 @@ pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
unsigned long address, unsigned pdshift, unsigned pshift)
{
pte_t *new = kmem_cache_zalloc(PGT_CACHE(pdshift - pshift),
GFP_KERNEL|__GFP_REPEAT);
struct kmem_cache *cachep;
pte_t *new;
#ifdef CONFIG_PPC64
cachep = PGT_CACHE(pdshift - pshift);
#else
int i;
int num_hugepd = 1 << (pshift - pdshift);
cachep = hugepte_cache;
#endif
new = kmem_cache_zalloc(cachep, GFP_KERNEL|__GFP_REPEAT);
BUG_ON(pshift > HUGEPD_SHIFT_MASK);
BUG_ON((unsigned long)new & HUGEPD_SHIFT_MASK);
@ -124,10 +131,31 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
return -ENOMEM;
spin_lock(&mm->page_table_lock);
#ifdef CONFIG_PPC64
if (!hugepd_none(*hpdp))
kmem_cache_free(PGT_CACHE(pdshift - pshift), new);
kmem_cache_free(cachep, new);
else
hpdp->pd = ((unsigned long)new & ~0x8000000000000000) | pshift;
hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
#else
/*
* We have multiple higher-level entries that point to the same
* actual pte location. Fill in each as we go and backtrack on error.
* We need all of these so the DTLB pgtable walk code can find the
* right higher-level entry without knowing if it's a hugepage or not.
*/
for (i = 0; i < num_hugepd; i++, hpdp++) {
if (unlikely(!hugepd_none(*hpdp)))
break;
else
hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
}
/* If we bailed from the for loop early, an error occurred, clean up */
if (i < num_hugepd) {
for (i = i - 1 ; i >= 0; i--, hpdp--)
hpdp->pd = 0;
kmem_cache_free(cachep, new);
}
#endif
spin_unlock(&mm->page_table_lock);
return 0;
}
@ -169,11 +197,132 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz
return hugepte_offset(hpdp, addr, pdshift);
}
#ifdef CONFIG_PPC32
/* Build list of addresses of gigantic pages. This function is used in early
* boot before the buddy or bootmem allocator is setup.
*/
void add_gpage(unsigned long addr, unsigned long page_size,
unsigned long number_of_pages)
void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages)
{
unsigned int idx = shift_to_mmu_psize(__ffs(page_size));
int i;
if (addr == 0)
return;
gpage_freearray[idx].nr_gpages = number_of_pages;
for (i = 0; i < number_of_pages; i++) {
gpage_freearray[idx].gpage_list[i] = addr;
addr += page_size;
}
}
/*
* Moves the gigantic page addresses from the temporary list to the
* huge_boot_pages list.
*/
int alloc_bootmem_huge_page(struct hstate *hstate)
{
struct huge_bootmem_page *m;
int idx = shift_to_mmu_psize(hstate->order + PAGE_SHIFT);
int nr_gpages = gpage_freearray[idx].nr_gpages;
if (nr_gpages == 0)
return 0;
#ifdef CONFIG_HIGHMEM
/*
* If gpages can be in highmem we can't use the trick of storing the
* data structure in the page; allocate space for this
*/
m = alloc_bootmem(sizeof(struct huge_bootmem_page));
m->phys = gpage_freearray[idx].gpage_list[--nr_gpages];
#else
m = phys_to_virt(gpage_freearray[idx].gpage_list[--nr_gpages]);
#endif
list_add(&m->list, &huge_boot_pages);
gpage_freearray[idx].nr_gpages = nr_gpages;
gpage_freearray[idx].gpage_list[nr_gpages] = 0;
m->hstate = hstate;
return 1;
}
/*
* Scan the command line hugepagesz= options for gigantic pages; store those in
* a list that we use to allocate the memory once all options are parsed.
*/
unsigned long gpage_npages[MMU_PAGE_COUNT];
static int __init do_gpage_early_setup(char *param, char *val)
{
static phys_addr_t size;
unsigned long npages;
/*
* The hugepagesz and hugepages cmdline options are interleaved. We
* use the size variable to keep track of whether or not this was done
* properly and skip over instances where it is incorrect. Other
* command-line parsing code will issue warnings, so we don't need to.
*
*/
if ((strcmp(param, "default_hugepagesz") == 0) ||
(strcmp(param, "hugepagesz") == 0)) {
size = memparse(val, NULL);
} else if (strcmp(param, "hugepages") == 0) {
if (size != 0) {
if (sscanf(val, "%lu", &npages) <= 0)
npages = 0;
gpage_npages[shift_to_mmu_psize(__ffs(size))] = npages;
size = 0;
}
}
return 0;
}
/*
* This function allocates physical space for pages that are larger than the
* buddy allocator can handle. We want to allocate these in highmem because
* the amount of lowmem is limited. This means that this function MUST be
* called before lowmem_end_addr is set up in MMU_init() in order for the lmb
* allocate to grab highmem.
*/
void __init reserve_hugetlb_gpages(void)
{
static __initdata char cmdline[COMMAND_LINE_SIZE];
phys_addr_t size, base;
int i;
strlcpy(cmdline, boot_command_line, COMMAND_LINE_SIZE);
parse_args("hugetlb gpages", cmdline, NULL, 0, &do_gpage_early_setup);
/*
* Walk gpage list in reverse, allocating larger page sizes first.
* Skip over unsupported sizes, or sizes that have 0 gpages allocated.
* When we reach the point in the list where pages are no longer
* considered gpages, we're done.
*/
for (i = MMU_PAGE_COUNT-1; i >= 0; i--) {
if (mmu_psize_defs[i].shift == 0 || gpage_npages[i] == 0)
continue;
else if (mmu_psize_to_shift(i) < (MAX_ORDER + PAGE_SHIFT))
break;
size = (phys_addr_t)(1ULL << mmu_psize_to_shift(i));
base = memblock_alloc_base(size * gpage_npages[i], size,
MEMBLOCK_ALLOC_ANYWHERE);
add_gpage(base, size, gpage_npages[i]);
}
}
#else /* PPC64 */
/* Build list of addresses of gigantic pages. This function is used in early
* boot before the buddy or bootmem allocator is setup.
*/
void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages)
{
if (!addr)
return;
@ -199,19 +348,79 @@ int alloc_bootmem_huge_page(struct hstate *hstate)
m->hstate = hstate;
return 1;
}
#endif
int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
{
return 0;
}
#ifdef CONFIG_PPC32
#define HUGEPD_FREELIST_SIZE \
((PAGE_SIZE - sizeof(struct hugepd_freelist)) / sizeof(pte_t))
struct hugepd_freelist {
struct rcu_head rcu;
unsigned int index;
void *ptes[0];
};
static DEFINE_PER_CPU(struct hugepd_freelist *, hugepd_freelist_cur);
static void hugepd_free_rcu_callback(struct rcu_head *head)
{
struct hugepd_freelist *batch =
container_of(head, struct hugepd_freelist, rcu);
unsigned int i;
for (i = 0; i < batch->index; i++)
kmem_cache_free(hugepte_cache, batch->ptes[i]);
free_page((unsigned long)batch);
}
static void hugepd_free(struct mmu_gather *tlb, void *hugepte)
{
struct hugepd_freelist **batchp;
batchp = &__get_cpu_var(hugepd_freelist_cur);
if (atomic_read(&tlb->mm->mm_users) < 2 ||
cpumask_equal(mm_cpumask(tlb->mm),
cpumask_of(smp_processor_id()))) {
kmem_cache_free(hugepte_cache, hugepte);
return;
}
if (*batchp == NULL) {
*batchp = (struct hugepd_freelist *)__get_free_page(GFP_ATOMIC);
(*batchp)->index = 0;
}
(*batchp)->ptes[(*batchp)->index++] = hugepte;
if ((*batchp)->index == HUGEPD_FREELIST_SIZE) {
call_rcu_sched(&(*batchp)->rcu, hugepd_free_rcu_callback);
*batchp = NULL;
}
}
#endif
static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshift,
unsigned long start, unsigned long end,
unsigned long floor, unsigned long ceiling)
{
pte_t *hugepte = hugepd_page(*hpdp);
unsigned shift = hugepd_shift(*hpdp);
int i;
unsigned long pdmask = ~((1UL << pdshift) - 1);
unsigned int num_hugepd = 1;
#ifdef CONFIG_PPC64
unsigned int shift = hugepd_shift(*hpdp);
#else
/* Note: On 32-bit the hpdp may be the first of several */
num_hugepd = (1 << (hugepd_shift(*hpdp) - pdshift));
#endif
start &= pdmask;
if (start < floor)
@ -224,9 +433,15 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
if (end - 1 > ceiling - 1)
return;
hpdp->pd = 0;
for (i = 0; i < num_hugepd; i++, hpdp++)
hpdp->pd = 0;
tlb->need_flush = 1;
#ifdef CONFIG_PPC64
pgtable_free_tlb(tlb, hugepte, pdshift - shift);
#else
hugepd_free(tlb, hugepte);
#endif
}
static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
@ -331,18 +546,27 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb,
* too.
*/
pgd = pgd_offset(tlb->mm, addr);
do {
next = pgd_addr_end(addr, end);
pgd = pgd_offset(tlb->mm, addr);
if (!is_hugepd(pgd)) {
if (pgd_none_or_clear_bad(pgd))
continue;
hugetlb_free_pud_range(tlb, pgd, addr, next, floor, ceiling);
} else {
#ifdef CONFIG_PPC32
/*
* Increment next by the size of the huge mapping since
* on 32-bit there may be more than one entry at the pgd
* level for a single hugepage, but all of them point to
* the same kmem cache that holds the hugepte.
*/
next = addr + (1 << hugepd_shift(*(hugepd_t *)pgd));
#endif
free_hugepd_range(tlb, (hugepd_t *)pgd, PGDIR_SHIFT,
addr, next, floor, ceiling);
}
} while (pgd++, addr = next, addr != end);
} while (addr = next, addr != end);
}
struct page *
@ -477,17 +701,35 @@ unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
unsigned long len, unsigned long pgoff,
unsigned long flags)
{
#ifdef CONFIG_PPC_MM_SLICES
struct hstate *hstate = hstate_file(file);
int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0);
#else
return get_unmapped_area(file, addr, len, pgoff, flags);
#endif
}
unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
{
#ifdef CONFIG_PPC_MM_SLICES
unsigned int psize = get_slice_psize(vma->vm_mm, vma->vm_start);
return 1UL << mmu_psize_to_shift(psize);
#else
if (!is_vm_hugetlb_page(vma))
return PAGE_SIZE;
return huge_page_size(hstate_vma(vma));
#endif
}
static inline bool is_power_of_4(unsigned long x)
{
if (is_power_of_2(x))
return (__ilog2(x) % 2) ? false : true;
return false;
}
static int __init add_huge_page_size(unsigned long long size)
@ -497,9 +739,14 @@ static int __init add_huge_page_size(unsigned long long size)
/* Check that it is a page size supported by the hardware and
* that it fits within pagetable and slice limits. */
#ifdef CONFIG_PPC_FSL_BOOK3E
if ((size < PAGE_SIZE) || !is_power_of_4(size))
return -EINVAL;
#else
if (!is_power_of_2(size)
|| (shift > SLICE_HIGH_SHIFT) || (shift <= PAGE_SHIFT))
return -EINVAL;
#endif
if ((mmu_psize = shift_to_mmu_psize(shift)) < 0)
return -EINVAL;
@ -536,6 +783,46 @@ static int __init hugepage_setup_sz(char *str)
}
__setup("hugepagesz=", hugepage_setup_sz);
#ifdef CONFIG_FSL_BOOKE
struct kmem_cache *hugepte_cache;
static int __init hugetlbpage_init(void)
{
int psize;
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
unsigned shift;
if (!mmu_psize_defs[psize].shift)
continue;
shift = mmu_psize_to_shift(psize);
/* Don't treat normal page sizes as huge... */
if (shift != PAGE_SHIFT)
if (add_huge_page_size(1ULL << shift) < 0)
continue;
}
/*
* Create a kmem cache for hugeptes. The bottom bits in the pte have
* size information encoded in them, so align them to allow this
*/
hugepte_cache = kmem_cache_create("hugepte-cache", sizeof(pte_t),
HUGEPD_SHIFT_MASK + 1, 0, NULL);
if (hugepte_cache == NULL)
panic("%s: Unable to create kmem cache for hugeptes\n",
__func__);
/* Default hpage size = 4M */
if (mmu_psize_defs[MMU_PAGE_4M].shift)
HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_4M].shift;
else
panic("%s: Unable to set default huge page size\n", __func__);
return 0;
}
#else
static int __init hugetlbpage_init(void)
{
int psize;
@ -578,15 +865,23 @@ static int __init hugetlbpage_init(void)
return 0;
}
#endif
module_init(hugetlbpage_init);
void flush_dcache_icache_hugepage(struct page *page)
{
int i;
void *start;
BUG_ON(!PageCompound(page));
for (i = 0; i < (1UL << compound_order(page)); i++)
__flush_dcache_icache(page_address(page+i));
for (i = 0; i < (1UL << compound_order(page)); i++) {
if (!PageHighMem(page)) {
__flush_dcache_icache(page_address(page+i));
} else {
start = kmap_atomic(page+i, KM_PPC_SYNC_ICACHE);
__flush_dcache_icache(start);
kunmap_atomic(start, KM_PPC_SYNC_ICACHE);
}
}
}

9
arch/powerpc/mm/init_32.c
View File

@ -32,6 +32,8 @@
#include <linux/pagemap.h>
#include <linux/memblock.h>
#include <linux/gfp.h>
#include <linux/slab.h>
#include <linux/hugetlb.h>
#include <asm/pgalloc.h>
#include <asm/prom.h>
@ -44,6 +46,7 @@
#include <asm/tlb.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <asm/hugetlb.h>
#include "mmu_decl.h"
@ -123,6 +126,12 @@ void __init MMU_init(void)
/* parse args from command line */
MMU_setup();
/*
* Reserve gigantic pages for hugetlb. This MUST occur before
* lowmem_end_addr is initialized below.
*/
reserve_hugetlb_gpages();
if (memblock.memory.cnt > 1) {
#ifndef CONFIG_WII
memblock.memory.cnt = 1;

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