drm/amdgpu/soc15: add support for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -686,6 +686,11 @@ static int nv_common_early_init(void *handle)
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adev->rev_id = 0;
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adev->rev_id = 0;
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adev->external_rev_id = adev->rev_id + 0xa;
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adev->external_rev_id = adev->rev_id + 0xa;
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break;
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break;
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case CHIP_SIENNA_CICHLID:
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adev->cg_flags = 0;
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adev->pg_flags = 0;
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adev->external_rev_id = adev->rev_id + 0x28;
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break;
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default:
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default:
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/* FIXME: not supported yet */
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/* FIXME: not supported yet */
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return -EINVAL;
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return -EINVAL;
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@@ -901,6 +906,7 @@ static int nv_common_set_clockgating_state(void *handle,
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case CHIP_NAVI10:
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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case CHIP_NAVI14:
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case CHIP_NAVI12:
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case CHIP_NAVI12:
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case CHIP_SIENNA_CICHLID:
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adev->nbio.funcs->update_medium_grain_clock_gating(adev,
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adev->nbio.funcs->update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
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state == AMD_CG_STATE_GATE);
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adev->nbio.funcs->update_medium_grain_light_sleep(adev,
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adev->nbio.funcs->update_medium_grain_light_sleep(adev,
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