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ARM: pm: ensure ARMv7 CPUs save and restore the TLS register

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Ensure that the TLS register is saved and restored over a suspend
cycle, so that userspace programs don't see a corrupted TLS value.

Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2011-06-22 15:41:58 +01:00
parent 7a0ee92b4a
commit 111b20d013
1 changed files with 7 additions and 3 deletions
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10
arch/arm/mm/proc-v7.S
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@ -210,19 +210,21 @@ cpu_v7_name:
/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl cpu_v7_suspend_size .globl cpu_v7_suspend_size
.equ cpu_v7_suspend_size, 4 * 8 .equ cpu_v7_suspend_size, 4 * 9
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
ENTRY(cpu_v7_do_suspend) ENTRY(cpu_v7_do_suspend)
stmfd sp!, {r4 - r11, lr} stmfd sp!, {r4 - r11, lr}
mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
mrc p15, 0, r5, c13, c0, 1 @ Context ID mrc p15, 0, r5, c13, c0, 1 @ Context ID
mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
stmia r0!, {r4 - r6}
mrc p15, 0, r6, c3, c0, 0 @ Domain ID mrc p15, 0, r6, c3, c0, 0 @ Domain ID
mrc p15, 0, r7, c2, c0, 0 @ TTB 0 mrc p15, 0, r7, c2, c0, 0 @ TTB 0
mrc p15, 0, r8, c2, c0, 1 @ TTB 1 mrc p15, 0, r8, c2, c0, 1 @ TTB 1
mrc p15, 0, r9, c1, c0, 0 @ Control register mrc p15, 0, r9, c1, c0, 0 @ Control register
mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
stmia r0, {r4 - r11} stmia r0, {r6 - r11}
ldmfd sp!, {r4 - r11, pc} ldmfd sp!, {r4 - r11, pc}
ENDPROC(cpu_v7_do_suspend) ENDPROC(cpu_v7_do_suspend)
@ -230,9 +232,11 @@ ENTRY(cpu_v7_do_resume)
mov ip, #0 mov ip, #0
mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
ldmia r0, {r4 - r11} ldmia r0!, {r4 - r6}
mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
mcr p15, 0, r5, c13, c0, 1 @ Context ID mcr p15, 0, r5, c13, c0, 1 @ Context ID
mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
ldmia r0, {r6 - r11}
mcr p15, 0, r6, c3, c0, 0 @ Domain ID mcr p15, 0, r6, c3, c0, 0 @ Domain ID
mcr p15, 0, r7, c2, c0, 0 @ TTB 0 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, r8, c2, c0, 1 @ TTB 1