forked from Minki/linux
drivers/edac: Lindent i82443bxgx
Run i82443bxgx.c file through Lindent for cleanup Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Douglas Thompson
Linus Torvalds
parent
203333cbba
commit
1111660109
@ -35,7 +35,6 @@
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#define EDAC_MOD_STR "i82443bxgx_edac"
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/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
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* Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
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* rows" "The 82443BX supports multiple-bit error detection and
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@ -61,67 +60,60 @@
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#define I82443BXGX_NR_CHANS 1
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#define I82443BXGX_NR_DIMMS 4
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/* 82443 PCI Device 0 */
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#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
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* config space offset */
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#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
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* row is non-ECC */
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#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
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#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
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* config space offset */
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#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
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* row is non-ECC */
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#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
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#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
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#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
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#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
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#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
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#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
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#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
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#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
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#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
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#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
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#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
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#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
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/* 82443 PCI Device 0 */
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#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
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* config space offset, Error Address
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* Pointer Register */
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#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
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#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
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#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC)*/
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#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
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* config space offset, Error Address
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* Pointer Register */
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#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
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#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
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#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
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#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
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#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
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* config space offset. */
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#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
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#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
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#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
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#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
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#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
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#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
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* config space offset. */
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#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
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#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
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#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
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#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
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#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
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#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
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#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
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#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
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#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
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* config space offset. */
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#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
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#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
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#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
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* config space offset. */
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#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
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#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
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#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
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#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
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#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
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* config space offset. */
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#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
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#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
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* config space offset. */
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/* FIXME - don't poll when ECC disabled? */
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struct i82443bxgx_edacmc_error_info {
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u32 eap;
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};
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static void i82443bxgx_edacmc_get_error_info (struct mem_ctl_info *mci,
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struct i82443bxgx_edacmc_error_info *info)
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static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
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struct i82443bxgx_edacmc_error_info
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*info)
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{
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struct pci_dev *pdev;
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pdev = to_pci_dev(mci->dev);
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@ -139,9 +131,10 @@ static void i82443bxgx_edacmc_get_error_info (struct mem_ctl_info *mci,
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I82443BXGX_EAP_OFFSET_MBE);
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}
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static int i82443bxgx_edacmc_process_error_info (struct mem_ctl_info *mci,
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struct i82443bxgx_edacmc_error_info *info, int handle_errors)
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static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
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struct
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i82443bxgx_edacmc_error_info
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*info, int handle_errors)
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{
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int error_found = 0;
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u32 eapaddr, page, pageoffset;
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@ -152,31 +145,26 @@ static int i82443bxgx_edacmc_process_error_info (struct mem_ctl_info *mci,
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page = eapaddr >> PAGE_SHIFT;
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pageoffset = eapaddr - (page << PAGE_SHIFT);
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if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
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if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
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error_found = 1;
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if (handle_errors)
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edac_mc_handle_ce(
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mci, page, pageoffset,
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/* 440BX/GX don't make syndrome information available */
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0,
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edac_mc_find_csrow_by_page(mci, page),
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0, /* channel */
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mci->ctl_name);
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edac_mc_handle_ce(mci, page, pageoffset,
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/* 440BX/GX don't make syndrome information available */
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0, edac_mc_find_csrow_by_page(mci, page), 0, /* channel */
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mci->ctl_name);
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}
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if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
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if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
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error_found = 1;
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if (handle_errors)
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edac_mc_handle_ue(
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mci, page, pageoffset,
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edac_mc_find_csrow_by_page(mci, page),
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mci->ctl_name);
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edac_mc_handle_ue(mci, page, pageoffset,
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edac_mc_find_csrow_by_page(mci, page),
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mci->ctl_name);
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}
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return error_found;
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}
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static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
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{
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struct i82443bxgx_edacmc_error_info info;
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@ -186,11 +174,10 @@ static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
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i82443bxgx_edacmc_process_error_info(mci, &info, 1);
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}
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static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
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struct pci_dev *pdev,
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enum edac_type edac_mode,
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enum mem_type mtype)
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struct pci_dev *pdev,
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enum edac_type edac_mode,
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enum mem_type mtype)
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{
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struct csrow_info *csrow;
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int index;
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@ -233,8 +220,7 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
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}
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}
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static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
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static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
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{
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struct mem_ctl_info *mci;
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u8 dramc;
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@ -260,7 +246,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
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pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
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switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
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case I82443BXGX_DRAMC_DRAM_IS_EDO:
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case I82443BXGX_DRAMC_DRAM_IS_EDO:
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mtype = MEM_EDO;
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break;
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case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
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@ -270,7 +256,8 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
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mtype = MEM_RDR;
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break;
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default:
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debugf0("Unknown/reserved DRAM type value in DRAMC register!\n");
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debugf0
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("Unknown/reserved DRAM type value in DRAMC register!\n");
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mtype = -MEM_UNKNOWN;
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}
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@ -282,13 +269,12 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
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mci->scrub_cap = SCRUB_FLAG_HW_SRC;
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pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
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ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
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(BIT(0) | BIT(1)));
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(BIT(0) | BIT(1)));
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mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
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? SCRUB_HW_SRC
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: SCRUB_NONE;
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? SCRUB_HW_SRC : SCRUB_NONE;
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switch(ecc_mode) {
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switch (ecc_mode) {
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case I82443BXGX_NBXCFG_INTEGRITY_NONE:
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edac_mode = EDAC_NONE;
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break;
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@ -300,8 +286,9 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
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edac_mode = EDAC_SECDED;
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break;
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default:
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debugf0("%s(): Unknown/reserved ECC state in NBXCFG register!\n",
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__func__);
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debugf0
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("%s(): Unknown/reserved ECC state in NBXCFG register!\n",
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__func__);
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edac_mode = EDAC_UNKNOWN;
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break;
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}
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@ -312,8 +299,10 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
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* here, or we get "phantom" errors occuring at module-load
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* time. */
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pci_write_bits32(pdev, I82443BXGX_EAP,
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(I82443BXGX_EAP_OFFSET_SBE | I82443BXGX_EAP_OFFSET_MBE),
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(I82443BXGX_EAP_OFFSET_SBE | I82443BXGX_EAP_OFFSET_MBE));
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(I82443BXGX_EAP_OFFSET_SBE |
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I82443BXGX_EAP_OFFSET_MBE),
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(I82443BXGX_EAP_OFFSET_SBE |
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I82443BXGX_EAP_OFFSET_MBE));
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = I82443_REVISION;
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@ -330,36 +319,36 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
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debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
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return 0;
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fail:
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fail:
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edac_mc_free(mci);
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return -ENODEV;
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}
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EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);
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/* returns count (>= 0), or negative on error */
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static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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const struct pci_device_id *ent)
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{
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debugf0("MC: " __FILE__ ": %s()\n", __func__);
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/* don't need to call pci_device_enable() */
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return i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
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return i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
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}
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static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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debugf0(__FILE__ ": %s()\n", __func__);
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if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL )
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if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
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return;
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edac_mc_free(mci);
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}
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EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
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EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
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static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
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@ -371,7 +360,6 @@ static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {
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MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
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static struct pci_driver i82443bxgx_edacmc_driver = {
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.name = EDAC_MOD_STR,
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.probe = i82443bxgx_edacmc_init_one,
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@ -379,23 +367,19 @@ static struct pci_driver i82443bxgx_edacmc_driver = {
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.id_table = i82443bxgx_pci_tbl,
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};
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static int __init i82443bxgx_edacmc_init(void)
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{
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return pci_register_driver(&i82443bxgx_edacmc_driver);
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}
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static void __exit i82443bxgx_edacmc_exit(void)
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{
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pci_unregister_driver(&i82443bxgx_edacmc_driver);
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}
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module_init(i82443bxgx_edacmc_init);
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module_exit(i82443bxgx_edacmc_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
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MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
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