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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable

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This commit is contained in:
Russell King 2011-01-05 10:23:38 +00:00
commit 1051b9f0f9
209 changed files with 14075 additions and 3519 deletions
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10
arch/arm/Kconfig
View File

@ -352,6 +352,14 @@ config ARCH_MXC
help
Support for Freescale MXC/iMX-based family of processors
config ARCH_MXS
bool "Freescale MXS-based"
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select COMMON_CLKDEV
help
Support for Freescale MXS-based family of processors
config ARCH_STMP3XXX
bool "Freescale STMP3xxx"
select CPU_ARM926T
@ -904,6 +912,8 @@ source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/plat-mxc/Kconfig"
source "arch/arm/mach-mxs/Kconfig"
source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"

3
arch/arm/Makefile
View File

@ -154,10 +154,11 @@ machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := imx
machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := mx25
machine-$(CONFIG_ARCH_MX25) := imx
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX5) := mx5
machine-$(CONFIG_ARCH_MXC91231) := mxc91231
machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx

1
arch/arm/configs/mx3_defconfig
View File

@ -84,6 +84,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y

138
arch/arm/mach-imx/Kconfig
View File

@ -1,13 +1,37 @@
config IMX_HAVE_DMA_V1
bool
if ARCH_MX1
config SOC_IMX1
bool
select CPU_ARM920T
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
config SOC_IMX21
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
config SOC_IMX25
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V2
select ARCH_MXC_IOMUX_V3
select MXC_AVIC
config SOC_IMX27
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
if ARCH_MX1
comment "MX1 platforms:"
config MACH_MXLADS
@ -31,33 +55,17 @@ endif
if ARCH_MX2
config SOC_IMX21
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
config SOC_IMX27
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
choice
prompt "CPUs:"
default MACH_MX21
config MACH_MX21
bool "i.MX21 support"
select SOC_IMX21
help
This enables support for Freescale's MX2 based i.MX21 processor.
config MACH_MX27
bool "i.MX27 support"
select SOC_IMX27
help
This enables support for Freescale's MX2 based i.MX27 processor.
@ -71,7 +79,10 @@ comment "MX21 platforms:"
config MACH_MX21ADS
bool "MX21ADS platform"
select SOC_IMX21
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for MX21ADS platform. This includes specific
@ -79,24 +90,79 @@ config MACH_MX21ADS
endif
if ARCH_MX25
comment "MX25 platforms:"
config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
select SOC_IMX25
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMXDI_RTC
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
config MACH_EUKREA_CPUIMX25
bool "Support Eukrea CPUIMX25 Platform"
select SOC_IMX25
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMXDI_RTC
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX25
default MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
endif
if MACH_MX27
comment "MX27 platforms:"
config MACH_MX27ADS
bool "MX27ADS platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
help
Include support for MX27ADS platform. This includes specific
configurations for the board and its peripherals.
config MACH_PCM038
bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
@ -109,8 +175,9 @@ choice
default MACH_PCM970_BASEBOARD
config MACH_PCM970_BASEBOARD
prompt "PHYTEC PCM970 development board"
bool
bool "PHYTEC PCM970 development board"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_MXC_MMC
help
This adds board specific devices that can be found on Phytec's
PCM970 evaluation board.
@ -119,9 +186,14 @@ endchoice
config MACH_CPUIMX27
bool "Eukrea CPUIMX27 module"
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX27 platform. This includes
@ -130,6 +202,7 @@ config MACH_CPUIMX27
config MACH_EUKREA_CPUIMX27_USESDHC2
bool "CPUIMX27 integrates SDHC2 module"
depends on MACH_CPUIMX27
select IMX_HAVE_PLATFORM_MXC_MMC
help
This adds support for the internal SDHC2 used on CPUIMX27
for wifi or eMMC.
@ -148,8 +221,11 @@ choice
config MACH_EUKREA_MBIMX27_BASEBOARD
bool "Eukrea MBIMX27 development board"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
help
This adds board specific devices that can be found on Eukrea's
@ -159,15 +235,26 @@ endchoice
config MACH_MX27_3DS
bool "MX27PDK platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX27PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_IMX27_VISSTRIM_M10
bool "Vista Silicon i.MX27 Visstrim_m10"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_EHCI
help
Include support for Visstrim_m10 platform and its different variants.
This includes specific configurations for the board and its
@ -175,6 +262,7 @@ config MACH_IMX27_VISSTRIM_M10
config MACH_IMX27LITE
bool "LogicPD MX27 LITEKIT platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for MX27 LITEKIT platform. This includes specific
@ -182,10 +270,17 @@ config MACH_IMX27LITE
config MACH_PCA100
bool "Phytec phyCARD-s (pca100)"
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
@ -194,8 +289,11 @@ config MACH_PCA100
config MACH_MXT_TD60
bool "Maxtrack i-MXT TD60"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for i-MXT (aka td60) platform. This

8
arch/arm/mach-imx/Makefile
View File

@ -4,13 +4,13 @@
# Object file lists.
obj-y := devices.o
obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o
obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
@ -22,6 +22,10 @@ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o

4
arch/arm/mach-imx/Makefile.boot
View File

@ -6,6 +6,10 @@ zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
zreladdr-$(CONFIG_ARCH_MX25) := 0x80008000
params_phys-$(CONFIG_ARCH_MX25) := 0x80000100
initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000

2
arch/arm/mach-imx/clock-imx21.c
View File

@ -1185,7 +1185,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "brom", brom_clk)
_REGISTER_CLOCK(NULL, "emma", emma_clk[0])
_REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "gpio", gpio_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
_REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)

2
arch/arm/mach-mx25/clock.c → arch/arm/mach-imx/clock-imx25.c
View File

@ -296,7 +296,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)

24
arch/arm/mach-imx/clock-imx27.c
View File

@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
if (clk->parent == parent)
return 0;
if (mx27_revision() >= CHIP_REV_2_0) {
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
if (parent == &mpll_main1_clk) {
cscr |= CCM_CSCR_ARM_SRC;
} else {
@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate)
div--;
reg = __raw_readl(CCM_CSCR);
if (mx27_revision() >= CHIP_REV_2_0) {
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
reg &= ~(3 << 12);
reg |= div << 12;
reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
parent_rate = clk_get_rate(clk->parent);
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
pdf += 4; /* MX27 TO2+ */
else
pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
parent_rate = clk_get_rate(clk->parent);
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
else
nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk)
parent_rate = clk_get_rate(clk->parent);
if (mx27_revision() >= CHIP_REV_2_0) {
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
vpu_pdf += 4;
} else {
@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk)
* clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
* clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
*/
if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
return 2UL * parent_rate / 3UL;
return parent_rate;
@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk)
/* On TO2 we have to write the value back. Otherwise we
* read 0 from this register the next time.
*/
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
__raw_writel(reg, CCM_SPCTL0);
return mxc_decode_pll(reg, rate);
@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk)
u32 div;
unsigned long rate;
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
else
div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
{
unsigned long rate, bclk_pdf;
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
else
bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk)
{
unsigned long rate, ipg_pdf;
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
return clk_get_rate(clk->parent);
else
ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
@ -667,7 +667,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
_REGISTER_CLOCK(NULL, "ata", ata_clk)
_REGISTER_CLOCK(NULL, "mstick", mstick_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "gpio", gpio_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void)
{
unsigned long cscr = __raw_readl(CCM_CSCR);
if (mx27_revision() >= CHIP_REV_2_0) {
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
if (cscr & CCM_CSCR_ARM_SRC)
cpu_clk.parent = &mpll_main1_clk;

14
arch/arm/mach-imx/cpu-imx27.c
View File

@ -42,7 +42,19 @@ static void query_silicon_parameter(void)
val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
+ SYS_CHIP_ID));
cpu_silicon_rev = (int)(val >> 28);
switch (val >> 28) {
case 0:
cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
break;
case 1:
cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
break;
case 2:
cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
break;
default:
cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
}
cpu_partnumber = (int)((val >> 12) & 0xFFFF);
}

24
arch/arm/mach-imx/devices-imx21.h
View File

@ -9,10 +9,26 @@
#include <mach/mx21.h>
#include <mach/devices-common.h>
extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
#define imx21_add_imx21_hcd(pdata) \
imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
#define imx21_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx21_imx2_wdt_data)
extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
#define imx21_add_imx_fb(pdata) \
imx_add_imx_fb(&imx21_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
#define imx21_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
#define imx21_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
#define imx21_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
@ -25,10 +41,18 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
#define imx21_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
#define imx21_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx21_mxc_w1_data)
extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
#define imx21_add_cspi(id, pdata) \
imx_add_spi_imx(&imx21_cspi_data[id], pdata)

51
arch/arm/mach-mx25/devices-imx25.h → arch/arm/mach-imx/devices-imx25.h
View File

@ -13,10 +13,27 @@ extern const struct imx_fec_data imx25_fec_data __initconst;
#define imx25_add_fec(pdata) \
imx_add_fec(&imx25_fec_data, pdata)
#define imx25_add_flexcan0(pdata) \
imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
#define imx25_add_flexcan1(pdata) \
imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
#define imx25_add_flexcan(id, pdata) \
imx_add_flexcan(&imx25_flexcan_data[id], pdata)
#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata)
#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata)
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
#define imx25_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
#define imx25_add_imxdi_rtc(pdata) \
imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
#define imx25_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx25_imx2_wdt_data)
extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
#define imx25_add_imx_fb(pdata) \
imx_add_imx_fb(&imx25_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
#define imx25_add_imx_i2c(id, pdata) \
@ -25,6 +42,10 @@ extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
#define imx25_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
#define imx25_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
@ -38,17 +59,29 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
#define imx25_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
#define imx25_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
#define imx25_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
#define imx25_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx25_sdhci_esdhc_imx_data[] __initconst;
#define imx25_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
#define imx25_add_spi_imx(id, pdata) \
imx_add_spi_imx(&imx25_cspi_data[id], pdata)
imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
#define imx25_add_esdhc(id, pdata) \
imx_add_esdhc(&imx25_esdhc_data[id], pdata)

35
arch/arm/mach-imx/devices-imx27.h
View File

@ -13,10 +13,26 @@ extern const struct imx_fec_data imx27_fec_data __initconst;
#define imx27_add_fec(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
#define imx27_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
#define imx27_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx27_imx2_wdt_data)
extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
#define imx27_add_imx_fb(pdata) \
imx_add_imx_fb(&imx27_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
#define imx27_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
#define imx27_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
@ -31,10 +47,29 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
#define imx27_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
#define imx27_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
#define imx27_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
#define imx27_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
#define imx27_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx27_mxc_w1_data)
extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
#define imx27_add_cspi(id, pdata) \
imx_add_spi_imx(&imx27_cspi_data[id], pdata)

553
arch/arm/mach-imx/devices.c
View File

@ -1,553 +0,0 @@
/*
* Author: MontaVista Software, Inc.
* <source@mvista.com>
*
* Based on the OMAP devices.c
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
* Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include "devices.h"
#if defined(CONFIG_ARCH_MX1)
static struct resource imx1_camera_resources[] = {
{
.start = 0x00224000,
.end = 0x00224010,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_CSI_INT,
.end = MX1_CSI_INT,
.flags = IORESOURCE_IRQ,
},
};
static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
struct platform_device imx1_camera_device = {
.name = "mx1-camera",
.id = 0, /* This is used to put cameras on this interface */
.dev = {
.dma_mask = &imx1_camera_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = imx1_camera_resources,
.num_resources = ARRAY_SIZE(imx1_camera_resources),
};
static struct resource imx_rtc_resources[] = {
{
.start = 0x00204000,
.end = 0x00204024,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_RTC_INT,
.end = MX1_RTC_INT,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_RTC_SAMINT,
.end = MX1_RTC_SAMINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_rtc_device = {
.name = "rtc-imx",
.id = 0,
.resource = imx_rtc_resources,
.num_resources = ARRAY_SIZE(imx_rtc_resources),
};
static struct resource imx_wdt_resources[] = {
{
.start = 0x00201000,
.end = 0x00201008,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_WDT_INT,
.end = MX1_WDT_INT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_wdt_device = {
.name = "imx-wdt",
.id = 0,
.resource = imx_wdt_resources,
.num_resources = ARRAY_SIZE(imx_wdt_resources),
};
static struct resource imx_usb_resources[] = {
{
.start = 0x00212000,
.end = 0x00212148,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_USBD_INT0,
.end = MX1_USBD_INT0,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT1,
.end = MX1_USBD_INT1,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT2,
.end = MX1_USBD_INT2,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT3,
.end = MX1_USBD_INT3,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT4,
.end = MX1_USBD_INT4,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT5,
.end = MX1_USBD_INT5,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT6,
.end = MX1_USBD_INT6,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_usb_device = {
.name = "imx_udc",
.id = 0,
.num_resources = ARRAY_SIZE(imx_usb_resources),
.resource = imx_usb_resources,
};
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
.irq = MX1_GPIO_INT_PORTA,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
.irq = MX1_GPIO_INT_PORTB,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
.irq = MX1_GPIO_INT_PORTC,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, {
.chip.label = "gpio-3",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
.irq = MX1_GPIO_INT_PORTD,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}
};
int __init imx1_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
#endif
#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
#ifdef CONFIG_MACH_MX27
static struct resource mx27_camera_resources[] = {
{
.start = MX27_CSI_BASE_ADDR,
.end = MX27_CSI_BASE_ADDR + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_EMMA_PRP_BASE_ADDR,
.end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_CSI,
.end = MX27_INT_CSI,
.flags = IORESOURCE_IRQ,
},{
.start = MX27_INT_EMMAPRP,
.end = MX27_INT_EMMAPRP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx27_camera_device = {
.name = "mx2-camera",
.id = 0,
.num_resources = ARRAY_SIZE(mx27_camera_resources),
.resource = mx27_camera_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
#endif
/*
* General Purpose Timer
* - i.MX21: 3 timers
* - i.MX27: 6 timers
*/
#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
static struct resource timer ## n ##_resources[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
} \
}; \
\
struct platform_device mxc_gpt ## n = { \
.name = "imx_gpt", \
.id = n, \
.num_resources = ARRAY_SIZE(timer ## n ## _resources), \
.resource = timer ## n ## _resources, \
}
/* We use gpt1 as system timer, so do not add a device for this one */
DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
#ifdef CONFIG_MACH_MX27
DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
#endif
/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
static struct resource mxc_wdt_resources[] = {
{
.start = MX2x_WDOG_BASE_ADDR,
.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_wdt = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdt_resources),
.resource = mxc_wdt_resources,
};
static struct resource mxc_w1_master_resources[] = {
{
.start = MX2x_OWIRE_BASE_ADDR,
.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_w1_master_device = {
.name = "mxc_w1",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
.resource = mxc_w1_master_resources,
};
/*
* lcdc:
* - i.MX1: the basic controller
* - i.MX21: to be checked
* - i.MX27: like i.MX1, with slightly variations
*/
static struct resource mxc_fb[] = {
{
.start = MX2x_LCDC_BASE_ADDR,
.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX2x_INT_LCDC,
.end = MX2x_INT_LCDC,
.flags = IORESOURCE_IRQ,
}
};
/* mxc lcd driver */
struct platform_device mxc_fb_device = {
.name = "imx-fb",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_fb),
.resource = mxc_fb,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource mxc_pwm_resources[] = {
{
.start = MX2x_PWM_BASE_ADDR,
.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX2x_INT_PWM,
.end = MX2x_INT_PWM,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device = {
.name = "mxc_pwm",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_pwm_resources),
.resource = mxc_pwm_resources,
};
#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
static struct resource mxc_sdhc_resources ## n[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
}, { \
.start = dmareq, \
.end = dmareq, \
.flags = IORESOURCE_DMA, \
}, \
}; \
\
static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
\
struct platform_device mxc_sdhc_device ## n = { \
.name = "mxc-mmc", \
.id = n, \
.dev = { \
.dma_mask = &mxc_sdhc ## n ## _dmamask, \
.coherent_dma_mask = DMA_BIT_MASK(32), \
}, \
.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
.resource = mxc_sdhc_resources ## n, \
}
DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR,
.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB3,
.end = MX27_INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
static u64 otg_dmamask = DMA_BIT_MASK(32);
/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* OTG host */
struct platform_device mxc_otg_host = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &otg_dmamask,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* USB host 1 */
static u64 usbh1_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh1_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR + 0x200,
.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB1,
.end = MX27_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &usbh1_dmamask,
},
.resource = mxc_usbh1_resources,
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};
/* USB host 2 */
static u64 usbh2_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh2_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR + 0x400,
.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB2,
.end = MX27_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 2,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif
/* GPIO port description */
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
{ \
.chip.label = "gpio-" #n, \
.irq = _irq, \
.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
n * 0x100), \
.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
}
#define DEFINE_MXC_GPIO_PORT(SOC, n) \
{ \
.chip.label = "gpio-" #n, \
.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
n * 0x100), \
.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
}
#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
DEFINE_MXC_GPIO_PORT(SOC, 1), \
DEFINE_MXC_GPIO_PORT(SOC, 2), \
DEFINE_MXC_GPIO_PORT(SOC, 3), \
DEFINE_MXC_GPIO_PORT(SOC, 4), \
DEFINE_MXC_GPIO_PORT(SOC, 5), \
}
#ifdef CONFIG_MACH_MX21
DEFINE_MXC_GPIO_PORTS(MX21, imx21);
int __init imx21_register_gpios(void)
{
return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
}
#endif
#ifdef CONFIG_MACH_MX27
DEFINE_MXC_GPIO_PORTS(MX27, imx27);
int __init imx27_register_gpios(void)
{
return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
}
#endif
#ifdef CONFIG_MACH_MX21
static struct resource mx21_usbhc_resources[] = {
{
.start = MX21_USBOTG_BASE_ADDR,
.end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MX21_INT_USBHOST,
.end = MX21_INT_USBHOST,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx21_usbhc_device = {
.name = "imx21-hcd",
.id = 0,
.dev = {
.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(mx21_usbhc_resources),
.resource = mx21_usbhc_resources,
};
#endif
static struct resource imx_kpp_resources[] = {
{
.start = MX2x_KPP_BASE_ADDR,
.end = MX2x_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM
}, {
.start = MX2x_INT_KPP,
.end = MX2x_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(imx_kpp_resources),
.resource = imx_kpp_resources,
};
#endif

29
arch/arm/mach-imx/devices.h
View File

@ -1,29 +0,0 @@
#ifdef CONFIG_ARCH_MX1
extern struct platform_device imx1_camera_device;
extern struct platform_device imx_rtc_device;
extern struct platform_device imx_wdt_device;
extern struct platform_device imx_usb_device;
#endif
#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
extern struct platform_device mxc_gpt1;
extern struct platform_device mxc_gpt2;
#ifdef CONFIG_MACH_MX27
extern struct platform_device mxc_gpt3;
extern struct platform_device mxc_gpt4;
extern struct platform_device mxc_gpt5;
#endif
extern struct platform_device mxc_wdt;
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mxc_fb_device;
extern struct platform_device mxc_pwm_device;
extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1;
extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mx27_camera_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mx21_usbhc_device;
extern struct platform_device imx_kpp_device;
#endif

4
arch/arm/mach-imx/dma-v1.c
View File

@ -818,9 +818,11 @@ static int __init imx_dma_init(void)
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
else
#endif
BUG();
return 0;
dma_clk = clk_get(NULL, "dma");
if (IS_ERR(dma_clk))
return PTR_ERR(dma_clk);
clk_enable(dma_clk);
/* reset DMA module */

17
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View File

@ -26,20 +26,16 @@
#include <linux/spi/ads7846.h>
#include <linux/backlight.h>
#include <video/platform_lcd.h>
#include <linux/input/matrix_keypad.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/imxfb.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/spi.h>
#include <mach/audmux.h>
#include "devices-imx27.h"
#include "devices.h"
static const int eukrea_mbimx27_pins[] __initconst = {
/* UART2 */
@ -111,7 +107,8 @@ static const uint32_t eukrea_mbimx27_keymap[] = {
KEY(1, 1, KEY_LEFT),
};
static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
static const struct matrix_keymap_data
eukrea_mbimx27_keymap_data __initconst = {
.keymap = eukrea_mbimx27_keymap,
.keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
};
@ -196,7 +193,7 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
},
};
static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
.mode = eukrea_mbimx27_modes,
.num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
@ -300,7 +297,7 @@ static struct platform_device *platform_devices[] __initdata = {
&leds_gpio,
};
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.dat3_card_detect = 1,
};
@ -345,8 +342,8 @@ void __init eukrea_mbimx27_baseboard_init(void)
imx27_add_imx_uart3(&uart_pdata);
#endif
mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
imx27_add_mxc_mmc(0, &sdhc_pdata);
i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
@ -380,7 +377,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
gpio_request(GPIO_PORTA | 25, "lcd_enable");
platform_device_register(&eukrea_mbimx27_lcd_powerdev);
mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

10
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c → arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
View File

@ -33,13 +33,11 @@
#include <asm/mach/arch.h>
#include <mach/mx25.h>
#include <mach/imx-uart.h>
#include <mach/imxfb.h>
#include <mach/audmux.h>
#include "devices-imx25.h"
#include "devices.h"
static struct pad_desc eukrea_mbimxsd_pads[] = {
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LCD */
MX25_PAD_LD0__LD0,
MX25_PAD_LD1__LD1,
@ -151,7 +149,7 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
},
};
static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
.mode = eukrea_mximxsd_modes,
.num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
.pwmr = 0x00A903FF,
@ -273,11 +271,11 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
#endif
imx25_add_imx_uart1(&uart_pdata);
mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx25_add_flexcan1(NULL);
imx25_add_esdhc(0, NULL);
imx25_add_sdhci_esdhc_imx(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);

21
arch/arm/mach-imx/mach-cpuimx27.c
View File

@ -28,7 +28,6 @@
#include <linux/serial_8250.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -40,11 +39,9 @@
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
static const int eukrea_cpuimx27_pins[] __initconst = {
/* UART1 */
@ -157,8 +154,6 @@ cpuimx27_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&eukrea_cpuimx27_nor_mtd_device,
&mxc_wdt,
&mxc_w1_master_device,
};
static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
@ -215,18 +210,18 @@ static struct platform_device serial_device = {
#endif
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
@ -262,10 +257,12 @@ static void __init eukrea_cpuimx27_init(void)
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
/* SDHC2 can be used for Wifi */
mxc_register_device(&mxc_sdhc_device1, NULL);
imx27_add_mxc_mmc(1, NULL);
#endif
#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
/* in which case UART4 is also used for Bluetooth */
@ -281,16 +278,16 @@ static void __init eukrea_cpuimx27_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx27_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx27_add_fsl_usb2_udc(&otg_device_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
eukrea_mbimx27_baseboard_init();

19
arch/arm/mach-mx25/mach-cpuimx25.c → arch/arm/mach-imx/mach-eukrea_cpuimx25.c
View File

@ -26,7 +26,6 @@
#include <linux/platform_device.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <mach/eukrea-baseboards.h>
#include <mach/hardware.h>
@ -39,17 +38,15 @@
#include <mach/mx25.h>
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/mxc_ehci.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"
#include "devices.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct pad_desc eukrea_cpuimx25_pads[] = {
static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
/* FEC - RMII */
MX25_PAD_FEC_MDC__FEC_MDC,
MX25_PAD_FEC_MDIO__FEC_MDIO,
@ -87,18 +84,18 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
},
};
static struct mxc_usbh_platform_data otg_pdata = {
static const struct mxc_usbh_platform_data otg_pdata __initconst = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
MXC_EHCI_IPPUE_DOWN,
};
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
@ -126,7 +123,7 @@ static void __init eukrea_cpuimx25_init(void)
imx25_add_imx_uart0(&uart_pdata);
imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
mxc_register_device(&mx25_rtc_device, NULL);
imx25_add_imxdi_rtc(NULL);
imx25_add_fec(&mx25_fec_pdata);
i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
@ -134,11 +131,11 @@ static void __init eukrea_cpuimx25_init(void)
imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
if (otg_mode_host)
mxc_register_device(&mxc_otg, &otg_pdata);
imx25_add_mxc_ehci_otg(&otg_pdata);
else
mxc_register_device(&otg_udc_device, &otg_device_pdata);
imx25_add_fsl_usb2_udc(&otg_device_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx25_add_mxc_ehci_hs(&usbh2_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
eukrea_mbimxsd25_baseboard_init();

12
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
View File

@ -34,12 +34,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include <mach/iomux.h>
#include <mach/mxc_ehci.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
#define SDHC1_IRQ IRQ_GPIOB(25)
@ -156,7 +153,7 @@ static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
free_irq(SDHC1_IRQ, data);
}
static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
.init = visstrim_m10_sdhc1_init,
.exit = visstrim_m10_sdhc1_exit,
};
@ -216,7 +213,8 @@ static int otg_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
static const struct mxc_usbh_platform_data
visstrim_m10_usbotg_pdata __initconst = {
.init = otg_phy_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
@ -237,8 +235,8 @@ static void __init visstrim_m10_board_init(void)
ARRAY_SIZE(visstrim_m10_i2c_devices));
imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

1
arch/arm/mach-imx/mach-imx27lite.c
View File

@ -25,7 +25,6 @@
#include <mach/iomux-mx27.h>
#include "devices-imx27.h"
#include "devices.h"
static const int mx27lite_pins[] __initconst = {
/* UART1 */

1
arch/arm/mach-imx/mach-mx1ads.c
View File

@ -30,7 +30,6 @@
#include <mach/irqs.h>
#include "devices-imx1.h"
#include "devices.h"
static const int mx1ads_pins[] __initconst = {
/* UART1 */

20
arch/arm/mach-imx/mach-mx21ads.c
View File

@ -24,13 +24,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h>
#include <mach/mmc.h>
#include "devices-imx21.h"
#include "devices.h"
/*
* Memory-mapped I/O on MX21ADS base board
@ -213,7 +210,7 @@ static struct imx_fb_videomode mx21ads_modes[] = {
},
};
static struct imx_fb_platform_data mx21ads_fb_data = {
static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
.mode = mx21ads_modes,
.num_modes = ARRAY_SIZE(mx21ads_modes),
@ -233,15 +230,8 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
int ret;
ret = request_irq(IRQ_GPIOD(25), detect_irq,
return request_irq(IRQ_GPIOD(25), detect_irq,
IRQF_TRIGGER_FALLING, "mmc-detect", data);
if (ret)
goto out;
return 0;
out:
return ret;
}
static void mx21ads_sdhc_exit(struct device *dev, void *data)
@ -249,7 +239,7 @@ static void mx21ads_sdhc_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOD(25), data);
}
static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
.ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
.get_ro = mx21ads_sdhc_get_ro,
.init = mx21ads_sdhc_init,
@ -296,8 +286,8 @@ static void __init mx21ads_board_init(void)
imx21_add_imx_uart0(&uart_pdata_rts);
imx21_add_imx_uart2(&uart_pdata_norts);
imx21_add_imx_uart3(&uart_pdata_rts);
mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
imx21_add_imx_fb(&mx21ads_fb_data);
imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
imx21_add_mxc_nand(&mx21ads_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

34
arch/arm/mach-mx25/mach-mx25_3ds.c → arch/arm/mach-imx/mach-mx25_3ds.c
View File

@ -30,6 +30,7 @@
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/input/matrix_keypad.h>
#include <linux/usb/otg.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -39,17 +40,15 @@
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/mx25.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"
#include "devices.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct pad_desc mx25pdk_pads[] = {
static iomux_v3_cfg_t mx25pdk_pads[] = {
MX25_PAD_FEC_MDC__FEC_MDC,
MX25_PAD_FEC_MDIO__FEC_MDIO,
MX25_PAD_FEC_TDATA0__FEC_TDATA0,
@ -107,7 +106,7 @@ static struct pad_desc mx25pdk_pads[] = {
};
static const struct fec_platform_data mx25_fec_pdata __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
.phy = PHY_INTERFACE_MODE_RMII,
};
#define FEC_ENABLE_GPIO 35
@ -154,7 +153,7 @@ static struct imx_fb_videomode mx25pdk_modes[] = {
},
};
static struct imx_fb_platform_data mx25pdk_fb_pdata = {
static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
.mode = mx25pdk_modes,
.num_modes = ARRAY_SIZE(mx25pdk_modes),
.pwmr = 0x00A903FF,
@ -181,28 +180,39 @@ static const uint32_t mx25pdk_keymap[] = {
KEY(3, 3, KEY_POWER),
};
static struct matrix_keymap_data mx25pdk_keymap_data = {
static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = {
.keymap = mx25pdk_keymap,
.keymap_size = ARRAY_SIZE(mx25pdk_keymap),
};
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERNAL_PHY,
};
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
static void __init mx25pdk_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
ARRAY_SIZE(mx25pdk_pads));
imx25_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxc_usbh2, NULL);
imx25_add_fsl_usb2_udc(&otg_device_pdata);
imx25_add_mxc_ehci_hs(&usbh2_pdata);
imx25_add_mxc_nand(&mx25pdk_nand_board_info);
mxc_register_device(&mx25_rtc_device, NULL);
mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
mxc_register_device(&mxc_wdt, NULL);
imx25_add_imxdi_rtc(NULL);
imx25_add_imx_fb(&mx25pdk_fb_pdata);
imx25_add_imx2_wdt(NULL);
mx25pdk_fec_reset();
imx25_add_fec(&mx25_fec_pdata);
mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
imx25_add_imx_keypad(&mx25pdk_keymap_data);
imx25_add_esdhc(0, NULL);
imx25_add_sdhci_esdhc_imx(0, NULL);
}
static void __init mx25pdk_timer_init(void)

160
arch/arm/mach-imx/mach-mx27_3ds.c
View File

@ -22,20 +22,27 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/input/matrix_keypad.h>
#include <linux/irq.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/delay.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/mmc.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
#define SD1_EN_GPIO (GPIO_PORTB + 25)
#define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23)
#define SPI2_SS0 (GPIO_PORTD + 21)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
@ -70,6 +77,24 @@ static const int mx27pdk_pins[] __initconst = {
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
/* OTG */
OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* CSPI2 */
PD22_PF_CSPI2_SCLK,
PD23_PF_CSPI2_MISO,
PD24_PF_CSPI2_MOSI,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@ -92,7 +117,7 @@ static const uint32_t mx27_3ds_keymap[] = {
KEY(2, 3, KEY_F10),
};
static struct matrix_keymap_data mx27_3ds_keymap_data = {
static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
.keymap = mx27_3ds_keymap,
.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
};
@ -109,7 +134,7 @@ static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOB(26), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mx27_3ds_sdhc1_init,
.exit = mx27_3ds_sdhc1_exit,
};
@ -121,6 +146,111 @@ static void mx27_3ds_sdhc1_enable_level_translator(void)
gpio_direction_output(SD1_EN_GPIO, 1);
}
static int otg_phy_init(void)
{
gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset");
gpio_direction_output(OTG_PHY_RESET_GPIO, 0);
mdelay(1);
gpio_set_value(OTG_PHY_RESET_GPIO, 1);
return 0;
}
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static int otg_mode_host;
static int __init mx27_3ds_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", mx27_3ds_otg_mode);
/* Regulators */
static struct regulator_consumer_supply vmmc1_consumers[] = {
REGULATOR_SUPPLY("lcd_2v8", NULL),
};
static struct regulator_init_data vmmc1_init = {
.constraints = {
.min_uV = 2800000,
.max_uV = 2800000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
.consumer_supplies = vmmc1_consumers,
};
static struct regulator_consumer_supply vgen_consumers[] = {
REGULATOR_SUPPLY("vdd_lcdio", NULL),
};
static struct regulator_init_data vgen_init = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
.consumer_supplies = vgen_consumers,
};
static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
{
.id = MC13783_REGU_VMMC1,
.init_data = &vmmc1_init,
}, {
.id = MC13783_REGU_VGEN,
.init_data = &vgen_init,
},
};
/* MC13783 */
static struct mc13783_platform_data mc13783_pdata __initdata = {
.regulators = mx27_3ds_regulators,
.num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
.flags = MC13783_USE_REGULATOR,
};
/* SPI */
static int spi2_internal_chipselect[] = {SPI2_SS0};
static const struct spi_imx_master spi2_pdata __initconst = {
.chipselect = spi2_internal_chipselect,
.num_chipselect = ARRAY_SIZE(spi2_internal_chipselect),
};
static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
{
.modalias = "mc13783",
.max_speed_hz = 1000000,
.bus_num = 1,
.chip_select = 0, /* SS0 */
.platform_data = &mc13783_pdata,
.irq = IRQ_GPIOC(14),
.mode = SPI_CS_HIGH,
},
};
static void __init mx27pdk_init(void)
{
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
@ -128,8 +258,24 @@ static void __init mx27pdk_init(void)
mx27_3ds_sdhc1_enable_level_translator();
imx27_add_imx_uart0(&uart_pdata);
imx27_add_fec(NULL);
mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
imx27_add_imx_keypad(&mx27_3ds_keymap_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_imx2_wdt(NULL);
otg_phy_init();
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
imx27_add_mxc_ehci_otg(&otg_pdata);
}
#endif
if (!otg_mode_host)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
imx27_add_spi_imx1(&spi2_pdata);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
}
static void __init mx27pdk_timer_init(void)

17
arch/arm/mach-imx/mach-mx27ads.c
View File

@ -30,11 +30,8 @@
#include <mach/gpio.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
/*
* Base address of PBC controller, CS4
@ -228,7 +225,7 @@ static struct imx_fb_videomode mx27ads_modes[] = {
},
};
static struct imx_fb_platform_data mx27ads_fb_data = {
static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
.mode = mx27ads_modes,
.num_modes = ARRAY_SIZE(mx27ads_modes),
@ -272,19 +269,18 @@ static void mx27ads_sdhc2_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOB(7), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mx27ads_sdhc1_init,
.exit = mx27ads_sdhc1_exit,
};
static struct imxmmc_platform_data sdhc2_pdata = {
static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
.init = mx27ads_sdhc2_init,
.exit = mx27ads_sdhc2_exit,
};
static struct platform_device *platform_devices[] __initdata = {
&mx27ads_nor_mtd_device,
&mxc_w1_master_device,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@ -308,12 +304,13 @@ static void __init mx27ads_board_init(void)
i2c_register_board_info(1, mx27ads_i2c_devices,
ARRAY_SIZE(mx27ads_i2c_devices));
imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
imx27_add_imx_fb(&mx27ads_fb_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_mxc_mmc(1, &sdhc2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_mxc_w1(NULL);
}
static void __init mx27ads_timer_init(void)

11
arch/arm/mach-imx/mach-mxt_td60.c
View File

@ -31,11 +31,8 @@
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <linux/i2c/pca953x.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
static const int mxt_td60_pins[] __initconst = {
/* UART0 */
@ -196,7 +193,7 @@ static struct imx_fb_videomode mxt_td60_modes[] = {
},
};
static struct imx_fb_platform_data mxt_td60_fb_data = {
static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
.mode = mxt_td60_modes,
.num_modes = ARRAY_SIZE(mxt_td60_modes),
@ -226,7 +223,7 @@ static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOF(8), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mxt_td60_sdhc1_init,
.exit = mxt_td60_sdhc1_exit,
};
@ -253,8 +250,8 @@ static void __init mxt_td60_board_init(void)
imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
imx27_add_imx_fb(&mxt_td60_fb_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_fec(NULL);
}

33
arch/arm/mach-imx/mach-pca100.c
View File

@ -29,7 +29,6 @@
#include <linux/gpio.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@ -40,13 +39,9 @@
#include <mach/audmux.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/imxfb.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
@ -171,11 +166,6 @@ pca100_nand_board_info __initconst = {
.hw_ecc = 1,
};
static struct platform_device *platform_devices[] __initdata = {
&mxc_w1_master_device,
&mxc_wdt,
};
static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
.bitrate = 100000,
};
@ -274,7 +264,7 @@ static void pca100_sdhc2_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOC(29), data);
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.init = pca100_sdhc2_init,
.exit = pca100_sdhc2_exit,
};
@ -286,7 +276,7 @@ static int otg_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.init = otg_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
@ -298,14 +288,14 @@ static int usbh2_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
@ -355,7 +345,7 @@ static struct imx_fb_videomode pca100_fb_modes[] = {
},
};
static struct imx_fb_platform_data pca100_fb_data = {
static const struct imx_fb_platform_data pca100_fb_data __initconst = {
.mode = pca100_fb_modes,
.num_modes = ARRAY_SIZE(pca100_fb_modes),
@ -389,7 +379,7 @@ static void __init pca100_init(void)
imx27_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
imx27_add_mxc_mmc(1, &sdhc_pdata);
imx27_add_mxc_nand(&pca100_nand_board_info);
@ -417,23 +407,24 @@ static void __init pca100_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx27_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host) {
gpio_set_value(OTG_PHY_CS_GPIO, 0);
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx27_add_fsl_usb2_udc(&otg_device_pdata);
}
mxc_register_device(&mxc_fb_device, &pca100_fb_data);
imx27_add_imx_fb(&pca100_fb_data);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
}
static void __init pca100_timer_init(void)

12
arch/arm/mach-imx/mach-pcm038.c
View File

@ -37,11 +37,9 @@
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
static const int pcm038_pins[] __initconst = {
/* UART1 */
@ -172,9 +170,7 @@ pcm038_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&pcm038_nor_mtd_device,
&mxc_w1_master_device,
&pcm038_sram_mtd_device,
&mxc_wdt,
};
/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
@ -214,7 +210,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = {
static struct regulator_consumer_supply sdhc1_consumers[] = {
{
.dev = &mxc_sdhc_device1.dev,
.dev_name = "mxc-mmc.1",
.supply = "sdhc_vcc",
},
};
@ -285,7 +281,7 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
}
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
};
@ -322,10 +318,12 @@ static void __init pcm038_init(void)
spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info));
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
#ifdef CONFIG_MACH_PCM970_BASEBOARD
pcm970_baseboard_init();

1
arch/arm/mach-imx/mach-scb9328.c
View File

@ -25,7 +25,6 @@
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
#include "devices.h"
/*
* This scb9328 has a 32MiB flash

7
arch/arm/mach-imx/mm-imx1.c
View File

@ -25,12 +25,7 @@
#include <mach/hardware.h>
static struct map_desc imx_io_desc[] __initdata = {
{
.virtual = MX1_IO_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
.length = MX1_IO_SIZE,
.type = MT_DEVICE
}
imx_map_entry(MX1, IO, MT_DEVICE),
};
void __init mx1_map_io(void)

21
arch/arm/mach-imx/mm-imx21.c
View File

@ -35,33 +35,18 @@ static struct map_desc imx21_io_desc[] __initdata = {
* - ROM Patch
* - and some reserved space
*/
{
.virtual = MX21_AIPI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
.length = MX21_AIPI_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, AIPI, MT_DEVICE),
/*
* this fixed mapping covers:
* - CSI
* - ATA
*/
{
.virtual = MX21_SAHB1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
.length = MX21_SAHB1_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, SAHB1, MT_DEVICE),
/*
* this fixed mapping covers:
* - EMI
*/
{
.virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
.length = MX21_X_MEMC_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, X_MEMC, MT_DEVICE),
};
/*

27
arch/arm/mach-mx25/mm.c → arch/arm/mach-imx/mm-imx25.c
View File

@ -30,25 +30,12 @@
/*
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX3 boards.
* These are the mappings common across all MX25 boards.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MX25_AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AVIC_BASE_ADDR),
.length = MX25_AVIC_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX25_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
.length = MX25_AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX25_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
.length = MX25_AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
},
static struct map_desc mx25_io_desc[] __initdata = {
imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
};
/*
@ -62,14 +49,14 @@ void __init mx25_map_io(void)
mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
}
int imx25_register_gpios(void);
void __init mx25_init_irq(void)
{
mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
imx25_register_gpios();
}

21
arch/arm/mach-imx/mm-imx27.c
View File

@ -35,33 +35,18 @@ static struct map_desc imx27_io_desc[] __initdata = {
* - ROM Patch
* - and some reserved space
*/
{
.virtual = MX27_AIPI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
.length = MX27_AIPI_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, AIPI, MT_DEVICE),
/*
* this fixed mapping covers:
* - CSI
* - ATA
*/
{
.virtual = MX27_SAHB1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
.length = MX27_SAHB1_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, SAHB1, MT_DEVICE),
/*
* this fixed mapping covers:
* - EMI
*/
{
.virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
.length = MX27_X_MEMC_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, X_MEMC, MT_DEVICE),
};
/*

12
arch/arm/mach-imx/pcm970-baseboard.c
View File

@ -25,11 +25,9 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/imxfb.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include "devices.h"
#include "devices-imx27.h"
static const int pcm970_pins[] __initconst = {
/* SDHC */
@ -119,7 +117,7 @@ static void pcm970_sdhc2_exit(struct device *dev, void *data)
gpio_free(GPIO_PORTC + 28);
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.get_ro = pcm970_sdhc2_get_ro,
.init = pcm970_sdhc2_init,
.exit = pcm970_sdhc2_exit,
@ -179,7 +177,7 @@ static struct imx_fb_videomode pcm970_modes[] = {
},
};
static struct imx_fb_platform_data pcm038_fb_data = {
static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
.mode = pcm970_modes,
.num_modes = ARRAY_SIZE(pcm970_modes),
@ -226,8 +224,8 @@ void __init pcm970_baseboard_init(void)
mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
"PCM970");
mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
imx27_add_imx_fb(&pcm038_fb_data);
mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
imx27_add_mxc_mmc(1, &sdhc_pdata);
platform_device_register(&pcm970_sja1000);
}

3
arch/arm/mach-imx/pm-imx27.c
View File

@ -39,6 +39,9 @@ static struct platform_suspend_ops mx27_suspend_ops = {
static int __init mx27_pm_init(void)
{
if (!cpu_is_mx27())
return 0;
suspend_set_ops(&mx27_suspend_ops);
return 0;
}

34
arch/arm/mach-mx25/Kconfig
View File

@ -1,34 +0,0 @@
if ARCH_MX25
comment "MX25 platforms:"
config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_ESDHC
config MACH_EUKREA_CPUIMX25
bool "Support Eukrea CPUIMX25 Platform"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select MXC_ULPI if USB_ULPI
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX25
default MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
endif

5
arch/arm/mach-mx25/Makefile
View File

@ -1,5 +0,0 @@
obj-y := mm.o devices.o
obj-$(CONFIG_ARCH_MX25) += clock.o
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o

3
arch/arm/mach-mx25/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000

308
arch/arm/mach-mx25/devices.c
View File

@ -1,308 +0,0 @@
/*
* Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <mach/mx25.h>
#include <mach/irqs.h>
static u64 otg_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_otg_resources[] = {
{
.start = MX25_OTG_BASE_ADDR,
.end = MX25_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = 37,
.end = 37,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_otg = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = mxc_otg_resources,
.num_resources = ARRAY_SIZE(mxc_otg_resources),
};
/* OTG gadget device */
struct platform_device otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = mxc_otg_resources,
.num_resources = ARRAY_SIZE(mxc_otg_resources),
};
static u64 usbh2_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh2_resources[] = {
{
.start = MX25_OTG_BASE_ADDR + 0x400,
.end = MX25_OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = 35,
.end = 35,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
static struct resource mxc_pwm_resources0[] = {
{
.start = 0x53fe0000,
.end = 0x53fe3fff,
.flags = IORESOURCE_MEM,
}, {
.start = 26,
.end = 26,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device0 = {
.name = "mxc_pwm",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_pwm_resources0),
.resource = mxc_pwm_resources0,
};
static struct resource mxc_pwm_resources1[] = {
{
.start = 0x53fa0000,
.end = 0x53fa3fff,
.flags = IORESOURCE_MEM,
}, {
.start = 36,
.end = 36,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device1 = {
.name = "mxc_pwm",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_pwm_resources1),
.resource = mxc_pwm_resources1,
};
static struct resource mxc_pwm_resources2[] = {
{
.start = 0x53fa8000,
.end = 0x53fabfff,
.flags = IORESOURCE_MEM,
}, {
.start = 41,
.end = 41,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device2 = {
.name = "mxc_pwm",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_pwm_resources2),
.resource = mxc_pwm_resources2,
};
static struct resource mxc_keypad_resources[] = {
{
.start = 0x43fa8000,
.end = 0x43fabfff,
.flags = IORESOURCE_MEM,
}, {
.start = 24,
.end = 24,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_keypad_device = {
.name = "mxc-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(mxc_keypad_resources),
.resource = mxc_keypad_resources,
};
static struct resource mxc_pwm_resources3[] = {
{
.start = 0x53fc8000,
.end = 0x53fcbfff,
.flags = IORESOURCE_MEM,
}, {
.start = 42,
.end = 42,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device3 = {
.name = "mxc_pwm",
.id = 3,
.num_resources = ARRAY_SIZE(mxc_pwm_resources3),
.resource = mxc_pwm_resources3,
};
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
.irq = 52,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
.irq = 51,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
.irq = 16,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, {
.chip.label = "gpio-3",
.base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
.irq = 23,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}
};
int __init imx25_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
static struct resource mx25_rtc_resources[] = {
{
.start = MX25_DRYICE_BASE_ADDR,
.end = MX25_DRYICE_BASE_ADDR + 0x40,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_DRYICE,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mx25_rtc_device = {
.name = "imxdi_rtc",
.id = 0,
.num_resources = ARRAY_SIZE(mx25_rtc_resources),
.resource = mx25_rtc_resources,
};
static struct resource mx25_fb_resources[] = {
{
.start = MX25_LCDC_BASE_ADDR,
.end = MX25_LCDC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_LCDC,
.end = MX25_INT_LCDC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx25_fb_device = {
.name = "imx-fb",
.id = 0,
.resource = mx25_fb_resources,
.num_resources = ARRAY_SIZE(mx25_fb_resources),
.dev = {
.coherent_dma_mask = 0xFFFFFFFF,
},
};
static struct resource mxc_wdt_resources[] = {
{
.start = MX25_WDOG_BASE_ADDR,
.end = MX25_WDOG_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_wdt = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdt_resources),
.resource = mxc_wdt_resources,
};
static struct resource mx25_kpp_resources[] = {
{
.start = MX25_KPP_BASE_ADDR,
.end = MX25_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_KPP,
.end = MX25_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx25_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(mx25_kpp_resources),
.resource = mx25_kpp_resources,
};
static struct resource mx25_csi_resources[] = {
{
.start = MX25_CSI_BASE_ADDR,
.end = MX25_CSI_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_CSI,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mx25_csi_device = {
.name = "mx2-camera",
.id = 0,
.num_resources = ARRAY_SIZE(mx25_csi_resources),
.resource = mx25_csi_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};

13
arch/arm/mach-mx25/devices.h
View File

@ -1,13 +0,0 @@
extern struct platform_device mxc_otg;
extern struct platform_device otg_udc_device;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_pwm_device0;
extern struct platform_device mxc_pwm_device1;
extern struct platform_device mxc_pwm_device2;
extern struct platform_device mxc_pwm_device3;
extern struct platform_device mxc_keypad_device;
extern struct platform_device mx25_rtc_device;
extern struct platform_device mx25_fb_device;
extern struct platform_device mxc_wdt;
extern struct platform_device mx25_kpp_device;
extern struct platform_device mx25_csi_device;

86
arch/arm/mach-mx3/Kconfig
View File

@ -1,21 +1,35 @@
if ARCH_MX3
# ARCH_MX31 and ARCH_MX35 are left for compatibility
# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
# more sensible) names are used: SOC_IMX31 and SOC_IMX35
config ARCH_MX31
select ARCH_HAS_RNGA
select ARCH_MXC_AUDMUX_V2
bool
config ARCH_MX35
bool
config SOC_IMX31
bool
select IMX_HAVE_PLATFORM_MXC_RNGA
select ARCH_MXC_AUDMUX_V2
select ARCH_MX31
select MXC_AVIC
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select HAVE_EPIT
select ARCH_MX35
select MXC_AVIC
comment "MX3 platforms:"
config MACH_MX31ADS
bool "Support MX31ADS platforms"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
@ -37,10 +51,15 @@ config MACH_MX31ADS_WM1133_EV1
config MACH_PCM037
bool "Support Phytec pcm037 (i.MX31) platforms"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm037 platform. This includes
@ -57,9 +76,12 @@ config MACH_PCM037_EET
config MACH_MX31LITE
bool "Support MX31 LITEKIT (LogicPD)"
select ARCH_MX31
select SOC_IMX31
select MXC_ULPI if USB_ULPI
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
help
@ -68,11 +90,16 @@ config MACH_MX31LITE
config MACH_MX31_3DS
bool "Support MX31PDK (3DS)"
select ARCH_MX31
select SOC_IMX31
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX31PDK (3DS) platform. This includes specific
configurations for the board and its peripherals.
@ -88,9 +115,12 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
@ -99,8 +129,10 @@ config MACH_MX31MOBOARD
config MACH_MX31LILLY
bool "Support MX31 LILLY-1131 platforms (INCO startec)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
@ -109,7 +141,7 @@ config MACH_MX31LILLY
config MACH_QONG
bool "Support Dave/DENX QongEVB-LITE platform"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Dave/DENX QongEVB-LITE platform. This includes
@ -117,13 +149,16 @@ config MACH_QONG
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select ARCH_MX35
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm043 platform. This includes
@ -131,9 +166,11 @@ config MACH_PCM043
config MACH_ARMADILLO5X0
bool "Support Atmark Armadillo-500 Development Base Board"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
@ -142,19 +179,21 @@ config MACH_ARMADILLO5X0
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select ARCH_MX35
select SOC_IMX35
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_ESDHC
default n
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_KZM_ARM11_01
bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for KZM-ARM11-01. This includes specific
@ -162,12 +201,15 @@ config MACH_KZM_ARM11_01
config MACH_EUKREA_CPUIMX35
bool "Support Eukrea CPUIMX35 Platform"
select ARCH_MX35
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_MXC_NAND
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX35 platform. This includes

7
arch/arm/mach-mx3/Makefile
View File

@ -5,17 +5,14 @@
# Object file lists.
obj-y := mm.o devices.o cpu.o
CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o
obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o
obj-$(CONFIG_SOC_IMX35) += clock-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
mx31moboard-marxbot.o mx31moboard-smartbot.o
obj-$(CONFIG_MACH_QONG) += mach-qong.o

4
arch/arm/mach-mx3/clock-imx31.c
View File

@ -530,7 +530,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "rtc", rtc_clk)
_REGISTER_CLOCK(NULL, "epit", epit1_clk)
_REGISTER_CLOCK(NULL, "epit", epit2_clk)
@ -615,7 +615,7 @@ int __init mx31_clocks_init(unsigned long fref)
mx31_read_cpu_rev();
if (mx31_revision() >= MX31_CHIP_REV_2_0) {
if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
reg = __raw_readl(MXC_CCM_PMCR1);
/* No PLL restart on DVFS switch; enable auto EMI handshake */
reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;

2
arch/arm/mach-mx3/clock-imx35.c
View File

@ -495,7 +495,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "max", max_clk)
_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
_REGISTER_CLOCK(NULL, "csi", csi_clk)

31
arch/arm/mach-mx3/cpu.c
View File

@ -25,15 +25,15 @@ struct mx3_cpu_type {
};
static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = MX3x_CHIP_REV_1_0 },
{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 },
{ .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
{ .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
{ .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 },
{ .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 },
{ .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 },
{ .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 },
{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
{ .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
{ .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
{ .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
};
void __init mx31_read_cpu_rev(void)
@ -53,6 +53,8 @@ void __init mx31_read_cpu_rev(void)
return;
}
mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
}
@ -62,22 +64,25 @@ EXPORT_SYMBOL(mx35_cpu_rev);
void __init mx35_read_cpu_rev(void)
{
u32 rev;
char *srev = "unknown";
char *srev;
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) {
case 0x00:
mx35_cpu_rev = MX3x_CHIP_REV_1_0;
mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
srev = "1.0";
break;
case 0x10:
mx35_cpu_rev = MX3x_CHIP_REV_2_0;
mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
srev = "2.0";
break;
case 0x11:
mx35_cpu_rev = MX3x_CHIP_REV_2_1;
mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
srev = "2.1";
break;
default:
mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
srev = "unknown";
}
printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);

27
arch/arm/mach-mx3/devices-imx31.h
View File

@ -9,6 +9,14 @@
#include <mach/mx31.h>
#include <mach/devices-common.h>
extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
#define imx31_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
#define imx31_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx31_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
#define imx31_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
@ -16,6 +24,10 @@ extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
#define imx31_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
@ -29,10 +41,25 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
#define imx31_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
#define imx31_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
#define imx31_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
#define imx31_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
#define imx31_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx31_mxc_w1_data)
extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
#define imx31_add_cspi(id, pdata) \
imx_add_spi_imx(&imx31_cspi_data[id], pdata)

41
arch/arm/mach-mx3/devices-imx35.h
View File

@ -13,10 +13,19 @@ extern const struct imx_fec_data imx35_fec_data __initconst;
#define imx35_add_fec(pdata) \
imx_add_fec(&imx35_fec_data, pdata)
#define imx35_add_flexcan0(pdata) \
imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
#define imx35_add_flexcan1(pdata) \
imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
#define imx35_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
#define imx35_add_flexcan(id, pdata) \
imx_add_flexcan(&imx35_flexcan_data[id], pdata)
#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
#define imx35_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx35_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
#define imx35_add_imx_i2c(id, pdata) \
@ -25,6 +34,10 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
#define imx35_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
@ -36,16 +49,28 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
#define imx35_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
#define imx35_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
#define imx35_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
#define imx35_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx35_mxc_w1_data)
extern const struct imx_sdhci_esdhc_imx_data
imx35_sdhci_esdhc_imx_data[] __initconst;
#define imx35_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
#define imx35_add_cspi(id, pdata) \
imx_add_spi_imx(&imx35_cspi_data[id], pdata)
#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
#define imx35_add_esdhc(id, pdata) \
imx_add_esdhc(&imx35_esdhc_data[id], pdata)

271
arch/arm/mach-mx3/devices.c
View File

@ -29,120 +29,25 @@
#include "devices.h"
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}
};
int __init imx3x_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
static struct resource mxc_w1_master_resources[] = {
{
.start = OWIRE_BASE_ADDR,
.end = OWIRE_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_w1_master_device = {
.name = "mxc_w1",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
.resource = mxc_w1_master_resources,
};
#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
{
.start = MX31_MMC_SDHC1_BASE_ADDR,
.end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX31_INT_MMC_SDHC1,
.end = MX31_INT_MMC_SDHC1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource mxcsdhc1_resources[] = {
{
.start = MX31_MMC_SDHC2_BASE_ADDR,
.end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX31_INT_MMC_SDHC2,
.end = MX31_INT_MMC_SDHC2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxcsdhc_device0 = {
.name = "mxc-mmc",
.id = 0,
.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
.resource = mxcsdhc0_resources,
};
struct platform_device mxcsdhc_device1 = {
.name = "mxc-mmc",
.id = 1,
.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
.resource = mxcsdhc1_resources,
};
static struct resource rnga_resources[] = {
{
.start = RNGA_BASE_ADDR,
.end = RNGA_BASE_ADDR + 0x28,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_rnga_device = {
.name = "mxc_rnga",
.id = -1,
.num_resources = 1,
.resource = rnga_resources,
};
#endif /* CONFIG_ARCH_MX31 */
/* i.MX31 Image Processing Unit */
/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
{
.start = IPU_CTRL_BASE_ADDR,
.end = IPU_CTRL_BASE_ADDR + 0x5F,
.start = MX3x_IPU_CTRL_BASE_ADDR,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
.flags = IORESOURCE_MEM,
}, {
.start = IPU_CTRL_BASE_ADDR + 0x88,
.end = IPU_CTRL_BASE_ADDR + 0xB3,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_IPU_SYN,
.end = MXC_INT_IPU_SYN,
.start = MX3x_INT_IPU_SYN,
.end = MX3x_INT_IPU_SYN,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC_INT_IPU_ERR,
.end = MXC_INT_IPU_ERR,
.start = MX3x_INT_IPU_ERR,
.end = MX3x_INT_IPU_ERR,
.flags = IORESOURCE_IRQ,
},
};
@ -156,8 +61,8 @@ struct platform_device mx3_ipu = {
static struct resource fb_resources[] = {
{
.start = IPU_CTRL_BASE_ADDR + 0xB4,
.end = IPU_CTRL_BASE_ADDR + 0x1BF,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
.flags = IORESOURCE_MEM,
},
};
@ -174,8 +79,8 @@ struct platform_device mx3_fb = {
static struct resource camera_resources[] = {
{
.start = IPU_CTRL_BASE_ADDR + 0x60,
.end = IPU_CTRL_BASE_ADDR + 0x87,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
.flags = IORESOURCE_MEM,
},
};
@ -190,110 +95,6 @@ struct platform_device mx3_camera = {
},
};
static struct resource otg_resources[] = {
{
.start = MX31_OTG_BASE_ADDR,
.end = MX31_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB3,
.end = MXC_INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
static u64 otg_dmamask = DMA_BIT_MASK(32);
/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* OTG host */
struct platform_device mxc_otg_host = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* USB host 1 */
static u64 usbh1_dmamask = ~(u32)0;
static struct resource mxc_usbh1_resources[] = {
{
.start = MX31_OTG_BASE_ADDR + 0x200,
.end = MX31_OTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB1,
.end = MXC_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh1_dmamask,
},
.resource = mxc_usbh1_resources,
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};
/* USB host 2 */
static u64 usbh2_dmamask = ~(u32)0;
static struct resource mxc_usbh2_resources[] = {
{
.start = MX31_OTG_BASE_ADDR + 0x400,
.end = MX31_OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB2,
.end = MXC_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 2,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
static struct resource imx_wdt_resources[] = {
{
.flags = IORESOURCE_MEM,
},
};
struct platform_device imx_wdt_device0 = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(imx_wdt_resources),
.resource = imx_wdt_resources,
};
static struct resource imx_rtc_resources[] = {
{
.start = MX31_RTC_BASE_ADDR,
@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = {
.num_resources = ARRAY_SIZE(imx_rtc_resources),
.resource = imx_rtc_resources,
};
static struct resource imx_kpp_resources[] = {
{
.start = MX3x_KPP_BASE_ADDR,
.end = MX3x_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM
}, {
.start = MX3x_INT_KPP,
.end = MX3x_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(imx_kpp_resources),
.resource = imx_kpp_resources,
};
static int __init mx3_devices_init(void)
{
#if defined(CONFIG_ARCH_MX31)
if (cpu_is_mx31()) {
imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
mxc_register_device(&mxc_rnga_device, NULL);
}
#endif
#if defined(CONFIG_ARCH_MX35)
if (cpu_is_mx35()) {
otg_resources[0].start = MX35_OTG_BASE_ADDR;
otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
otg_resources[1].start = MXC_INT_USBOTG;
otg_resources[1].end = MXC_INT_USBOTG;
mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
mxc_usbh1_resources[1].start = MXC_INT_USBHS;
mxc_usbh1_resources[1].end = MXC_INT_USBHS;
imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
}
#endif
return 0;
}
subsys_initcall(mx3_devices_init);

10
arch/arm/mach-mx3/devices.h
View File

@ -1,14 +1,4 @@
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mx3_ipu;
extern struct platform_device mx3_fb;
extern struct platform_device mx3_camera;
extern struct platform_device mxcsdhc_device0;
extern struct platform_device mxcsdhc_device1;
extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_rnga_device;
extern struct platform_device imx_wdt_device0;
extern struct platform_device imx_rtc_device0;
extern struct platform_device imx_kpp_device;

4
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
View File

@ -111,7 +111,7 @@ static struct mx3fb_platform_data mx3fb_pdata = {
.num_modes = ARRAY_SIZE(fb_modedb),
};
static struct pad_desc eukrea_mbimxsd_pads[] = {
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LCD */
MX35_PAD_LD0__IPU_DISPB_DAT_0,
MX35_PAD_LD1__IPU_DISPB_DAT_1,
@ -289,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx35_add_flexcan1(NULL);
imx35_add_esdhc(0, NULL);
imx35_add_sdhci_esdhc_imx(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);

14
arch/arm/mach-mx3/mach-armadillo5x0.c
View File

@ -49,10 +49,8 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/mmc.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
@ -245,13 +243,13 @@ h2_free_cs:
return err;
}
static struct mxc_usbh_platform_data usbotg_pdata = {
static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
.init = usbotg_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
@ -453,7 +451,7 @@ static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.get_ro = armadillo5x0_sdhc1_get_ro,
.init = armadillo5x0_sdhc1_init,
.exit = armadillo5x0_sdhc1_exit,
@ -520,7 +518,7 @@ static void __init armadillo5x0_init(void)
gpio_direction_input(MX31_PIN_GPIO1_0);
/* Register SDHC */
mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
imx31_add_mxc_mmc(0, &sdhc_pdata);
/* Register FB */
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
@ -555,8 +553,8 @@ static void __init armadillo5x0_init(void)
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &usbotg_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx31_add_mxc_ehci_otg(&usbotg_pdata);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
}

22
arch/arm/mach-mx3/mach-cpuimx35.c
View File

@ -30,7 +30,6 @@
#include <linux/i2c/tsc2007.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <linux/i2c-gpio.h>
#include <asm/mach-types.h>
@ -43,7 +42,6 @@
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include "devices-imx35.h"
#include "devices.h"
@ -74,11 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
},
};
static struct platform_device *devices[] __initdata = {
&imx_wdt_device0,
};
static struct pad_desc eukrea_cpuimx35_pads[] = {
static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
MX35_PAD_RTS1__UART1_RTS,
@ -117,18 +111,18 @@ static const struct mxc_nand_platform_data
.flash_bbt = 1,
};
static struct mxc_usbh_platform_data __maybe_unused otg_pdata = {
static const struct mxc_usbh_platform_data otg_pdata __initconst = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = {
static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
MXC_EHCI_IPPUE_DOWN,
};
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
.workaround = FLS_USB2_WORKAROUND_ENGCM09152,
@ -158,7 +152,7 @@ static void __init mxc_board_init(void)
ARRAY_SIZE(eukrea_cpuimx35_pads));
imx35_add_fec(NULL);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx35_add_imx2_wdt(NULL);
imx35_add_imx_uart0(&uart_pdata);
imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
@ -168,11 +162,11 @@ static void __init mxc_board_init(void)
imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
if (otg_mode_host)
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx35_add_mxc_ehci_otg(&otg_pdata);
else
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx35_add_fsl_usb2_udc(&otg_device_pdata);
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
imx35_add_mxc_ehci_hs(&usbh1_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
eukrea_mbimxsd35_baseboard_init();

6
arch/arm/mach-mx3/mach-kzm_arm11_01.c
View File

@ -41,9 +41,9 @@
#include "devices-imx31.h"
#include "devices.h"
#define KZM_ARM11_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX31_CS4) ?: \
IMX_IO_ADDRESS(x, MX31_CS5) ?: \
#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
MX31_IO_ADDRESS(x))
/*

124
arch/arm/mach-mx3/mach-mx31_3ds.c
View File

@ -22,8 +22,8 @@
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
#include <linux/fsl_devices.h>
#include <linux/input/matrix_keypad.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -34,6 +34,7 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/3ds_debugboard.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
@ -84,6 +85,21 @@ static int mx31_3ds_pins[] = {
MX31_PIN_KEY_COL1_KEY_COL1,
MX31_PIN_KEY_COL2_KEY_COL2,
MX31_PIN_KEY_COL3_KEY_COL3,
/* USB Host 2 */
IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
/* USB Host2 reset */
IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
};
/*
@ -102,7 +118,7 @@ static const uint32_t mx31_3ds_keymap[] = {
KEY(2, 3, KEY_F10),
};
static struct matrix_keymap_data mx31_3ds_keymap_data = {
static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
.keymap = mx31_3ds_keymap,
.keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
};
@ -115,6 +131,13 @@ static struct regulator_init_data pwgtx_init = {
},
};
static struct regulator_init_data gpo_init = {
.constraints = {
.boot_on = 1,
.always_on = 1,
}
};
static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
{
.id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
@ -122,6 +145,13 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
}, {
.id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
.init_data = &pwgtx_init,
}, {
.id = MC13783_REGU_GPO1, /* Turn on 1.8V */
.init_data = &gpo_init,
}, {
.id = MC13783_REGU_GPO3, /* Turn on 3.3V */
.init_data = &gpo_init,
},
};
@ -129,7 +159,7 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
static struct mc13783_platform_data mc13783_pdata __initdata = {
.regulators = mx31_3ds_regulators,
.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
.flags = MC13783_USE_REGULATOR,
.flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
};
/* SPI */
@ -175,6 +205,7 @@ mx31_3ds_nand_board_info __initconst = {
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
static int mx31_3ds_usbotg_init(void)
{
@ -214,11 +245,77 @@ usbotg_free_reset:
return err;
}
static struct fsl_usb2_platform_data usbotg_pdata = {
static int mx31_3ds_host2_init(struct platform_device *pdev)
{
int err;
mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
err = gpio_request(USBH2_RST_B, "usbh2-reset");
if (err) {
pr_err("Failed to request the USB Host 2 reset gpio\n");
return err;
}
err = gpio_direction_output(USBH2_RST_B, 0);
if (err) {
pr_err("Failed to drive the USB Host 2 reset gpio\n");
goto usbotg_free_reset;
}
mdelay(1);
gpio_set_value(USBH2_RST_B, 1);
return 0;
usbotg_free_reset:
gpio_free(USBH2_RST_B);
return err;
}
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = mx31_3ds_host2_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
#endif
static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static int otg_mode_host;
static int __init mx31_3ds_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", mx31_3ds_otg_mode);
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@ -246,14 +343,27 @@ static void __init mxc_board_init(void)
spi_register_board_info(mx31_3ds_spi_devs,
ARRAY_SIZE(mx31_3ds_spi_devs));
mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
imx31_add_imx_keypad(&mx31_3ds_keymap_data);
mx31_3ds_usbotg_init();
mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
imx31_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host)
imx31_add_fsl_usb2_udc(&usbotg_pdata);
if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
printk(KERN_WARNING "Init of the debug board failed, all "
"devices on the debug board are unusable.\n");
imx31_add_imx2_wdt(NULL);
}
static void __init mx31_3ds_timer_init(void)

9
arch/arm/mach-mx3/mach-mx31lilly.c
View File

@ -42,7 +42,6 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lilly.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
@ -230,13 +229,13 @@ static struct mxc_usbh_platform_data usbotg_pdata = {
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static struct mxc_usbh_platform_data usbh1_pdata = {
static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
.init = usbh1_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
@ -249,8 +248,8 @@ static void lilly1131_usb_init(void)
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
}
#else

5
arch/arm/mach-mx3/mach-mx31lite.c
View File

@ -40,7 +40,6 @@
#include <mach/board-mx31lite.h>
#include <mach/iomux-mx3.h>
#include <mach/irqs.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
@ -171,7 +170,7 @@ static int usbh2_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
@ -258,7 +257,7 @@ static void __init mxc_board_init(void)
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
/* SMSC9117 IRQ pin */

20
arch/arm/mach-mx3/mach-mx31moboard.c
View File

@ -40,8 +40,6 @@
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/mx3_camera.h>
#include <mach/spi.h>
#include <mach/ulpi.h>
@ -170,11 +168,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = {
static struct regulator_consumer_supply sdhc_consumers[] = {
{
.dev = &mxcsdhc_device0.dev,
.dev_name = "mxc-mmc.0",
.supply = "sdhc0_vcc",
},
{
.dev = &mxcsdhc_device1.dev,
.dev_name = "mxc-mmc.1",
.supply = "sdhc1_vcc",
},
};
@ -345,7 +343,7 @@ static void moboard_sdhc1_exit(struct device *dev, void *data)
gpio_free(SDHC1_CD);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.get_ro = moboard_sdhc1_get_ro,
.init = moboard_sdhc1_init,
.exit = moboard_sdhc1_exit,
@ -404,17 +402,23 @@ static void usb_xcvr_reset(void)
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static int __init moboard_usbh2_init(void)
{
struct platform_device *pdev;
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
return mxc_register_device(&mxc_usbh2, &usbh2_pdata);
pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return 0;
}
#else
static inline int moboard_usbh2_init(void) { return 0; }
@ -520,7 +524,7 @@ static void __init mxc_board_init(void)
spi_register_board_info(moboard_spi_board_info,
ARRAY_SIZE(moboard_spi_board_info));
mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
imx31_add_mxc_mmc(0, &sdhc1_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))

40
arch/arm/mach-mx3/mach-mx35_3ds.c
View File

@ -26,7 +26,7 @@
#include <linux/platform_device.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/fsl_devices.h>
#include <linux/usb/otg.h>
#include <linux/mtd/physmap.h>
@ -40,7 +40,6 @@
#include <mach/iomux-mx35.h>
#include <mach/irqs.h>
#include <mach/3ds_debugboard.h>
#include <mach/mxc_ehci.h>
#include "devices-imx35.h"
#include "devices.h"
@ -81,7 +80,7 @@ static struct platform_device *devices[] __initdata = {
&mx35pdk_flash,
};
static struct pad_desc mx35pdk_pads[] = {
static iomux_v3_cfg_t mx35pdk_pads[] = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
MX35_PAD_RTS1__UART1_RTS,
@ -122,18 +121,38 @@ static struct pad_desc mx35pdk_pads[] = {
};
/* OTG config */
static struct fsl_usb2_platform_data usb_otg_pdata = {
static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
};
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERNAL_PHY,
};
/* USB HOST config */
static struct mxc_usbh_platform_data usb_host_pdata = {
static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
MXC_EHCI_INTERNAL_PHY,
};
static int otg_mode_host;
static int __init mx35_3ds_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", mx35_3ds_otg_mode);
/*
* Board specific initialization.
*/
@ -142,16 +161,21 @@ static void __init mxc_board_init(void)
mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
imx35_add_fec(NULL);
imx35_add_imx2_wdt(NULL);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx35_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata);
if (otg_mode_host)
imx35_add_mxc_ehci_otg(&otg_pdata);
mxc_register_device(&mxc_usbh1, &usb_host_pdata);
imx35_add_mxc_ehci_hs(&usb_host_pdata);
if (!otg_mode_host)
imx35_add_fsl_usb2_udc(&usb_otg_pdata);
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
imx35_add_esdhc(0, NULL);
imx35_add_sdhci_esdhc_imx(0, NULL);
if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
pr_warn("Init of the debugboard failed, all "

23
arch/arm/mach-mx3/mach-pcm037.c
View File

@ -27,7 +27,6 @@
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <linux/can/platform/sja1000.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
@ -43,10 +42,8 @@
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mmc.h>
#include <mach/mx3_camera.h>
#include <mach/mx3fb.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
@ -399,7 +396,7 @@ static void pcm970_sdhc1_exit(struct device *dev, void *data)
gpio_free(SDHC1_GPIO_WP);
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
#ifdef PCM970_SDHC_RW_SWITCH
.get_ro = pcm970_sdhc1_get_ro,
#endif
@ -441,7 +438,6 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
static struct platform_device *devices[] __initdata = {
&pcm037_flash,
&pcm037_sram_device,
&imx_wdt_device0,
&pcm037_mt9t031,
&pcm037_mt9v022,
};
@ -538,18 +534,18 @@ static struct platform_device pcm970_sja1000 = {
};
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
@ -607,12 +603,13 @@ static void __init mxc_board_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
imx31_add_imx2_wdt(NULL);
imx31_add_imx_uart0(&uart_pdata);
/* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
imx31_add_imx_uart1(&uart_pdata);
imx31_add_imx_uart2(&uart_pdata);
mxc_register_device(&mxc_w1_master_device, NULL);
imx31_add_mxc_w1(NULL);
/* LAN9217 IRQ pin */
ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
@ -632,7 +629,7 @@ static void __init mxc_board_init(void)
imx31_add_imx_i2c2(&pcm037_i2c2_data);
imx31_add_mxc_nand(&pcm037_nand_board_info);
mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
imx31_add_mxc_mmc(0, &sdhc_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
@ -654,16 +651,16 @@ static void __init mxc_board_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx31_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx31_add_fsl_usb2_udc(&otg_device_pdata);
}

48
arch/arm/mach-mx3/mach-pcm043.c
View File

@ -27,7 +27,6 @@
#include <linux/i2c/at24.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -39,7 +38,6 @@
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/audmux.h>
@ -140,10 +138,9 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
static struct platform_device *devices[] __initdata = {
&pcm043_flash,
&imx_wdt_device0,
};
static struct pad_desc pcm043_pads[] = {
static iomux_v3_cfg_t pcm043_pads[] = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
MX35_PAD_RTS1__UART1_RTS,
@ -230,8 +227,8 @@ static struct pad_desc pcm043_pads[] = {
static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
{
struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
int ret;
ret = gpio_request(AC97_GPIO_TXFS, "SSI");
@ -240,7 +237,7 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
return;
}
mxc_iomux_v3_setup_pad(&txfs_gpio);
mxc_iomux_v3_setup_pad(txfs_gpio);
/* warm reset */
gpio_direction_output(AC97_GPIO_TXFS, 1);
@ -248,16 +245,16 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
gpio_set_value(AC97_GPIO_TXFS, 0);
gpio_free(AC97_GPIO_TXFS);
mxc_iomux_v3_setup_pad(&txfs);
mxc_iomux_v3_setup_pad(txfs);
}
static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
{
struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
int ret;
ret = gpio_request(AC97_GPIO_TXFS, "SSI");
@ -272,9 +269,9 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
if (ret)
goto err3;
mxc_iomux_v3_setup_pad(&txfs_gpio);
mxc_iomux_v3_setup_pad(&txd_gpio);
mxc_iomux_v3_setup_pad(&reset_gpio);
mxc_iomux_v3_setup_pad(txfs_gpio);
mxc_iomux_v3_setup_pad(txd_gpio);
mxc_iomux_v3_setup_pad(reset_gpio);
gpio_direction_output(AC97_GPIO_TXFS, 0);
gpio_direction_output(AC97_GPIO_TXD, 0);
@ -284,8 +281,8 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
udelay(10);
gpio_direction_output(AC97_GPIO_RESET, 1);
mxc_iomux_v3_setup_pad(&txd);
mxc_iomux_v3_setup_pad(&txfs);
mxc_iomux_v3_setup_pad(txd);
mxc_iomux_v3_setup_pad(txfs);
gpio_free(AC97_GPIO_RESET);
err3:
@ -311,19 +308,19 @@ pcm037_nand_board_info __initconst = {
};
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh1_pdata = {
static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
MXC_EHCI_IPPUE_DOWN,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
@ -364,6 +361,7 @@ static void __init mxc_board_init(void)
imx35_add_fec(NULL);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx35_add_imx2_wdt(NULL);
imx35_add_imx_uart0(&uart_pdata);
imx35_add_mxc_nand(&pcm037_nand_board_info);
@ -386,16 +384,16 @@ static void __init mxc_board_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx35_add_mxc_ehci_otg(&otg_pdata);
}
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
imx35_add_mxc_ehci_hs(&usbh1_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx35_add_fsl_usb2_udc(&otg_device_pdata);
imx35_add_flexcan1(NULL);
imx35_add_esdhc(0, NULL);
imx35_add_sdhci_esdhc_imx(0, NULL);
}
static void __init pcm043_timer_init(void)

84
arch/arm/mach-mx3/mm.c
View File

@ -36,40 +36,16 @@
* @ingroup Memory
*/
/*!
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX3 boards.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
.length = X_MEMC_SIZE,
.type = MT_DEVICE
}, {
.virtual = AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AVIC_BASE_ADDR),
.length = AVIC_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
.length = AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
.length = SPBA0_SIZE,
.type = MT_DEVICE_NONSHARED
},
#ifdef CONFIG_SOC_IMX31
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};
/*!
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
@ -77,34 +53,44 @@ static struct map_desc mxc_io_desc[] __initdata = {
void __init mx31_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
#ifdef CONFIG_ARCH_MX35
int imx31_register_gpios(void);
void __init mx31_init_irq(void)
{
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
imx31_register_gpios();
}
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};
void __init mx35_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}
#endif
int imx3x_register_gpios(void);
void __init mx31_init_irq(void)
{
mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
imx3x_register_gpios();
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
int imx35_register_gpios(void);
void __init mx35_init_irq(void)
{
mx31_init_irq();
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
imx35_register_gpios();
}
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_CACHE_L2X0
static int mxc_init_l2x0(void)
@ -129,7 +115,7 @@ static int mxc_init_l2x0(void)
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));

5
arch/arm/mach-mx3/mx31lilly-db.c
View File

@ -34,7 +34,6 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lilly.h>
#include <mach/mmc.h>
#include <mach/mx3fb.h>
#include <mach/ipu.h>
@ -158,7 +157,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
}
static struct imxmmc_platform_data mmc_pdata = {
static const struct imxmmc_platform_data mmc_pdata __initconst = {
.get_ro = mxc_mmc1_get_ro,
.init = mxc_mmc1_init,
.exit = mxc_mmc1_exit,
@ -216,7 +215,7 @@ void __init mx31lilly_db_init(void)
imx31_add_imx_uart0(&uart_pdata);
imx31_add_imx_uart1(&uart_pdata);
imx31_add_imx_uart2(&uart_pdata);
mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
imx31_add_mxc_mmc(0, &mmc_pdata);
mx31lilly_init_fb();
}

8
arch/arm/mach-mx3/mx31lite-db.c
View File

@ -35,7 +35,6 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lite.h>
#include <mach/mmc.h>
#include "devices-imx31.h"
#include "devices.h"
@ -142,7 +141,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
}
static struct imxmmc_platform_data mmc_pdata = {
static const struct imxmmc_platform_data mmc_pdata __initconst = {
.get_ro = mxc_mmc1_get_ro,
.init = mxc_mmc1_init,
.exit = mxc_mmc1_exit,
@ -197,10 +196,9 @@ void __init mx31lite_db_init(void)
ARRAY_SIZE(litekit_db_board_pins),
"development board pins");
imx31_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
imx31_add_mxc_mmc(0, &mmc_pdata);
imx31_add_spi_imx0(&spi0_pdata);
platform_device_register(&litekit_led_device);
mxc_register_device(&imx_wdt_device0, NULL);
imx31_add_imx2_wdt(NULL);
mxc_register_device(&imx_rtc_device0, NULL);
}

20
arch/arm/mach-mx3/mx31moboard-devboard.c
View File

@ -18,15 +18,12 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/fsl_devices.h>
#include <linux/usb/otg.h>
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
@ -103,7 +100,7 @@ static void devboard_sdhc2_exit(struct device *dev, void *data)
gpio_free(SDHC2_CD);
}
static struct imxmmc_platform_data sdhc2_pdata = {
static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
.get_ro = devboard_sdhc2_get_ro,
.init = devboard_sdhc2_init,
.exit = devboard_sdhc2_exit,
@ -187,7 +184,7 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
return 0;
}
static struct mxc_usbh_platform_data usbh1_pdata = {
static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
.init = devboard_usbh1_hw_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
@ -196,6 +193,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
static int __init devboard_usbh1_init(void)
{
struct otg_transceiver *otg;
struct platform_device *pdev;
otg = kzalloc(sizeof(*otg), GFP_KERNEL);
if (!otg)
@ -207,11 +205,15 @@ static int __init devboard_usbh1_init(void)
usbh1_pdata.otg = otg;
return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return 0;
}
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
@ -228,11 +230,11 @@ void __init mx31moboard_devboard_init(void)
imx31_add_imx_uart1(&uart_pdata);
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
imx31_add_mxc_mmc(1, &sdhc2_pdata);
devboard_init_sel_gpios();
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
imx31_add_fsl_usb2_udc(&usb_pdata);
devboard_usbh1_init();
}

21
arch/arm/mach-mx3/mx31moboard-marxbot.c
View File

@ -21,7 +21,6 @@
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/fsl_devices.h>
#include <linux/usb/otg.h>
@ -29,12 +28,11 @@
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int marxbot_pins[] = {
@ -116,7 +114,7 @@ static void marxbot_sdhc2_exit(struct device *dev, void *data)
gpio_free(SDHC2_CD);
}
static struct imxmmc_platform_data sdhc2_pdata = {
static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
.get_ro = marxbot_sdhc2_get_ro,
.init = marxbot_sdhc2_init,
.exit = marxbot_sdhc2_exit,
@ -302,7 +300,7 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
return 0;
}
static struct mxc_usbh_platform_data usbh1_pdata = {
static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
.init = marxbot_usbh1_hw_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
@ -311,6 +309,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
static int __init marxbot_usbh1_init(void)
{
struct otg_transceiver *otg;
struct platform_device *pdev;
otg = kzalloc(sizeof(*otg), GFP_KERNEL);
if (!otg)
@ -322,10 +321,14 @@ static int __init marxbot_usbh1_init(void)
usbh1_pdata.otg = otg;
return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return 0;
}
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
@ -344,7 +347,7 @@ void __init mx31moboard_marxbot_init(void)
dspics_resets_init();
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
imx31_add_mxc_mmc(1, &sdhc2_pdata);
spi_register_board_info(marxbot_spi_board_info,
ARRAY_SIZE(marxbot_spi_board_info));
@ -357,7 +360,7 @@ void __init mx31moboard_marxbot_init(void)
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
imx31_add_fsl_usb2_udc(&usb_pdata);
marxbot_usbh1_init();
}

16
arch/arm/mach-mx3/mx31moboard-smartbot.c
View File

@ -19,7 +19,6 @@
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/fsl_devices.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
@ -28,7 +27,6 @@
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31moboard.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
@ -118,24 +116,30 @@ static int __init smartbot_cam_init(void)
return 0;
}
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_host_pdata = {
static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static int __init smartbot_otg_host_init(void)
{
struct platform_device *pdev;
otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
return mxc_register_device(&mxc_otg_host, &otg_host_pdata);
pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return 0;
}
#else
static inline int smartbot_otg_host_init(void) { return 0; }
@ -182,7 +186,7 @@ void __init mx31moboard_smartbot_init(int board)
switch (board) {
case MX31SMARTBOT:
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
imx31_add_fsl_usb2_udc(&usb_pdata);
break;
case MX31EYEBOT:
smartbot_otg_host_init();

63
arch/arm/mach-mx5/Kconfig
View File

@ -1,20 +1,47 @@
if ARCH_MX5
# ARCH_MX51 and ARCH_MX50 are left for compatibility
config ARCH_MX50
bool
config ARCH_MX51
bool
default y
config ARCH_MX53
bool
config SOC_IMX50
bool
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
select ARCH_MX50
config SOC_IMX51
bool
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
select ARCH_MX51
config SOC_IMX53
bool
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MX53
comment "MX5 platforms:"
config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
select SOC_IMX51
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX51 Babbage platform, also known as MX51EVK in
u-boot. This includes specific configurations for the board and its
@ -22,7 +49,9 @@ config MACH_MX51_BABBAGE
config MACH_MX51_3DS
bool "Support MX51PDK (3DS)"
select SOC_IMX51
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_DEBUG_BOARD
help
@ -31,6 +60,7 @@ config MACH_MX51_3DS
config MACH_EUKREA_CPUIMX51
bool "Support Eukrea CPUIMX51 module"
select SOC_IMX51
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
@ -47,7 +77,7 @@ choice
config MACH_EUKREA_MBIMX51_BASEBOARD
prompt "Eukrea MBIMX51 development board"
bool
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
This adds board specific devices that can be found on Eukrea's
MBIMX51 evaluation board.
@ -56,6 +86,7 @@ endchoice
config MACH_EUKREA_CPUIMX51SD
bool "Support Eukrea CPUIMX51SD module"
select SOC_IMX51
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_IMX_UART
@ -72,7 +103,7 @@ choice
config MACH_EUKREA_MBIMXSD51_BASEBOARD
prompt "Eukrea MBIMXSD development board"
bool
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
@ -81,9 +112,33 @@ endchoice
config MACH_MX51_EFIKAMX
bool "Support MX51 Genesi Efika MX nettop"
select SOC_IMX51
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for Genesi Efika MX nettop. This includes specific
configurations for the board and its peripherals.
config MACH_MX53_EVK
bool "Support MX53 EVK platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for MX53 EVK platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX50_RDP
bool "Support MX50 reference design platform"
depends on BROKEN
select SOC_IMX50
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX50 reference design platform (RDP) board. This
includes specific configurations for the board and its peripherals.
endif

5
arch/arm/mach-mx5/Makefile
View File

@ -3,13 +3,16 @@
#
# Object file lists.
obj-y := cpu.o mm.o clock-mx51.o devices.o
obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o
obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o

12
arch/arm/mach-mx5/Makefile.boot
View File

@ -1,3 +1,9 @@
zreladdr-y := 0x90008000
params_phys-y := 0x90000100
initrd_phys-y := 0x90800000
zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000
params_phys-$(CONFIG_ARCH_MX50) := 0x70000100
initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000
zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000
params_phys-$(CONFIG_ARCH_MX51) := 0x90000100
initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000
zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000
params_phys-$(CONFIG_ARCH_MX53) := 0x70000100
initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000

32
arch/arm/mach-mx5/board-cpuimx51.c
View File

@ -40,11 +40,11 @@
#include "devices-imx51.h"
#include "devices.h"
#define CPUIMX51_USBH1_STP (0*32 + 27)
#define CPUIMX51_QUARTA_GPIO (2*32 + 28)
#define CPUIMX51_QUARTB_GPIO (2*32 + 25)
#define CPUIMX51_QUARTC_GPIO (2*32 + 26)
#define CPUIMX51_QUARTD_GPIO (2*32 + 27)
#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
@ -113,7 +113,7 @@ static struct platform_device *devices[] __initdata = {
#endif
};
static struct pad_desc eukrea_cpuimx51_pads[] = {
static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
@ -121,15 +121,15 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
MX51_PAD_UART1_CTS__UART1_CTS,
/* I2C2 */
MX51_PAD_GPIO_1_2__I2C2_SCL,
MX51_PAD_GPIO_1_3__I2C2_SDA,
MX51_PAD_NANDF_D10__GPIO_3_30,
MX51_PAD_GPIO1_2__I2C2_SCL,
MX51_PAD_GPIO1_3__I2C2_SDA,
MX51_PAD_NANDF_D10__GPIO3_30,
/* QUART IRQ */
MX51_PAD_NANDF_D15__GPIO_3_25,
MX51_PAD_NANDF_D14__GPIO_3_26,
MX51_PAD_NANDF_D13__GPIO_3_27,
MX51_PAD_NANDF_D12__GPIO_3_28,
MX51_PAD_NANDF_D15__GPIO3_25,
MX51_PAD_NANDF_D14__GPIO3_26,
MX51_PAD_NANDF_D13__GPIO3_27,
MX51_PAD_NANDF_D12__GPIO3_28,
/* USB HOST1 */
MX51_PAD_USBH1_CLK__USBH1_CLK,
@ -178,6 +178,8 @@ static int initialize_otg_port(struct platform_device *pdev)
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* Set the PHY clock to 19.2MHz */
@ -196,6 +198,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* The clock for the USBH1 ULPI port will come externally from the PHY. */
@ -292,7 +296,7 @@ static struct sys_timer mxc_timer = {
MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
/* Maintainer: Eric Bénard <eric@eukrea.com> */
.boot_params = PHYS_OFFSET + 0x100,
.boot_params = MX51_PHYS_OFFSET + 0x100,
.map_io = mx51_map_io,
.init_irq = mx51_init_irq,
.init_machine = eukrea_cpuimx51_init,

68
arch/arm/mach-mx5/board-cpuimx51sd.c
View File

@ -43,19 +43,19 @@
#include "devices-imx51.h"
#include "devices.h"
#define USBH1_RST (1*32 + 28)
#define ETH_RST (1*32 + 31)
#define TSC2007_IRQGPIO (2*32 + 12)
#define CAN_IRQGPIO (0*32 + 1)
#define CAN_RST (3*32 + 15)
#define CAN_NCS (3*32 + 24)
#define CAN_RXOBF (0*32 + 4)
#define CAN_RX1BF (0*32 + 6)
#define CAN_TXORTS (0*32 + 7)
#define CAN_TX1RTS (0*32 + 8)
#define CAN_TX2RTS (0*32 + 9)
#define I2C_SCL (3*32 + 16)
#define I2C_SDA (3*32 + 17)
#define USBH1_RST IMX_GPIO_NR(2, 28)
#define ETH_RST IMX_GPIO_NR(2, 31)
#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
#define CAN_RST IMX_GPIO_NR(4, 15)
#define CAN_NCS IMX_GPIO_NR(4, 24)
#define CAN_RXOBF IMX_GPIO_NR(1, 4)
#define CAN_RX1BF IMX_GPIO_NR(1, 6)
#define CAN_TXORTS IMX_GPIO_NR(1, 7)
#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
#define I2C_SCL IMX_GPIO_NR(4, 16)
#define I2C_SDA IMX_GPIO_NR(4, 17)
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
@ -65,10 +65,7 @@
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
#define MX51_USB_PLL_DIV_24_MHZ 0x02
#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
static struct pad_desc eukrea_cpuimx51sd_pads[] = {
static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
@ -88,30 +85,33 @@ static struct pad_desc eukrea_cpuimx51sd_pads[] = {
MX51_PAD_USBH1_DATA6__USBH1_DATA6,
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
MX51_PAD_USBH1_STP__USBH1_STP,
MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */
MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
/* FEC */
MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */
MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
/* HSI2C */
MX51_PAD_I2C1_CLK__GPIO_4_16,
MX51_PAD_I2C1_DAT__GPIO_4_17,
MX51_PAD_I2C1_CLK__GPIO4_16,
MX51_PAD_I2C1_DAT__GPIO4_17,
/* CAN */
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */
MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */
MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */
MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */
MX51_PAD_GPIO_1_6__GPIO_1_6,
MX51_PAD_GPIO_1_7__GPIO_1_7,
MX51_PAD_GPIO_1_8__GPIO_1_8,
MX51_PAD_GPIO_1_9__GPIO_1_9,
MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
MX51_PAD_GPIO1_6__GPIO1_6,
MX51_PAD_GPIO1_7__GPIO1_7,
MX51_PAD_GPIO1_8__GPIO1_8,
MX51_PAD_GPIO1_9__GPIO1_9,
/* Touchscreen */
CPUIMX51SD_GPIO_3_12, /* IRQ */
/* IRQ */
_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@ -157,6 +157,8 @@ static int initialize_otg_port(struct platform_device *pdev)
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* Set the PHY clock to 19.2MHz */
@ -175,6 +177,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* The clock for the USBH1 ULPI port will come from the PHY. */
@ -243,7 +247,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
.mode = SPI_MODE_0,
.chip_select = 0,
.platform_data = &mcp251x_info,
.irq = gpio_to_irq(0 * 32 + 1)
.irq = gpio_to_irq(CAN_IRQGPIO)
},
};
@ -323,7 +327,7 @@ static struct sys_timer mxc_timer = {
MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
/* Maintainer: Eric Bénard <eric@eukrea.com> */
.boot_params = PHYS_OFFSET + 0x100,
.boot_params = MX51_PHYS_OFFSET + 0x100,
.map_io = mx51_map_io,
.init_irq = mx51_init_irq,
.init_machine = eukrea_cpuimx51sd_init,

197
arch/arm/mach-mx5/board-mx50_rdp.c Normal file
View File

@ -0,0 +1,197 @@
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx50.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-mx50.h"
static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
/* SD1 */
MX50_PAD_ECSPI2_SS0__GPIO_4_19,
MX50_PAD_EIM_CRE__GPIO_1_27,
MX50_PAD_SD1_CMD__SD1_CMD,
MX50_PAD_SD1_CLK__SD1_CLK,
MX50_PAD_SD1_D0__SD1_D0,
MX50_PAD_SD1_D1__SD1_D1,
MX50_PAD_SD1_D2__SD1_D2,
MX50_PAD_SD1_D3__SD1_D3,
/* SD2 */
MX50_PAD_SD2_CD__GPIO_5_17,
MX50_PAD_SD2_WP__GPIO_5_16,
MX50_PAD_SD2_CMD__SD2_CMD,
MX50_PAD_SD2_CLK__SD2_CLK,
MX50_PAD_SD2_D0__SD2_D0,
MX50_PAD_SD2_D1__SD2_D1,
MX50_PAD_SD2_D2__SD2_D2,
MX50_PAD_SD2_D3__SD2_D3,
MX50_PAD_SD2_D4__SD2_D4,
MX50_PAD_SD2_D5__SD2_D5,
MX50_PAD_SD2_D6__SD2_D6,
MX50_PAD_SD2_D7__SD2_D7,
/* SD3 */
MX50_PAD_SD3_CMD__SD3_CMD,
MX50_PAD_SD3_CLK__SD3_CLK,
MX50_PAD_SD3_D0__SD3_D0,
MX50_PAD_SD3_D1__SD3_D1,
MX50_PAD_SD3_D2__SD3_D2,
MX50_PAD_SD3_D3__SD3_D3,
MX50_PAD_SD3_D4__SD3_D4,
MX50_PAD_SD3_D5__SD3_D5,
MX50_PAD_SD3_D6__SD3_D6,
MX50_PAD_SD3_D7__SD3_D7,
/* PWR_INT */
MX50_PAD_ECSPI2_MISO__GPIO_4_18,
/* UART pad setting */
MX50_PAD_UART1_TXD__UART1_TXD,
MX50_PAD_UART1_RXD__UART1_RXD,
MX50_PAD_UART1_RTS__UART1_RTS,
MX50_PAD_UART2_TXD__UART2_TXD,
MX50_PAD_UART2_RXD__UART2_RXD,
MX50_PAD_UART2_CTS__UART2_CTS,
MX50_PAD_UART2_RTS__UART2_RTS,
MX50_PAD_I2C1_SCL__I2C1_SCL,
MX50_PAD_I2C1_SDA__I2C1_SDA,
MX50_PAD_I2C2_SCL__I2C2_SCL,
MX50_PAD_I2C2_SDA__I2C2_SDA,
MX50_PAD_EPITO__USBH1_PWR,
/* Need to comment below line if
* one needs to debug owire.
*/
MX50_PAD_OWIRE__USBH1_OC,
/* using gpio to control otg pwr */
MX50_PAD_PWM2__GPIO_6_25,
MX50_PAD_I2C3_SCL__USBOTG_OC,
MX50_PAD_SSI_RXC__FEC_MDIO,
MX50_PAD_SSI_RXC__FEC_MDIO,
MX50_PAD_DISP_D0__FEC_TXCLK,
MX50_PAD_DISP_D1__FEC_RX_ER,
MX50_PAD_DISP_D2__FEC_RX_DV,
MX50_PAD_DISP_D3__FEC_RXD1,
MX50_PAD_DISP_D4__FEC_RXD0,
MX50_PAD_DISP_D5__FEC_TX_EN,
MX50_PAD_DISP_D6__FEC_TXD1,
MX50_PAD_DISP_D7__FEC_TXD0,
MX50_PAD_SSI_RXFS__FEC_MDC,
MX50_PAD_I2C3_SDA__GPIO_6_23,
MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
MX50_PAD_CSPI_SS0__CSPI_SS0,
MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
MX50_PAD_CSPI_MOSI__CSPI_MOSI,
MX50_PAD_CSPI_MISO__CSPI_MISO,
/* SGTL500_OSC_EN */
MX50_PAD_UART1_CTS__GPIO_6_8,
/* SGTL_AMP_SHDN */
MX50_PAD_UART3_RXD__GPIO_6_15,
/* Keypad */
MX50_PAD_KEY_COL0__KEY_COL0,
MX50_PAD_KEY_ROW0__KEY_ROW0,
MX50_PAD_KEY_COL1__KEY_COL1,
MX50_PAD_KEY_ROW1__KEY_ROW1,
MX50_PAD_KEY_COL2__KEY_COL2,
MX50_PAD_KEY_ROW2__KEY_ROW2,
MX50_PAD_KEY_COL3__KEY_COL3,
MX50_PAD_KEY_ROW3__KEY_ROW3,
MX50_PAD_EIM_DA0__KEY_COL4,
MX50_PAD_EIM_DA1__KEY_ROW4,
MX50_PAD_EIM_DA2__KEY_COL5,
MX50_PAD_EIM_DA3__KEY_ROW5,
MX50_PAD_EIM_DA4__KEY_COL6,
MX50_PAD_EIM_DA5__KEY_ROW6,
MX50_PAD_EIM_DA6__KEY_COL7,
MX50_PAD_EIM_DA7__KEY_ROW7,
/*EIM pads */
MX50_PAD_EIM_DA8__GPIO_1_8,
MX50_PAD_EIM_DA9__GPIO_1_9,
MX50_PAD_EIM_DA10__GPIO_1_10,
MX50_PAD_EIM_DA11__GPIO_1_11,
MX50_PAD_EIM_DA12__GPIO_1_12,
MX50_PAD_EIM_DA13__GPIO_1_13,
MX50_PAD_EIM_DA14__GPIO_1_14,
MX50_PAD_EIM_DA15__GPIO_1_15,
MX50_PAD_EIM_CS2__GPIO_1_16,
MX50_PAD_EIM_CS1__GPIO_1_17,
MX50_PAD_EIM_CS0__GPIO_1_18,
MX50_PAD_EIM_EB0__GPIO_1_19,
MX50_PAD_EIM_EB1__GPIO_1_20,
MX50_PAD_EIM_WAIT__GPIO_1_21,
MX50_PAD_EIM_BCLK__GPIO_1_22,
MX50_PAD_EIM_RDY__GPIO_1_23,
MX50_PAD_EIM_OE__GPIO_1_24,
};
/* Serial ports */
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
/*
* Board specific initialization.
*/
static void __init mx50_rdp_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
ARRAY_SIZE(mx50_rdp_pads));
imx50_add_imx_uart(0, &uart_pdata);
imx50_add_imx_uart(1, &uart_pdata);
}
static void __init mx50_rdp_timer_init(void)
{
mx50_clocks_init(32768, 24000000, 22579200);
}
static struct sys_timer mx50_rdp_timer = {
.init = mx50_rdp_timer_init,
};
MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
.map_io = mx50_map_io,
.init_irq = mx50_init_irq,
.init_machine = mx50_rdp_board_init,
.timer = &mx50_rdp_timer,
MACHINE_END

9
arch/arm/mach-mx5/board-mx51_3ds.c
View File

@ -30,7 +30,7 @@
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
static struct pad_desc mx51_3ds_pads[] = {
static iomux_v3_cfg_t mx51_3ds_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
@ -50,7 +50,7 @@ static struct pad_desc mx51_3ds_pads[] = {
MX51_PAD_EIM_D27__UART3_RTS,
/* CPLD PARENT IRQ PIN */
MX51_PAD_GPIO_1_6__GPIO_1_6,
MX51_PAD_GPIO1_6__GPIO1_6,
/* KPP */
MX51_PAD_KEY_ROW0__KEY_ROW0,
@ -68,7 +68,7 @@ static struct pad_desc mx51_3ds_pads[] = {
MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
MX51_PAD_NANDF_RB3__ECSPI2_MISO,
MX51_PAD_NANDF_D15__ECSPI2_MOSI,
MX51_PAD_NANDF_D12__GPIO_3_28,
MX51_PAD_NANDF_D12__GPIO3_28,
};
/* Serial ports */
@ -172,6 +172,7 @@ static void __init mxc_board_init(void)
printk(KERN_WARNING "Init of the debugboard failed, all "
"devices on the board are unusable.\n");
imx51_add_sdhci_esdhc_imx(0, NULL);
mxc_init_keypad();
}
@ -186,7 +187,7 @@ static struct sys_timer mxc_timer = {
MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
/* Maintainer: Freescale Semiconductor, Inc. */
.boot_params = PHYS_OFFSET + 0x100,
.boot_params = MX51_PHYS_OFFSET + 0x100,
.map_io = mx51_map_io,
.init_irq = mx51_init_irq,
.init_machine = mxc_board_init,

101
arch/arm/mach-mx5/board-mx51_babbage.c
View File

@ -20,6 +20,8 @@
#include <linux/fec.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/hardware.h>
@ -36,11 +38,13 @@
#include "devices.h"
#include "cpu_op-mx51.h"
#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */
#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5)
#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
@ -65,7 +69,7 @@ static const struct gpio_keys_platform_data imx_button_data __initconst = {
.nbuttons = ARRAY_SIZE(babbage_buttons),
};
static struct pad_desc mx51babbage_pads[] = {
static iomux_v3_cfg_t mx51babbage_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
@ -91,8 +95,8 @@ static struct pad_desc mx51babbage_pads[] = {
MX51_PAD_KEY_COL5__I2C2_SDA,
/* HSI2C */
MX51_PAD_I2C1_CLK__HSI2C_CLK,
MX51_PAD_I2C1_DAT__HSI2C_DAT,
MX51_PAD_I2C1_CLK__I2C1_CLK,
MX51_PAD_I2C1_DAT__I2C1_DAT,
/* USB HOST1 */
MX51_PAD_USBH1_CLK__USBH1_CLK,
@ -108,29 +112,29 @@ static struct pad_desc mx51babbage_pads[] = {
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
/* USB HUB reset line*/
MX51_PAD_GPIO_1_7__GPIO_1_7,
MX51_PAD_GPIO1_7__GPIO1_7,
/* FEC */
MX51_PAD_EIM_EB2__FEC_MDIO,
MX51_PAD_EIM_EB3__FEC_RDAT1,
MX51_PAD_EIM_CS2__FEC_RDAT2,
MX51_PAD_EIM_CS3__FEC_RDAT3,
MX51_PAD_EIM_EB3__FEC_RDATA1,
MX51_PAD_EIM_CS2__FEC_RDATA2,
MX51_PAD_EIM_CS3__FEC_RDATA3,
MX51_PAD_EIM_CS4__FEC_RX_ER,
MX51_PAD_EIM_CS5__FEC_CRS,
MX51_PAD_NANDF_RB2__FEC_COL,
MX51_PAD_NANDF_RB3__FEC_RXCLK,
MX51_PAD_NANDF_RB6__FEC_RDAT0,
MX51_PAD_NANDF_RB7__FEC_TDAT0,
MX51_PAD_NANDF_RB3__FEC_RX_CLK,
MX51_PAD_NANDF_D9__FEC_RDATA0,
MX51_PAD_NANDF_D8__FEC_TDATA0,
MX51_PAD_NANDF_CS2__FEC_TX_ER,
MX51_PAD_NANDF_CS3__FEC_MDC,
MX51_PAD_NANDF_CS4__FEC_TDAT1,
MX51_PAD_NANDF_CS5__FEC_TDAT2,
MX51_PAD_NANDF_CS6__FEC_TDAT3,
MX51_PAD_NANDF_CS4__FEC_TDATA1,
MX51_PAD_NANDF_CS5__FEC_TDATA2,
MX51_PAD_NANDF_CS6__FEC_TDATA3,
MX51_PAD_NANDF_CS7__FEC_TX_EN,
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
/* FEC PHY reset line */
MX51_PAD_EIM_A20__GPIO_2_14,
MX51_PAD_EIM_A20__GPIO2_14,
/* SD 1 */
MX51_PAD_SD1_CMD__SD1_CMD,
@ -147,6 +151,13 @@ static struct pad_desc mx51babbage_pads[] = {
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
/* eCSPI1 */
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
MX51_PAD_CSPI1_SS0__GPIO4_24,
MX51_PAD_CSPI1_SS1__GPIO4_25,
};
/* Serial ports */
@ -177,12 +188,12 @@ static struct imxi2c_platform_data babbage_hsi2c_data = {
static int gpio_usbh1_active(void)
{
struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
int ret;
/* Set USBH1_STP to GPIO and toggle it */
mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
mxc_iomux_v3_setup_pad(usbh1stp_gpio);
ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
if (ret) {
@ -195,7 +206,7 @@ static int gpio_usbh1_active(void)
gpio_free(BABBAGE_USBH1_STP);
/* De-assert USB PHY RESETB */
mxc_iomux_v3_setup_pad(&phyreset_gpio);
mxc_iomux_v3_setup_pad(phyreset_gpio);
ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
if (ret) {
@ -251,6 +262,8 @@ static int initialize_otg_port(struct platform_device *pdev)
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* Set the PHY clock to 19.2MHz */
@ -269,6 +282,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* The clock for the USBH1 ULPI port will come externally from the PHY. */
@ -310,13 +325,35 @@ static int __init babbage_otg_mode(char *options)
}
__setup("otg_mode=", babbage_otg_mode);
static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
{
.modalias = "mtd_dataflash",
.max_speed_hz = 25000000,
.bus_num = 0,
.chip_select = 1,
.mode = SPI_MODE_0,
.platform_data = NULL,
},
};
static int mx51_babbage_spi_cs[] = {
BABBAGE_ECSPI1_CS0,
BABBAGE_ECSPI1_CS1,
};
static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
.chipselect = mx51_babbage_spi_cs,
.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
};
/*
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
#if defined(CONFIG_CPU_FREQ_IMX)
get_cpu_op = mx51_get_cpu_op;
@ -328,8 +365,7 @@ static void __init mxc_board_init(void)
imx51_add_fec(NULL);
/* Set the PAD settings for the pwr key. */
power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
mxc_iomux_v3_setup_pad(&power_key);
mxc_iomux_v3_setup_pad(power_key);
imx51_add_gpio_keys(&imx_button_data);
imx51_add_imx_i2c(0, &babbage_i2c_data);
@ -346,11 +382,16 @@ static void __init mxc_board_init(void)
gpio_usbh1_active();
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
/* setback USBH1_STP to be function */
mxc_iomux_v3_setup_pad(&usbh1stp);
mxc_iomux_v3_setup_pad(usbh1stp);
babbage_usbhub_reset();
imx51_add_esdhc(0, NULL);
imx51_add_esdhc(1, NULL);
imx51_add_sdhci_esdhc_imx(0, NULL);
imx51_add_sdhci_esdhc_imx(1, NULL);
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
imx51_add_imx2_wdt(0, NULL);
}
static void __init mx51_babbage_timer_init(void)

247
arch/arm/mach-mx5/board-mx51_efikamx.c
View File

@ -18,9 +18,13 @@
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/hardware.h>
@ -39,12 +43,81 @@
#define MX51_USB_PLL_DIV_24_MHZ 0x01
static struct pad_desc mx51efikamx_pads[] = {
#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
/* board 1.1 doesn't have same reset gpio */
#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
/* the pci ids pin have pull up. they're driven low according to board id */
#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
static iomux_v3_cfg_t mx51efikamx_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
MX51_PAD_UART1_RTS__UART1_RTS,
MX51_PAD_UART1_CTS__UART1_CTS,
/* board id */
MX51_PAD_PCBID0,
MX51_PAD_PCBID1,
MX51_PAD_PCBID2,
/* SD 1 */
MX51_PAD_SD1_CMD__SD1_CMD,
MX51_PAD_SD1_CLK__SD1_CLK,
MX51_PAD_SD1_DATA0__SD1_DATA0,
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
/* SD 2 */
MX51_PAD_SD2_CMD__SD2_CMD,
MX51_PAD_SD2_CLK__SD2_CLK,
MX51_PAD_SD2_DATA0__SD2_DATA0,
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
/* SD/MMC WP/CD */
MX51_PAD_GPIO1_0__SD1_CD,
MX51_PAD_GPIO1_1__SD1_WP,
MX51_PAD_GPIO1_7__SD2_WP,
MX51_PAD_GPIO1_8__SD2_CD,
/* leds */
MX51_PAD_CSI1_D9__GPIO3_13,
MX51_PAD_CSI1_VSYNC__GPIO3_14,
MX51_PAD_CSI1_HSYNC__GPIO3_15,
/* power key */
MX51_PAD_PWRKEY,
/* spi */
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
MX51_PAD_CSPI1_SS0__GPIO4_24,
MX51_PAD_CSPI1_SS1__GPIO4_25,
MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
/* reset */
MX51_PAD_DI1_PIN13__GPIO3_2,
MX51_PAD_GPIO1_4__GPIO1_4,
};
/* Serial ports */
@ -75,6 +148,8 @@ static int initialize_otg_port(struct platform_device *pdev)
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
/* Set the PHY clock to 19.2MHz */
@ -92,12 +167,182 @@ static struct mxc_usbh_platform_data dr_utmi_config = {
.flags = MXC_EHCI_INTERNAL_PHY,
};
/* PCBID2 PCBID1 PCBID0 STATE
1 1 1 ER1:rev1.1
1 1 0 ER2:rev1.2
1 0 1 ER3:rev1.3
1 0 0 ER4:rev1.4
*/
static void __init mx51_efikamx_board_id(void)
{
int id;
/* things are taking time to settle */
msleep(150);
gpio_request(EFIKAMX_PCBID0, "pcbid0");
gpio_direction_input(EFIKAMX_PCBID0);
gpio_request(EFIKAMX_PCBID1, "pcbid1");
gpio_direction_input(EFIKAMX_PCBID1);
gpio_request(EFIKAMX_PCBID2, "pcbid2");
gpio_direction_input(EFIKAMX_PCBID2);
id = gpio_get_value(EFIKAMX_PCBID0);
id |= gpio_get_value(EFIKAMX_PCBID1) << 1;
id |= gpio_get_value(EFIKAMX_PCBID2) << 2;
switch (id) {
case 7:
system_rev = 0x11;
break;
case 6:
system_rev = 0x12;
break;
case 5:
system_rev = 0x13;
break;
case 4:
system_rev = 0x14;
break;
default:
system_rev = 0x10;
break;
}
if ((system_rev == 0x10)
|| (system_rev == 0x12)
|| (system_rev == 0x14)) {
printk(KERN_WARNING
"EfikaMX: Unsupported board revision 1.%u!\n",
system_rev & 0xf);
}
}
static struct gpio_led mx51_efikamx_leds[] = {
{
.name = "efikamx:green",
.default_trigger = "default-on",
.gpio = EFIKAMX_GREEN_LED,
},
{
.name = "efikamx:red",
.default_trigger = "ide-disk",
.gpio = EFIKAMX_RED_LED,
},
{
.name = "efikamx:blue",
.default_trigger = "mmc0",
.gpio = EFIKAMX_BLUE_LED,
},
};
static struct gpio_led_platform_data mx51_efikamx_leds_data = {
.leds = mx51_efikamx_leds,
.num_leds = ARRAY_SIZE(mx51_efikamx_leds),
};
static struct platform_device mx51_efikamx_leds_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &mx51_efikamx_leds_data,
},
};
static struct gpio_keys_button mx51_efikamx_powerkey[] = {
{
.code = KEY_POWER,
.gpio = EFIKAMX_POWER_KEY,
.type = EV_PWR,
.desc = "Power Button (CM)",
.wakeup = 1,
.debounce_interval = 10, /* ms */
},
};
static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
.buttons = mx51_efikamx_powerkey,
.nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
};
static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
{
.name = "u-boot",
.offset = 0,
.size = SZ_256K,
},
{
.name = "config",
.offset = MTDPART_OFS_APPEND,
.size = SZ_64K,
},
};
static struct flash_platform_data mx51_efikamx_spi_flash_data = {
.name = "spi_flash",
.parts = mx51_efikamx_spi_nor_partitions,
.nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
.type = "sst25vf032b",
};
static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
{
.modalias = "m25p80",
.max_speed_hz = 25000000,
.bus_num = 0,
.chip_select = 1,
.platform_data = &mx51_efikamx_spi_flash_data,
.irq = -1,
},
};
static int mx51_efikamx_spi_cs[] = {
EFIKAMX_SPI_CS0,
EFIKAMX_SPI_CS1,
};
static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
.chipselect = mx51_efikamx_spi_cs,
.num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
};
void mx51_efikamx_reset(void)
{
if (system_rev == 0x11)
gpio_direction_output(EFIKAMX_RESET1_1, 0);
else
gpio_direction_output(EFIKAMX_RESET, 0);
}
static void __init mxc_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
ARRAY_SIZE(mx51efikamx_pads));
mx51_efikamx_board_id();
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
mxc_init_imx_uart();
imx51_add_sdhci_esdhc_imx(0, NULL);
/* on < 1.2 boards both SD controllers are used */
if (system_rev < 0x12) {
imx51_add_sdhci_esdhc_imx(1, NULL);
mx51_efikamx_leds[2].default_trigger = "mmc1";
}
platform_device_register(&mx51_efikamx_leds_device);
imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
spi_register_board_info(mx51_efikamx_spi_board_info,
ARRAY_SIZE(mx51_efikamx_spi_board_info));
imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
if (system_rev == 0x11) {
gpio_request(EFIKAMX_RESET1_1, "reset");
gpio_direction_output(EFIKAMX_RESET1_1, 1);
} else {
gpio_request(EFIKAMX_RESET, "reset");
gpio_direction_output(EFIKAMX_RESET, 1);
}
}
static void __init mx51_efikamx_timer_init(void)

84
arch/arm/mach-mx5/board-mx53_evk.c Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#include "crm_regs.h"
#include "devices-imx53.h"
static iomux_v3_cfg_t mx53_evk_pads[] = {
MX53_PAD_CSI0_D10__UART1_TXD,
MX53_PAD_CSI0_D11__UART1_RXD,
MX53_PAD_ATA_DIOW__UART1_TXD,
MX53_PAD_ATA_DMACK__UART1_RXD,
MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
MX53_PAD_ATA_DMARQ__UART2_TXD,
MX53_PAD_ATA_DIOR__UART2_RTS,
MX53_PAD_ATA_INTRQ__UART2_CTS,
MX53_PAD_ATA_CS_0__UART3_TXD,
MX53_PAD_ATA_CS_1__UART3_RXD,
MX53_PAD_ATA_DA_1__UART3_CTS,
MX53_PAD_ATA_DA_2__UART3_RTS,
};
static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static inline void mx53_evk_init_uart(void)
{
imx53_add_imx_uart(0, &mx53_evk_uart_pdata);
imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
imx53_add_imx_uart(2, &mx53_evk_uart_pdata);
}
static void __init mx53_evk_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
ARRAY_SIZE(mx53_evk_pads));
mx53_evk_init_uart();
}
static void __init mx53_evk_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mx53_evk_timer = {
.init = mx53_evk_timer_init,
};
MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
.map_io = mx53_map_io,
.init_irq = mx53_init_irq,
.init_machine = mx53_evk_board_init,
.timer = &mx53_evk_timer,
MACHINE_END

296
arch/arm/mach-mx5/clock-mx51.c → arch/arm/mach-mx5/clock-mx51-mx53.c
View File

@ -33,11 +33,15 @@ static struct clk pll1_main_clk;
static struct clk pll1_sw_clk;
static struct clk pll2_sw_clk;
static struct clk pll3_sw_clk;
static struct clk mx53_pll4_sw_clk;
static struct clk lp_apm_clk;
static struct clk periph_apm_clk;
static struct clk ahb_clk;
static struct clk ipg_clk;
static struct clk usboh3_clk;
static struct clk emi_fast_clk;
static struct clk ipu_clk;
static struct clk mipi_hsc1_clk;
#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
@ -123,7 +127,7 @@ static inline u32 _get_mux(struct clk *parent, struct clk *m0,
return -EINVAL;
}
static inline void __iomem *_get_pll_base(struct clk *pll)
static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
{
if (pll == &pll1_main_clk)
return MX51_DPLL1_BASE;
@ -137,6 +141,30 @@ static inline void __iomem *_get_pll_base(struct clk *pll)
return NULL;
}
static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
{
if (pll == &pll1_main_clk)
return MX53_DPLL1_BASE;
else if (pll == &pll2_sw_clk)
return MX53_DPLL2_BASE;
else if (pll == &pll3_sw_clk)
return MX53_DPLL3_BASE;
else if (pll == &mx53_pll4_sw_clk)
return MX53_DPLL4_BASE;
else
BUG();
return NULL;
}
static inline void __iomem *_get_pll_base(struct clk *pll)
{
if (cpu_is_mx51())
return _mx51_get_pll_base(pll);
else
return _mx53_get_pll_base(pll);
}
static unsigned long clk_pll_get_rate(struct clk *clk)
{
long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
@ -514,7 +542,10 @@ static int _clk_max_enable(struct clk *clk)
/* Handshake with MAX when LPM is entered. */
reg = __raw_readl(MXC_CCM_CLPCR);
reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
if (cpu_is_mx51())
reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
else if (cpu_is_mx53())
reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
__raw_writel(reg, MXC_CCM_CLPCR);
return 0;
@ -528,7 +559,10 @@ static void _clk_max_disable(struct clk *clk)
/* No Handshake with MAX when LPM is entered as its disabled. */
reg = __raw_readl(MXC_CCM_CLPCR);
reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
if (cpu_is_mx51())
reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
else if (cpu_is_mx53())
reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
__raw_writel(reg, MXC_CCM_CLPCR);
}
@ -679,6 +713,19 @@ static unsigned long clk_emi_slow_get_rate(struct clk *clk)
return clk_get_rate(clk->parent) / div;
}
static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
{
unsigned long rate;
u32 reg, div;
reg = __raw_readl(MXC_CCM_CBCDR);
div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
rate = clk_get_rate(clk->parent) / div;
return rate;
}
/* External high frequency clock */
static struct clk ckih_clk = {
.get_rate = get_high_reference_clock_rate,
@ -739,6 +786,14 @@ static struct clk pll3_sw_clk = {
.disable = _clk_pll_disable,
};
/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
static struct clk mx53_pll4_sw_clk = {
.parent = &osc_clk,
.set_rate = _clk_pll_set_rate,
.enable = _clk_pll_enable,
.disable = _clk_pll_disable,
};
/* Low-power Audio Playback Mode clock */
static struct clk lp_apm_clk = {
.parent = &osc_clk,
@ -763,6 +818,12 @@ static struct clk ahb_clk = {
.round_rate = _clk_ahb_round_rate,
};
static struct clk iim_clk = {
.parent = &ipg_clk,
.enable_reg = MXC_CCM_CCGR0,
.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
};
/* Main IP interface clock for access to registers */
static struct clk ipg_clk = {
.parent = &ahb_clk,
@ -810,6 +871,10 @@ static struct clk kpp_clk = {
.id = 0,
};
static struct clk dummy_clk = {
.id = 0,
};
static struct clk emi_slow_clk = {
.parent = &pll2_sw_clk,
.enable_reg = MXC_CCM_CCGR5,
@ -819,6 +884,109 @@ static struct clk emi_slow_clk = {
.get_rate = clk_emi_slow_get_rate,
};
static int clk_ipu_enable(struct clk *clk)
{
u32 reg;
_clk_ccgr_enable(clk);
/* Enable handshake with IPU when certain clock rates are changed */
reg = __raw_readl(MXC_CCM_CCDR);
reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
__raw_writel(reg, MXC_CCM_CCDR);
/* Enable handshake with IPU when LPM is entered */
reg = __raw_readl(MXC_CCM_CLPCR);
reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
__raw_writel(reg, MXC_CCM_CLPCR);
return 0;
}
static void clk_ipu_disable(struct clk *clk)
{
u32 reg;
_clk_ccgr_disable(clk);
/* Disable handshake with IPU whe dividers are changed */
reg = __raw_readl(MXC_CCM_CCDR);
reg |= MXC_CCM_CCDR_IPU_HS_MASK;
__raw_writel(reg, MXC_CCM_CCDR);
/* Disable handshake with IPU when LPM is entered */
reg = __raw_readl(MXC_CCM_CLPCR);
reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
__raw_writel(reg, MXC_CCM_CLPCR);
}
static struct clk ahbmux1_clk = {
.parent = &ahb_clk,
.secondary = &ahb_max_clk,
.enable_reg = MXC_CCM_CCGR0,
.enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
.enable = _clk_ccgr_enable,
.disable = _clk_ccgr_disable_inwait,
};
static struct clk ipu_sec_clk = {
.parent = &emi_fast_clk,
.secondary = &ahbmux1_clk,
};
static struct clk ddr_hf_clk = {
.parent = &pll1_sw_clk,
.get_rate = _clk_ddr_hf_get_rate,
};
static struct clk ddr_clk = {
.parent = &ddr_hf_clk,
};
/* clock definitions for MIPI HSC unit which has been removed
* from documentation, but not from hardware
*/
static int _clk_hsc_enable(struct clk *clk)
{
u32 reg;
_clk_ccgr_enable(clk);
/* Handshake with IPU when certain clock rates are changed. */
reg = __raw_readl(MXC_CCM_CCDR);
reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
__raw_writel(reg, MXC_CCM_CCDR);
reg = __raw_readl(MXC_CCM_CLPCR);
reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
__raw_writel(reg, MXC_CCM_CLPCR);
return 0;
}
static void _clk_hsc_disable(struct clk *clk)
{
u32 reg;
_clk_ccgr_disable(clk);
/* No handshake with HSC as its not enabled. */
reg = __raw_readl(MXC_CCM_CCDR);
reg |= MXC_CCM_CCDR_HSC_HS_MASK;
__raw_writel(reg, MXC_CCM_CCDR);
reg = __raw_readl(MXC_CCM_CLPCR);
reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
__raw_writel(reg, MXC_CCM_CLPCR);
}
static struct clk mipi_hsp_clk = {
.parent = &ipu_clk,
.enable_reg = MXC_CCM_CCGR4,
.enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
.enable = _clk_hsc_enable,
.disable = _clk_hsc_disable,
.secondary = &mipi_hsc1_clk,
};
#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
static struct clk name = { \
.id = i, \
@ -927,6 +1095,41 @@ static struct clk usboh3_clk = {
.parent = &pll2_sw_clk,
.get_rate = clk_usboh3_get_rate,
.set_parent = clk_usboh3_set_parent,
.enable = _clk_ccgr_enable,
.disable = _clk_ccgr_disable,
.enable_reg = MXC_CCM_CCGR2,
.enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
};
static struct clk usb_ahb_clk = {
.parent = &ipg_clk,
.enable = _clk_ccgr_enable,
.disable = _clk_ccgr_disable,
.enable_reg = MXC_CCM_CCGR2,
.enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
};
static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg;
reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
if (parent == &pll3_sw_clk)
reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
__raw_writel(reg, MXC_CCM_CSCMR1);
return 0;
}
static struct clk usb_phy1_clk = {
.parent = &pll3_sw_clk,
.set_parent = clk_usb_phy1_set_parent,
.enable = _clk_ccgr_enable,
.enable_reg = MXC_CCM_CCGR2,
.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
.disable = _clk_ccgr_disable,
};
/* eCSPI */
@ -1013,6 +1216,10 @@ DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
NULL, NULL, &ipg_clk, NULL);
DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
NULL, NULL, &ipg_clk, NULL);
DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
/* eCSPI */
DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
@ -1046,6 +1253,23 @@ DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
/* IPU */
DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
&ddr_clk, NULL);
DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
NULL, NULL, &pll3_sw_clk, NULL);
DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
NULL, NULL, &pll3_sw_clk, NULL);
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
@ -1053,7 +1277,7 @@ DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
.clk = &c, \
},
static struct clk_lookup lookups[] = {
static struct clk_lookup mx51_lookups[] = {
_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
@ -1063,15 +1287,19 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
_REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
_REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
_REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
_REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
_REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
_REGISTER_CLOCK(NULL, "ckih", ckih_clk)
_REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
@ -1082,6 +1310,22 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
_REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
_REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
_REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
_REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
};
static struct clk_lookup mx53_lookups[] = {
_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
};
static void clk_tree_init(void)
@ -1114,14 +1358,22 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
ckih2_reference = ckih2;
oscillator_reference = osc;
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
clkdev_add(&mx51_lookups[i]);
clk_tree_init();
clk_set_parent(&uart_root_clk, &pll3_sw_clk);
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
clk_enable(&iim_clk);
mx51_revision();
clk_disable(&iim_clk);
/* move usb_phy_clk to 24MHz */
clk_set_parent(&usb_phy1_clk, &osc_clk);
/* set the usboh3_clk parent to pll2_sw_clk */
clk_set_parent(&usboh3_clk, &pll2_sw_clk);
@ -1138,3 +1390,31 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
MX51_MXC_INT_GPT);
return 0;
}
int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2)
{
int i;
external_low_reference = ckil;
external_high_reference = ckih1;
ckih2_reference = ckih2;
oscillator_reference = osc;
for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
clkdev_add(&mx53_lookups[i]);
clk_tree_init();
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
clk_enable(&iim_clk);
mx53_revision();
clk_disable(&iim_clk);
/* System timer */
mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
MX53_INT_GPT);
return 0;
}

114
arch/arm/mach-mx5/cpu.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@ -20,37 +20,18 @@
static int cpu_silicon_rev = -1;
#define SI_REV 0x48
#define IIM_SREV 0x24
static void query_silicon_parameter(void)
static int get_mx51_srev(void)
{
void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
u32 rev;
void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
u32 rev = readl(iim_base + IIM_SREV) & 0xff;
if (!rom) {
cpu_silicon_rev = -EINVAL;
return;
}
rev = readl(rom + SI_REV);
switch (rev) {
case 0x1:
cpu_silicon_rev = MX51_CHIP_REV_1_0;
break;
case 0x2:
cpu_silicon_rev = MX51_CHIP_REV_1_1;
break;
case 0x10:
cpu_silicon_rev = MX51_CHIP_REV_2_0;
break;
case 0x20:
cpu_silicon_rev = MX51_CHIP_REV_3_0;
break;
default:
cpu_silicon_rev = 0;
}
iounmap(rom);
if (rev == 0x0)
return IMX_CHIP_REVISION_2_0;
else if (rev == 0x10)
return IMX_CHIP_REVISION_3_0;
return 0;
}
/*
@ -64,7 +45,7 @@ int mx51_revision(void)
return -EINVAL;
if (cpu_silicon_rev == -1)
query_silicon_parameter();
cpu_silicon_rev = get_mx51_srev();
return cpu_silicon_rev;
}
@ -79,7 +60,10 @@ EXPORT_SYMBOL(mx51_revision);
*/
static int __init mx51_neon_fixup(void)
{
if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
if (!cpu_is_mx51())
return 0;
if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
elf_hwcap &= ~HWCAP_NEON;
pr_info("Turning off NEON support, detected broken NEON implementation\n");
}
@ -89,29 +73,65 @@ static int __init mx51_neon_fixup(void)
late_initcall(mx51_neon_fixup);
#endif
static int get_mx53_srev(void)
{
void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
u32 rev = readl(iim_base + IIM_SREV) & 0xff;
if (rev == 0x0)
return IMX_CHIP_REVISION_1_0;
else if (rev == 0x10)
return IMX_CHIP_REVISION_2_0;
return 0;
}
/*
* Returns:
* the silicon revision of the cpu
* -EINVAL - not a mx53
*/
int mx53_revision(void)
{
if (!cpu_is_mx53())
return -EINVAL;
if (cpu_silicon_rev == -1)
cpu_silicon_rev = get_mx53_srev();
return cpu_silicon_rev;
}
EXPORT_SYMBOL(mx53_revision);
static int __init post_cpu_init(void)
{
unsigned int reg;
void __iomem *base;
if (!cpu_is_mx51())
return 0;
if (cpu_is_mx51() || cpu_is_mx53()) {
if (cpu_is_mx51())
base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
else
base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
if (cpu_is_mx51())
base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
else
base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
}
return 0;
}

10
arch/arm/mach-mx5/crm_regs.h
View File

@ -18,6 +18,13 @@
#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
/*MX53*/
#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
/* PLL Register Offsets */
#define MXC_PLL_DP_CTL 0x00
#define MXC_PLL_DP_CONFIG 0x04
@ -380,7 +387,8 @@
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)

11
arch/arm/mach-mx5/devices-imx51.h
View File

@ -31,6 +31,11 @@ extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
#define imx51_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx51_sdhci_esdhc_imx_data[] __initconst;
#define imx51_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
#define imx51_add_cspi(pdata) \
imx_add_spi_imx(&imx51_cspi_data, pdata)
@ -39,6 +44,6 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
#define imx51_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst;
#define imx51_add_esdhc(id, pdata) \
imx_add_esdhc(&imx51_esdhc_data[id], pdata)
extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst;
#define imx51_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])

13
arch/arm/mach-mx5/devices-imx53.h Normal file
View File

@ -0,0 +1,13 @@
/*
* Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx53.h>
#include <mach/devices-common.h>
extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst;
#define imx53_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)

26
arch/arm/mach-mx5/devices-mx50.h Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <mach/mx50.h>
#include <mach/devices-common.h>
extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
#define imx50_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)

51
arch/arm/mach-mx5/devices.c
View File

@ -97,19 +97,27 @@ struct platform_device mxc_usbh1_device = {
},
};
static struct resource mxc_wdt_resources[] = {
static struct resource usbh2_resources[] = {
{
.start = MX51_WDOG_BASE_ADDR,
.end = MX51_WDOG_BASE_ADDR + SZ_16K - 1,
.start = MX51_OTG_BASE_ADDR + 0x400,
.end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff,
.flags = IORESOURCE_MEM,
},
{
.start = MX51_MXC_INT_USB_H2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_wdt = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdt_resources),
.resource = mxc_wdt_resources,
struct platform_device mxc_usbh2_device = {
.name = "mxc-ehci",
.id = 2,
.num_resources = ARRAY_SIZE(usbh2_resources),
.resource = usbh2_resources,
.dev = {
.dma_mask = &usb_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource mxc_kpp_resources[] = {
@ -160,9 +168,36 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
.irq_high = MX51_MXC_INT_GPIO4_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
},
{
.chip.label = "gpio-4",
.base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR),
.irq = MX53_INT_GPIO5_LOW,
.irq_high = MX53_INT_GPIO5_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4
},
{
.chip.label = "gpio-5",
.base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR),
.irq = MX53_INT_GPIO6_LOW,
.irq_high = MX53_INT_GPIO6_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5
},
{
.chip.label = "gpio-6",
.base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR),
.irq = MX53_INT_GPIO7_LOW,
.irq_high = MX53_INT_GPIO7_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6
},
};
int __init imx51_register_gpios(void)
{
return mxc_gpio_init(mxc_gpio_ports, 4);
}
int __init imx53_register_gpios(void)
{
return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
}

2
arch/arm/mach-mx5/devices.h
View File

@ -1,6 +1,6 @@
extern struct platform_device mxc_usbdr_host_device;
extern struct platform_device mxc_usbh1_device;
extern struct platform_device mxc_usbh2_device;
extern struct platform_device mxc_usbdr_udc_device;
extern struct platform_device mxc_wdt;
extern struct platform_device mxc_hsi2c_device;
extern struct platform_device mxc_keypad_device;

26
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View File

@ -33,12 +33,12 @@
#include "devices-imx51.h"
#include "devices.h"
#define MBIMX51_TSC2007_GPIO (2*32 + 30)
#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30)
#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
#define MBIMX51_LED0 (2*32 + 5)
#define MBIMX51_LED1 (2*32 + 6)
#define MBIMX51_LED2 (2*32 + 7)
#define MBIMX51_LED3 (2*32 + 8)
#define MBIMX51_LED0 IMX_GPIO_NR(3, 5)
#define MBIMX51_LED1 IMX_GPIO_NR(3, 6)
#define MBIMX51_LED2 IMX_GPIO_NR(3, 7)
#define MBIMX51_LED3 IMX_GPIO_NR(3, 8)
static struct gpio_led mbimx51_leds[] = {
{
@ -84,7 +84,7 @@ static struct platform_device *devices[] __initdata = {
&mbimx51_leds_gpio,
};
static struct pad_desc mbimx51_pads[] = {
static iomux_v3_cfg_t mbimx51_pads[] = {
/* UART2 */
MX51_PAD_UART2_RXD__UART2_RXD,
MX51_PAD_UART2_TXD__UART2_TXD,
@ -96,13 +96,13 @@ static struct pad_desc mbimx51_pads[] = {
MX51_PAD_KEY_COL5__UART3_CTS,
/* TSC2007 IRQ */
MX51_PAD_NANDF_D10__GPIO_3_30,
MX51_PAD_NANDF_D10__GPIO3_30,
/* LEDS */
MX51_PAD_DISPB2_SER_DIN__GPIO_3_5,
MX51_PAD_DISPB2_SER_DIO__GPIO_3_6,
MX51_PAD_DISPB2_SER_CLK__GPIO_3_7,
MX51_PAD_DISPB2_SER_RS__GPIO_3_8,
MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
MX51_PAD_DISPB2_SER_RS__GPIO3_8,
/* KPP */
MX51_PAD_KEY_ROW0__KEY_ROW0,
@ -217,6 +217,6 @@ void __init eukrea_mbimx51_baseboard_init(void)
i2c_register_board_info(1, mbimx51_i2c_devices,
ARRAY_SIZE(mbimx51_i2c_devices));
imx51_add_esdhc(0, NULL);
imx51_add_esdhc(1, NULL);
imx51_add_sdhci_esdhc_imx(0, NULL);
imx51_add_sdhci_esdhc_imx(1, NULL);
}

17
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
View File

@ -45,14 +45,13 @@
#include "devices-imx51.h"
#include "devices.h"
#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \
MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
static struct pad_desc eukrea_mbimxsd_pads[] = {
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LED */
MX51_PAD_NANDF_D10__GPIO_3_30,
MX51_PAD_NANDF_D10__GPIO3_30,
/* SWITCH */
MBIMXSD_GPIO_3_31,
_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
/* UART2 */
MX51_PAD_UART2_RXD__UART2_RXD,
MX51_PAD_UART2_TXD__UART2_TXD,
@ -70,8 +69,8 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
MX51_PAD_SD1_DATA3__SD1_DATA3,
};
#define GPIO_LED1 (2 * 32 + 30)
#define GPIO_SWITCH1 (2 * 32 + 31)
#define GPIO_LED1 IMX_GPIO_NR(3, 30)
#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
static struct gpio_led eukrea_mbimxsd_leds[] = {
{
@ -149,7 +148,7 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
imx51_add_imx_uart(1, NULL);
imx51_add_imx_uart(2, &uart_pdata);
imx51_add_esdhc(0, NULL);
imx51_add_sdhci_esdhc_imx(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);

59
arch/arm/mach-mx5/mm-mx50.c Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Create static mapping between physical to virtual memory.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-v3.h>
/*
* Define the MX50 memory map.
*/
static struct map_desc mx50_io_desc[] __initdata = {
imx_map_entry(MX50, TZIC, MT_DEVICE),
imx_map_entry(MX50, SPBA0, MT_DEVICE),
imx_map_entry(MX50, AIPS1, MT_DEVICE),
imx_map_entry(MX50, AIPS2, MT_DEVICE),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx50_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX50);
mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
}
int imx50_register_gpios(void);
void __init mx50_init_irq(void)
{
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
imx50_register_gpios();
}

75
arch/arm/mach-mx5/mm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@ -23,33 +23,21 @@
/*
* Define the MX51 memory map.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MX51_IRAM_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),
.length = MX51_IRAM_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_DEBUG_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
.length = MX51_DEBUG_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
.length = MX51_AIPS1_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
.length = MX51_SPBA0_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
.length = MX51_AIPS2_SIZE,
.type = MT_DEVICE
},
static struct map_desc mx51_io_desc[] __initdata = {
imx_map_entry(MX51, IRAM, MT_DEVICE),
imx_map_entry(MX51, DEBUG, MT_DEVICE),
imx_map_entry(MX51, AIPS1, MT_DEVICE),
imx_map_entry(MX51, SPBA0, MT_DEVICE),
imx_map_entry(MX51, AIPS2, MT_DEVICE),
};
/*
* Define the MX53 memory map.
*/
static struct map_desc mx53_io_desc[] __initdata = {
imx_map_entry(MX53, AIPS1, MT_DEVICE),
imx_map_entry(MX53, SPBA0, MT_DEVICE),
imx_map_entry(MX53, AIPS2, MT_DEVICE),
};
/*
@ -61,8 +49,16 @@ void __init mx51_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX51);
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
}
void __init mx53_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX53);
mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR));
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
}
int imx51_register_gpios(void);
@ -72,7 +68,7 @@ void __init mx51_init_irq(void)
unsigned long tzic_addr;
void __iomem *tzic_virt;
if (mx51_revision() < MX51_CHIP_REV_2_0)
if (mx51_revision() < IMX_CHIP_REVISION_2_0)
tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
else
tzic_addr = MX51_TZIC_BASE_ADDR;
@ -84,3 +80,20 @@ void __init mx51_init_irq(void)
tzic_init_irq(tzic_virt);
imx51_register_gpios();
}
int imx53_register_gpios(void);
void __init mx53_init_irq(void)
{
unsigned long tzic_addr;
void __iomem *tzic_virt;
tzic_addr = MX53_TZIC_BASE_ADDR;
tzic_virt = ioremap(tzic_addr, SZ_16K);
if (!tzic_virt)
panic("unable to map TZIC interrupt controller\n");
tzic_init_irq(tzic_virt);
imx53_register_gpios();
}

53
arch/arm/mach-mxc91231/mm.c
View File

@ -27,48 +27,15 @@
/*
* This structure defines the MXC memory map.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MXC91231_L2CC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
.length = MXC91231_L2CC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
.length = MXC91231_X_MEMC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_ROMP_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
.length = MXC91231_ROMP_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
.length = MXC91231_AVIC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
.length = MXC91231_AIPS1_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
.length = MXC91231_SPBA0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_SPBA1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
.length = MXC91231_SPBA1_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
.length = MXC91231_AIPS2_SIZE,
.type = MT_DEVICE,
},
static struct map_desc mxc91231_io_desc[] __initdata = {
imx_map_entry(MXC91231, L2CC, MT_DEVICE),
imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
imx_map_entry(MXC91231, ROMP, MT_DEVICE),
imx_map_entry(MXC91231, AVIC, MT_DEVICE),
imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
};
/*
@ -80,7 +47,7 @@ void __init mxc91231_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MXC91231);
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
}
int mxc91231_register_gpios(void);

34
arch/arm/mach-mxs/Kconfig Normal file
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@ -0,0 +1,34 @@
if ARCH_MXS
source "arch/arm/mach-mxs/devices/Kconfig"
config SOC_IMX23
bool
select CPU_ARM926T
config SOC_IMX28
bool
select CPU_ARM926T
comment "MXS platforms:"
config MACH_MX23EVK
bool "Support MX23EVK Platform"
select SOC_IMX23
select MXS_HAVE_PLATFORM_DUART
default y
help
Include support for MX23EVK platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX28EVK
bool "Support MX28EVK Platform"
select SOC_IMX28
select MXS_HAVE_PLATFORM_DUART
select MXS_HAVE_PLATFORM_FEC
default y
help
Include support for MX28EVK platform. This includes specific
configurations for the board and its peripherals.
endif

10
arch/arm/mach-mxs/Makefile Normal file
View File

@ -0,0 +1,10 @@
# Common support
obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
obj-y += devices/

1
arch/arm/mach-mxs/Makefile.boot Normal file
View File

@ -0,0 +1 @@
zreladdr-y := 0x40008000

526
arch/arm/mach-mxs/clock-mx23.c Normal file
View File

@ -0,0 +1,526 @@
/*
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <asm/clkdev.h>
#include <asm/div64.h>
#include <mach/mx23.h>
#include <mach/common.h>
#include <mach/clock.h>
#include "regs-clkctrl-mx23.h"
#define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
#define DIGCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
#define PARENT_RATE_SHIFT 8
static int _raw_clk_enable(struct clk *clk)
{
u32 reg;
if (clk->enable_reg) {
reg = __raw_readl(clk->enable_reg);
reg &= ~(1 << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
return 0;
}
static void _raw_clk_disable(struct clk *clk)
{
u32 reg;
if (clk->enable_reg) {
reg = __raw_readl(clk->enable_reg);
reg |= 1 << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
}
}
/*
* ref_xtal_clk
*/
static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
{
return 24000000;
}
static struct clk ref_xtal_clk = {
.get_rate = ref_xtal_clk_get_rate,
};
/*
* pll_clk
*/
static unsigned long pll_clk_get_rate(struct clk *clk)
{
return 480000000;
}
static int pll_clk_enable(struct clk *clk)
{
__raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
/* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
* and is incorrect (excessive). Per definition of the PLLCTRL0
* POWER field, waiting at least 10us.
*/
udelay(10);
return 0;
}
static void pll_clk_disable(struct clk *clk)
{
__raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
}
static struct clk pll_clk = {
.get_rate = pll_clk_get_rate,
.enable = pll_clk_enable,
.disable = pll_clk_disable,
.parent = &ref_xtal_clk,
};
/*
* ref_clk
*/
#define _CLK_GET_RATE_REF(name, sr, ss) \
static unsigned long name##_get_rate(struct clk *clk) \
{ \
unsigned long parent_rate; \
u32 reg, div; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
parent_rate = clk_get_rate(clk->parent); \
\
return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
div, PARENT_RATE_SHIFT); \
}
_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
#define _DEFINE_CLOCK_REF(name, er, es) \
static struct clk name = { \
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
.enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
.get_rate = name##_get_rate, \
.enable = _raw_clk_enable, \
.disable = _raw_clk_disable, \
.parent = &pll_clk, \
}
_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
/*
* General clocks
*
* clk_get_rate
*/
static unsigned long rtc_clk_get_rate(struct clk *clk)
{
/* ref_xtal_clk is implemented as the only parent */
return clk_get_rate(clk->parent) / 768;
}
static unsigned long clk32k_clk_get_rate(struct clk *clk)
{
return clk->parent->get_rate(clk->parent) / 750;
}
#define _CLK_GET_RATE(name, rs) \
static unsigned long name##_get_rate(struct clk *clk) \
{ \
u32 reg, div; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
\
if (clk->parent == &ref_xtal_clk) \
div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
BP_CLKCTRL_##rs##_DIV_XTAL; \
else \
div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
BP_CLKCTRL_##rs##_DIV_##rs; \
\
if (!div) \
return -EINVAL; \
\
return clk_get_rate(clk->parent) / div; \
}
_CLK_GET_RATE(cpu_clk, CPU)
_CLK_GET_RATE(emi_clk, EMI)
#define _CLK_GET_RATE1(name, rs) \
static unsigned long name##_get_rate(struct clk *clk) \
{ \
u32 reg, div; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
\
if (!div) \
return -EINVAL; \
\
return clk_get_rate(clk->parent) / div; \
}
_CLK_GET_RATE1(hbus_clk, HBUS)
_CLK_GET_RATE1(xbus_clk, XBUS)
_CLK_GET_RATE1(ssp_clk, SSP)
_CLK_GET_RATE1(gpmi_clk, GPMI)
_CLK_GET_RATE1(lcdif_clk, PIX)
#define _CLK_GET_RATE_STUB(name) \
static unsigned long name##_get_rate(struct clk *clk) \
{ \
return clk_get_rate(clk->parent); \
}
_CLK_GET_RATE_STUB(uart_clk)
_CLK_GET_RATE_STUB(audio_clk)
_CLK_GET_RATE_STUB(pwm_clk)
/*
* clk_set_rate
*/
static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg, bm_busy, div_max, d, f, div, frac;
unsigned long diff, parent_rate, calc_rate;
int i;
parent_rate = clk_get_rate(clk->parent);
if (clk->parent == &ref_xtal_clk) {
div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
div = DIV_ROUND_UP(parent_rate, rate);
if (div == 0 || div > div_max)
return -EINVAL;
} else {
div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
rate >>= PARENT_RATE_SHIFT;
parent_rate >>= PARENT_RATE_SHIFT;
diff = parent_rate;
div = frac = 1;
for (d = 1; d <= div_max; d++) {
f = parent_rate * 18 / d / rate;
if ((parent_rate * 18 / d) % rate)
f++;
if (f < 18 || f > 35)
continue;
calc_rate = parent_rate * 18 / f / d;
if (calc_rate > rate)
continue;
if (rate - calc_rate < diff) {
frac = f;
div = d;
diff = rate - calc_rate;
}
if (diff == 0)
break;
}
if (diff == parent_rate)
return -EINVAL;
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
reg |= frac;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
}
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
for (i = 10000; i; i--)
if (!(__raw_readl(CLKCTRL_BASE_ADDR +
HW_CLKCTRL_CPU) & bm_busy))
break;
if (!i) {
pr_err("%s: divider writing timeout\n", __func__);
return -ETIMEDOUT;
}
return 0;
}
#define _CLK_SET_RATE(name, dr) \
static int name##_set_rate(struct clk *clk, unsigned long rate) \
{ \
u32 reg, div_max, div; \
unsigned long parent_rate; \
int i; \
\
parent_rate = clk_get_rate(clk->parent); \
div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
\
div = DIV_ROUND_UP(parent_rate, rate); \
if (div == 0 || div > div_max) \
return -EINVAL; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
reg &= ~BM_CLKCTRL_##dr##_DIV; \
reg |= div << BP_CLKCTRL_##dr##_DIV; \
if (reg | (1 << clk->enable_shift)) { \
pr_err("%s: clock is gated\n", __func__); \
return -EINVAL; \
} \
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
\
for (i = 10000; i; i--) \
if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
break; \
if (!i) { \
pr_err("%s: divider writing timeout\n", __func__); \
return -ETIMEDOUT; \
} \
\
return 0; \
}
_CLK_SET_RATE(xbus_clk, XBUS)
_CLK_SET_RATE(ssp_clk, SSP)
_CLK_SET_RATE(gpmi_clk, GPMI)
_CLK_SET_RATE(lcdif_clk, PIX)
#define _CLK_SET_RATE_STUB(name) \
static int name##_set_rate(struct clk *clk, unsigned long rate) \
{ \
return -EINVAL; \
}
_CLK_SET_RATE_STUB(emi_clk)
_CLK_SET_RATE_STUB(uart_clk)
_CLK_SET_RATE_STUB(audio_clk)
_CLK_SET_RATE_STUB(pwm_clk)
_CLK_SET_RATE_STUB(clk32k_clk)
/*
* clk_set_parent
*/
#define _CLK_SET_PARENT(name, bit) \
static int name##_set_parent(struct clk *clk, struct clk *parent) \
{ \
if (parent != clk->parent) { \
__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
HW_CLKCTRL_CLKSEQ_TOG); \
clk->parent = parent; \
} \
\
return 0; \
}
_CLK_SET_PARENT(cpu_clk, CPU)
_CLK_SET_PARENT(emi_clk, EMI)
_CLK_SET_PARENT(ssp_clk, SSP)
_CLK_SET_PARENT(gpmi_clk, GPMI)
_CLK_SET_PARENT(lcdif_clk, PIX)
#define _CLK_SET_PARENT_STUB(name) \
static int name##_set_parent(struct clk *clk, struct clk *parent) \
{ \
if (parent != clk->parent) \
return -EINVAL; \
else \
return 0; \
}
_CLK_SET_PARENT_STUB(uart_clk)
_CLK_SET_PARENT_STUB(audio_clk)
_CLK_SET_PARENT_STUB(pwm_clk)
_CLK_SET_PARENT_STUB(clk32k_clk)
/*
* clk definition
*/
static struct clk cpu_clk = {
.get_rate = cpu_clk_get_rate,
.set_rate = cpu_clk_set_rate,
.set_parent = cpu_clk_set_parent,
.parent = &ref_cpu_clk,
};
static struct clk hbus_clk = {
.get_rate = hbus_clk_get_rate,
.parent = &cpu_clk,
};
static struct clk xbus_clk = {
.get_rate = xbus_clk_get_rate,
.set_rate = xbus_clk_set_rate,
.parent = &ref_xtal_clk,
};
static struct clk rtc_clk = {
.get_rate = rtc_clk_get_rate,
.parent = &ref_xtal_clk,
};
/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
static struct clk usb_clk = {
.enable_reg = DIGCTRL_BASE_ADDR,
.enable_shift = 2,
.enable = _raw_clk_enable,
.disable = _raw_clk_disable,
.parent = &pll_clk,
};
#define _DEFINE_CLOCK(name, er, es, p) \
static struct clk name = { \
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
.enable_shift = BP_CLKCTRL_##er##_##es, \
.get_rate = name##_get_rate, \
.set_rate = name##_set_rate, \
.set_parent = name##_set_parent, \
.enable = _raw_clk_enable, \
.disable = _raw_clk_disable, \
.parent = p, \
}
_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = &c, \
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK(NULL, "hclk", hbus_clk)
_REGISTER_CLOCK(NULL, "xclk", xbus_clk)
_REGISTER_CLOCK(NULL, "usb", usb_clk)
_REGISTER_CLOCK(NULL, "audio", audio_clk)
_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
};
static int clk_misc_init(void)
{
u32 reg;
int i;
/* Fix up parent per register setting */
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
&ref_xtal_clk : &ref_cpu_clk;
emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
&ref_xtal_clk : &ref_emi_clk;
ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
&ref_xtal_clk : &ref_io_clk;
gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
&ref_xtal_clk : &ref_io_clk;
lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
&ref_xtal_clk : &ref_pix_clk;
/* Use int div over frac when both are available */
__raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
__raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
__raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
/*
* Set safe hbus clock divider. A divider of 3 ensure that
* the Vddd voltage required for the cpu clock is sufficiently
* high for the hbus clock.
*/
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
reg &= BM_CLKCTRL_HBUS_DIV;
reg |= 3 << BP_CLKCTRL_HBUS_DIV;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
for (i = 10000; i; i--)
if (!(__raw_readl(CLKCTRL_BASE_ADDR +
HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY))
break;
if (!i) {
pr_err("%s: divider writing timeout\n", __func__);
return -ETIMEDOUT;
}
/* Gate off cpu clock in WFI for power saving */
__raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
return 0;
}
int __init mx23_clocks_init(void)
{
clk_misc_init();
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
return 0;
}

734
arch/arm/mach-mxs/clock-mx28.c Normal file
View File

@ -0,0 +1,734 @@
/*
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <asm/clkdev.h>
#include <asm/div64.h>
#include <mach/mx28.h>
#include <mach/common.h>
#include <mach/clock.h>
#include "regs-clkctrl-mx28.h"
#define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
#define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
#define PARENT_RATE_SHIFT 8
static struct clk pll2_clk;
static struct clk cpu_clk;
static struct clk emi_clk;
static struct clk saif0_clk;
static struct clk saif1_clk;
static struct clk clk32k_clk;
static int _raw_clk_enable(struct clk *clk)
{
u32 reg;
if (clk->enable_reg) {
reg = __raw_readl(clk->enable_reg);
reg &= ~(1 << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
return 0;
}
static void _raw_clk_disable(struct clk *clk)
{
u32 reg;
if (clk->enable_reg) {
reg = __raw_readl(clk->enable_reg);
reg |= 1 << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
}
}
/*
* ref_xtal_clk
*/
static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
{
return 24000000;
}
static struct clk ref_xtal_clk = {
.get_rate = ref_xtal_clk_get_rate,
};
/*
* pll_clk
*/
static unsigned long pll0_clk_get_rate(struct clk *clk)
{
return 480000000;
}
static unsigned long pll1_clk_get_rate(struct clk *clk)
{
return 480000000;
}
static unsigned long pll2_clk_get_rate(struct clk *clk)
{
return 50000000;
}
#define _CLK_ENABLE_PLL(name, r, g) \
static int name##_enable(struct clk *clk) \
{ \
__raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
udelay(10); \
\
if (clk == &pll2_clk) \
__raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
else \
__raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
\
return 0; \
}
_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
#define _CLK_DISABLE_PLL(name, r, g) \
static void name##_disable(struct clk *clk) \
{ \
__raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
\
if (clk == &pll2_clk) \
__raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
else \
__raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
\
}
_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
#define _DEFINE_CLOCK_PLL(name) \
static struct clk name = { \
.get_rate = name##_get_rate, \
.enable = name##_enable, \
.disable = name##_disable, \
.parent = &ref_xtal_clk, \
}
_DEFINE_CLOCK_PLL(pll0_clk);
_DEFINE_CLOCK_PLL(pll1_clk);
_DEFINE_CLOCK_PLL(pll2_clk);
/*
* ref_clk
*/
#define _CLK_GET_RATE_REF(name, sr, ss) \
static unsigned long name##_get_rate(struct clk *clk) \
{ \
unsigned long parent_rate; \
u32 reg, div; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
parent_rate = clk_get_rate(clk->parent); \
\
return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
div, PARENT_RATE_SHIFT); \
}
_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
#define _DEFINE_CLOCK_REF(name, er, es) \
static struct clk name = { \
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
.enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
.get_rate = name##_get_rate, \
.enable = _raw_clk_enable, \
.disable = _raw_clk_disable, \
.parent = &pll0_clk, \
}
_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
/*
* General clocks
*
* clk_get_rate
*/
static unsigned long lradc_clk_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / 16;
}
static unsigned long rtc_clk_get_rate(struct clk *clk)
{
/* ref_xtal_clk is implemented as the only parent */
return clk_get_rate(clk->parent) / 768;
}
static unsigned long clk32k_clk_get_rate(struct clk *clk)
{
return clk->parent->get_rate(clk->parent) / 750;
}
static unsigned long spdif_clk_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / 4;
}
#define _CLK_GET_RATE(name, rs) \
static unsigned long name##_get_rate(struct clk *clk) \
{ \
u32 reg, div; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
\
if (clk->parent == &ref_xtal_clk) \
div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
BP_CLKCTRL_##rs##_DIV_XTAL; \
else \
div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
BP_CLKCTRL_##rs##_DIV_##rs; \
\
if (!div) \
return -EINVAL; \
\
return clk_get_rate(clk->parent) / div; \
}
_CLK_GET_RATE(cpu_clk, CPU)
_CLK_GET_RATE(emi_clk, EMI)
#define _CLK_GET_RATE1(name, rs) \
static unsigned long name##_get_rate(struct clk *clk) \
{ \
u32 reg, div; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
\
if (!div) \
return -EINVAL; \
\
if (clk == &saif0_clk || clk == &saif1_clk) \
return clk_get_rate(clk->parent) >> 16 * div; \
else \
return clk_get_rate(clk->parent) / div; \
}
_CLK_GET_RATE1(hbus_clk, HBUS)
_CLK_GET_RATE1(xbus_clk, XBUS)
_CLK_GET_RATE1(ssp0_clk, SSP0)
_CLK_GET_RATE1(ssp1_clk, SSP1)
_CLK_GET_RATE1(ssp2_clk, SSP2)
_CLK_GET_RATE1(ssp3_clk, SSP3)
_CLK_GET_RATE1(gpmi_clk, GPMI)
_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
_CLK_GET_RATE1(saif0_clk, SAIF0)
_CLK_GET_RATE1(saif1_clk, SAIF1)
#define _CLK_GET_RATE_STUB(name) \
static unsigned long name##_get_rate(struct clk *clk) \
{ \
return clk_get_rate(clk->parent); \
}
_CLK_GET_RATE_STUB(uart_clk)
_CLK_GET_RATE_STUB(pwm_clk)
_CLK_GET_RATE_STUB(can0_clk)
_CLK_GET_RATE_STUB(can1_clk)
_CLK_GET_RATE_STUB(fec_clk)
/*
* clk_set_rate
*/
/* fool compiler */
#define BM_CLKCTRL_CPU_DIV 0
#define BP_CLKCTRL_CPU_DIV 0
#define BM_CLKCTRL_CPU_BUSY 0
#define _CLK_SET_RATE(name, dr, fr, fs) \
static int name##_set_rate(struct clk *clk, unsigned long rate) \
{ \
u32 reg, bm_busy, div_max, d, f, div, frac; \
unsigned long diff, parent_rate, calc_rate; \
int i; \
\
parent_rate = clk_get_rate(clk->parent); \
div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
bm_busy = BM_CLKCTRL_##dr##_BUSY; \
\
if (clk->parent == &ref_xtal_clk) { \
div = DIV_ROUND_UP(parent_rate, rate); \
if (clk == &cpu_clk) { \
div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
BP_CLKCTRL_CPU_DIV_XTAL; \
bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \
} \
if (div == 0 || div > div_max) \
return -EINVAL; \
} else { \
rate >>= PARENT_RATE_SHIFT; \
parent_rate >>= PARENT_RATE_SHIFT; \
diff = parent_rate; \
div = frac = 1; \
if (clk == &cpu_clk) { \
div_max = BM_CLKCTRL_CPU_DIV_CPU >> \
BP_CLKCTRL_CPU_DIV_CPU; \
bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \
} \
for (d = 1; d <= div_max; d++) { \
f = parent_rate * 18 / d / rate; \
if ((parent_rate * 18 / d) % rate) \
f++; \
if (f < 18 || f > 35) \
continue; \
\
calc_rate = parent_rate * 18 / f / d; \
if (calc_rate > rate) \
continue; \
\
if (rate - calc_rate < diff) { \
frac = f; \
div = d; \
diff = rate - calc_rate; \
} \
\
if (diff == 0) \
break; \
} \
\
if (diff == parent_rate) \
return -EINVAL; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
reg |= frac; \
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
} \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
if (clk == &cpu_clk) { \
reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \
reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
} else { \
reg &= ~BM_CLKCTRL_##dr##_DIV; \
reg |= div << BP_CLKCTRL_##dr##_DIV; \
if (reg | (1 << clk->enable_shift)) { \
pr_err("%s: clock is gated\n", __func__); \
return -EINVAL; \
} \
} \
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); \
\
for (i = 10000; i; i--) \
if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
HW_CLKCTRL_##dr) & bm_busy)) \
break; \
if (!i) { \
pr_err("%s: divider writing timeout\n", __func__); \
return -ETIMEDOUT; \
} \
\
return 0; \
}
_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
#define _CLK_SET_RATE1(name, dr) \
static int name##_set_rate(struct clk *clk, unsigned long rate) \
{ \
u32 reg, div_max, div; \
unsigned long parent_rate; \
int i; \
\
parent_rate = clk_get_rate(clk->parent); \
div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
\
div = DIV_ROUND_UP(parent_rate, rate); \
if (div == 0 || div > div_max) \
return -EINVAL; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
reg &= ~BM_CLKCTRL_##dr##_DIV; \
reg |= div << BP_CLKCTRL_##dr##_DIV; \
if (reg | (1 << clk->enable_shift)) { \
pr_err("%s: clock is gated\n", __func__); \
return -EINVAL; \
} \
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
\
for (i = 10000; i; i--) \
if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
break; \
if (!i) { \
pr_err("%s: divider writing timeout\n", __func__); \
return -ETIMEDOUT; \
} \
\
return 0; \
}
_CLK_SET_RATE1(xbus_clk, XBUS)
/* saif clock uses 16 bits frac div */
#define _CLK_SET_RATE_SAIF(name, rs) \
static int name##_set_rate(struct clk *clk, unsigned long rate) \
{ \
u16 div; \
u32 reg; \
u64 lrate; \
unsigned long parent_rate; \
int i; \
\
parent_rate = clk_get_rate(clk->parent); \
if (rate > parent_rate) \
return -EINVAL; \
\
lrate = (u64)rate << 16; \
do_div(lrate, parent_rate); \
div = (u16)lrate; \
\
if (!div) \
return -EINVAL; \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
reg &= ~BM_CLKCTRL_##rs##_DIV; \
reg |= div << BP_CLKCTRL_##rs##_DIV; \
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
\
for (i = 10000; i; i--) \
if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY)) \
break; \
if (!i) { \
pr_err("%s: divider writing timeout\n", __func__); \
return -ETIMEDOUT; \
} \
\
return 0; \
}
_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
#define _CLK_SET_RATE_STUB(name) \
static int name##_set_rate(struct clk *clk, unsigned long rate) \
{ \
return -EINVAL; \
}
_CLK_SET_RATE_STUB(emi_clk)
_CLK_SET_RATE_STUB(uart_clk)
_CLK_SET_RATE_STUB(pwm_clk)
_CLK_SET_RATE_STUB(spdif_clk)
_CLK_SET_RATE_STUB(clk32k_clk)
_CLK_SET_RATE_STUB(can0_clk)
_CLK_SET_RATE_STUB(can1_clk)
_CLK_SET_RATE_STUB(fec_clk)
/*
* clk_set_parent
*/
#define _CLK_SET_PARENT(name, bit) \
static int name##_set_parent(struct clk *clk, struct clk *parent) \
{ \
if (parent != clk->parent) { \
__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
HW_CLKCTRL_CLKSEQ_TOG); \
clk->parent = parent; \
} \
\
return 0; \
}
_CLK_SET_PARENT(cpu_clk, CPU)
_CLK_SET_PARENT(emi_clk, EMI)
_CLK_SET_PARENT(ssp0_clk, SSP0)
_CLK_SET_PARENT(ssp1_clk, SSP1)
_CLK_SET_PARENT(ssp2_clk, SSP2)
_CLK_SET_PARENT(ssp3_clk, SSP3)
_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
_CLK_SET_PARENT(gpmi_clk, GPMI)
_CLK_SET_PARENT(saif0_clk, SAIF0)
_CLK_SET_PARENT(saif1_clk, SAIF1)
#define _CLK_SET_PARENT_STUB(name) \
static int name##_set_parent(struct clk *clk, struct clk *parent) \
{ \
if (parent != clk->parent) \
return -EINVAL; \
else \
return 0; \
}
_CLK_SET_PARENT_STUB(pwm_clk)
_CLK_SET_PARENT_STUB(uart_clk)
_CLK_SET_PARENT_STUB(clk32k_clk)
_CLK_SET_PARENT_STUB(spdif_clk)
_CLK_SET_PARENT_STUB(fec_clk)
_CLK_SET_PARENT_STUB(can0_clk)
_CLK_SET_PARENT_STUB(can1_clk)
/*
* clk definition
*/
static struct clk cpu_clk = {
.get_rate = cpu_clk_get_rate,
.set_rate = cpu_clk_set_rate,
.set_parent = cpu_clk_set_parent,
.parent = &ref_cpu_clk,
};
static struct clk hbus_clk = {
.get_rate = hbus_clk_get_rate,
.parent = &cpu_clk,
};
static struct clk xbus_clk = {
.get_rate = xbus_clk_get_rate,
.set_rate = xbus_clk_set_rate,
.parent = &ref_xtal_clk,
};
static struct clk lradc_clk = {
.get_rate = lradc_clk_get_rate,
.parent = &clk32k_clk,
};
static struct clk rtc_clk = {
.get_rate = rtc_clk_get_rate,
.parent = &ref_xtal_clk,
};
/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
static struct clk usb0_clk = {
.enable_reg = DIGCTRL_BASE_ADDR,
.enable_shift = 2,
.enable = _raw_clk_enable,
.disable = _raw_clk_disable,
.parent = &pll0_clk,
};
static struct clk usb1_clk = {
.enable_reg = DIGCTRL_BASE_ADDR,
.enable_shift = 16,
.enable = _raw_clk_enable,
.disable = _raw_clk_disable,
.parent = &pll1_clk,
};
#define _DEFINE_CLOCK(name, er, es, p) \
static struct clk name = { \
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
.enable_shift = BP_CLKCTRL_##er##_##es, \
.get_rate = name##_get_rate, \
.set_rate = name##_set_rate, \
.set_parent = name##_set_parent, \
.enable = _raw_clk_enable, \
.disable = _raw_clk_disable, \
.parent = p, \
}
_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = &c, \
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK("pll2", NULL, pll2_clk)
_REGISTER_CLOCK(NULL, "hclk", hbus_clk)
_REGISTER_CLOCK(NULL, "xclk", xbus_clk)
_REGISTER_CLOCK(NULL, "can0", can0_clk)
_REGISTER_CLOCK(NULL, "can1", can1_clk)
_REGISTER_CLOCK(NULL, "usb0", usb0_clk)
_REGISTER_CLOCK(NULL, "usb1", usb1_clk)
_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
_REGISTER_CLOCK(NULL, "lradc", lradc_clk)
_REGISTER_CLOCK(NULL, "spdif", spdif_clk)
};
static int clk_misc_init(void)
{
u32 reg;
int i;
/* Fix up parent per register setting */
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
&ref_xtal_clk : &ref_cpu_clk;
emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
&ref_xtal_clk : &ref_emi_clk;
ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
&ref_xtal_clk : &ref_io0_clk;
ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
&ref_xtal_clk : &ref_io0_clk;
ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
&ref_xtal_clk : &ref_io1_clk;
ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
&ref_xtal_clk : &ref_io1_clk;
lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
&ref_xtal_clk : &ref_pix_clk;
gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
&ref_xtal_clk : &ref_gpmi_clk;
saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
&ref_xtal_clk : &pll0_clk;
saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
&ref_xtal_clk : &pll0_clk;
/* Use int div over frac when both are available */
__raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
__raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
__raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
/* SAIF has to use frac div for functional operation */
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
/*
* Set safe hbus clock divider. A divider of 3 ensure that
* the Vddd voltage required for the cpu clock is sufficiently
* high for the hbus clock.
*/
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
reg &= BM_CLKCTRL_HBUS_DIV;
reg |= 3 << BP_CLKCTRL_HBUS_DIV;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
for (i = 10000; i; i--)
if (!(__raw_readl(CLKCTRL_BASE_ADDR +
HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
break;
if (!i) {
pr_err("%s: divider writing timeout\n", __func__);
return -ETIMEDOUT;
}
/* Gate off cpu clock in WFI for power saving */
__raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
/* Extra fec clock setting */
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
reg &= ~BM_CLKCTRL_ENET_SLEEP;
reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
return 0;
}
int __init mx28_clocks_init(void)
{
clk_misc_init();
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
return 0;
}

200
arch/arm/mach-mxs/clock.c Normal file
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@ -0,0 +1,200 @@
/*
* Based on arch/arm/plat-omap/clock.c
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
/* #define DEBUG */
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/proc_fs.h>
#include <linux/semaphore.h>
#include <linux/string.h>
#include <mach/clock.h>
static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);
/*-------------------------------------------------------------------------
* Standard clock functions defined in include/linux/clk.h
*-------------------------------------------------------------------------*/
static void __clk_disable(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return;
WARN_ON(!clk->usecount);
if (!(--clk->usecount)) {
if (clk->disable)
clk->disable(clk);
__clk_disable(clk->parent);
__clk_disable(clk->secondary);
}
}
static int __clk_enable(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
if (clk->usecount++ == 0) {
__clk_enable(clk->parent);
__clk_enable(clk->secondary);
if (clk->enable)
clk->enable(clk);
}
return 0;
}
/* This function increments the reference count on the clock and enables the
* clock if not already enabled. The parent clock tree is recursively enabled
*/
int clk_enable(struct clk *clk)
{
int ret = 0;
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
mutex_lock(&clocks_mutex);
ret = __clk_enable(clk);
mutex_unlock(&clocks_mutex);
return ret;
}
EXPORT_SYMBOL(clk_enable);
/* This function decrements the reference count on the clock and disables
* the clock when reference count is 0. The parent clock tree is
* recursively disabled
*/
void clk_disable(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return;
mutex_lock(&clocks_mutex);
__clk_disable(clk);
mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clk_disable);
/* Retrieve the *current* clock rate. If the clock itself
* does not provide a special calculation routine, ask
* its parent and so on, until one is able to return
* a valid clock rate
*/
unsigned long clk_get_rate(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return 0UL;
if (clk->get_rate)
return clk->get_rate(clk);
return clk_get_rate(clk->parent);
}
EXPORT_SYMBOL(clk_get_rate);
/* Round the requested clock rate to the nearest supported
* rate that is less than or equal to the requested rate.
* This is dependent on the clock's current parent.
*/
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
return 0;
return clk->round_rate(clk, rate);
}
EXPORT_SYMBOL(clk_round_rate);
/* Set the clock to the requested clock rate. The rate must
* match a supported rate exactly based on what clk_round_rate returns
*/
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
return ret;
mutex_lock(&clocks_mutex);
ret = clk->set_rate(clk, rate);
mutex_unlock(&clocks_mutex);
return ret;
}
EXPORT_SYMBOL(clk_set_rate);
/* Set the clock's parent to another clock source */
int clk_set_parent(struct clk *clk, struct clk *parent)
{
int ret = -EINVAL;
struct clk *old;
if (clk == NULL || IS_ERR(clk) || parent == NULL ||
IS_ERR(parent) || clk->set_parent == NULL)
return ret;
if (clk->usecount)
clk_enable(parent);
mutex_lock(&clocks_mutex);
ret = clk->set_parent(clk, parent);
if (ret == 0) {
old = clk->parent;
clk->parent = parent;
} else {
old = parent;
}
mutex_unlock(&clocks_mutex);
if (clk->usecount)
clk_disable(old);
return ret;
}
EXPORT_SYMBOL(clk_set_parent);
/* Retrieve the clock's parent clock source */
struct clk *clk_get_parent(struct clk *clk)
{
struct clk *ret = NULL;
if (clk == NULL || IS_ERR(clk))
return ret;
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);

16
arch/arm/mach-mxs/devices-mx23.h Normal file
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/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx23.h>
#include <mach/devices-common.h>
extern const struct mxs_duart_data mx23_duart_data __initconst;
#define mx23_add_duart() \
mxs_add_duart(&mx23_duart_data)

20
arch/arm/mach-mxs/devices-mx28.h Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx28.h>
#include <mach/devices-common.h>
extern const struct mxs_duart_data mx28_duart_data __initconst;
#define mx28_add_duart() \
mxs_add_duart(&mx28_duart_data)
extern const struct mxs_fec_data mx28_fec_data[] __initconst;
#define mx28_add_fec(id, pdata) \
mxs_add_fec(&mx28_fec_data[id], pdata)

75
arch/arm/mach-mxs/devices.c Normal file
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@ -0,0 +1,75 @@
/*
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <mach/common.h>
struct platform_device *__init mxs_add_platform_device_dmamask(
const char *name, int id,
const struct resource *res, unsigned int num_resources,
const void *data, size_t size_data, u64 dmamask)
{
int ret = -ENOMEM;
struct platform_device *pdev;
pdev = platform_device_alloc(name, id);
if (!pdev)
goto err;
if (dmamask) {
/*
* This memory isn't freed when the device is put,
* I don't have a nice idea for that though. Conceptually
* dma_mask in struct device should not be a pointer.
* See http://thread.gmane.org/gmane.linux.kernel.pci/9081
*/
pdev->dev.dma_mask =
kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
if (!pdev->dev.dma_mask)
/* ret is still -ENOMEM; */
goto err;
*pdev->dev.dma_mask = dmamask;
pdev->dev.coherent_dma_mask = dmamask;
}
if (res) {
ret = platform_device_add_resources(pdev, res, num_resources);
if (ret)
goto err;
}
if (data) {
ret = platform_device_add_data(pdev, data, size_data);
if (ret)
goto err;
}
ret = platform_device_add(pdev);
if (ret) {
err:
platform_device_put(pdev);
return ERR_PTR(ret);
}
return pdev;
}

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