forked from Minki/linux
KVM: Add HYPER-V apic access MSRs
Implement HYPER-V apic MSRs. Spec defines three MSRs that speed-up access to EOI/TPR/ICR apic registers for PV guests. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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@ -363,6 +363,8 @@ struct kvm_vcpu_arch {
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/* used for guest single stepping over the given code position */
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u16 singlestep_cs;
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unsigned long singlestep_rip;
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/* fields used by HYPER-V emulation */
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u64 hv_vapic;
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};
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struct kvm_mem_alias {
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@ -1246,3 +1246,34 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
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return 0;
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}
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int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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if (!irqchip_in_kernel(vcpu->kvm))
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return 1;
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/* if this is ICR write vector before command */
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if (reg == APIC_ICR)
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apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
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return apic_reg_write(apic, reg, (u32)data);
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}
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int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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u32 low, high = 0;
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if (!irqchip_in_kernel(vcpu->kvm))
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return 1;
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if (apic_reg_read(apic, reg, 4, &low))
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return 1;
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if (reg == APIC_ICR)
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apic_reg_read(apic, APIC_ICR2, 4, &high);
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*data = (((u64)high) << 32) | low;
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return 0;
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}
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@ -48,4 +48,12 @@ void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
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int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
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}
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#endif
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@ -622,10 +622,11 @@ static inline u32 bit(int bitno)
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* kvm-specific. Those are put in the beginning of the list.
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*/
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#define KVM_SAVE_MSRS_BEGIN 4
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#define KVM_SAVE_MSRS_BEGIN 5
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static u32 msrs_to_save[] = {
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MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
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HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
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HV_X64_MSR_APIC_ASSIST_PAGE,
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MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
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MSR_K6_STAR,
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#ifdef CONFIG_X86_64
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@ -1067,10 +1068,36 @@ static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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{
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pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x data 0x%llx\n",
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msr, data);
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switch (msr) {
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case HV_X64_MSR_APIC_ASSIST_PAGE: {
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unsigned long addr;
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return 1;
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if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
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vcpu->arch.hv_vapic = data;
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break;
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}
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addr = gfn_to_hva(vcpu->kvm, data >>
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HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
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if (kvm_is_error_hva(addr))
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return 1;
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if (clear_user((void __user *)addr, PAGE_SIZE))
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return 1;
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vcpu->arch.hv_vapic = data;
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break;
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}
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case HV_X64_MSR_EOI:
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return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
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case HV_X64_MSR_ICR:
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return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
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case HV_X64_MSR_TPR:
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return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
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default:
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pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
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"data 0x%llx\n", msr, data);
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return 1;
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}
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return 0;
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}
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int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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@ -1330,6 +1357,12 @@ static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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data = r;
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break;
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}
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case HV_X64_MSR_EOI:
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return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
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case HV_X64_MSR_ICR:
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return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
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case HV_X64_MSR_TPR:
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return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
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default:
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pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
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return 1;
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@ -1530,6 +1563,7 @@ int kvm_dev_ioctl_check_extension(long ext)
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case KVM_CAP_ADJUST_CLOCK:
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case KVM_CAP_VCPU_EVENTS:
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case KVM_CAP_HYPERV:
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case KVM_CAP_HYPERV_VAPIC:
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r = 1;
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break;
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case KVM_CAP_COALESCED_MMIO:
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@ -498,6 +498,7 @@ struct kvm_ioeventfd {
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#define KVM_CAP_S390_PSW 42
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#define KVM_CAP_PPC_SEGSTATE 43
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#define KVM_CAP_HYPERV 44
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#define KVM_CAP_HYPERV_VAPIC 45
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#ifdef KVM_CAP_IRQ_ROUTING
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