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x86/intel/lpss: Add pin control support to Intel low power subsystem

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x86 chips with LPSS (low power subsystem) such as Lynxpoint and
Baytrail have SoC like peripheral support and controllable pins.

At the moment, Baytrail needs the pinctrl-baytrail driver to let
peripherals control their gpio resources, but more pincontrol
functions such as pin muxing and grouping are possible to add
later.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: http://lkml.kernel.org/r/1379080949-21734-1-git-send-email-mathias.nyman@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Mathias Nyman 2013-09-13 17:02:29 +03:00 committed by Ingo Molnar
parent 9d8e3f9693
commit 0f531431d3
1 changed files with 3 additions and 2 deletions
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5
arch/x86/Kconfig
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@ -482,11 +482,12 @@ config X86_INTEL_LPSS
bool "Intel Low Power Subsystem Support"
depends on ACPI
select COMMON_CLK
select PINCTRL
---help---
Select to build support for Intel Low Power Subsystem such as
found on Intel Lynxpoint PCH. Selecting this option enables
things like clock tree (common clock framework) which are needed
by the LPSS peripheral drivers.
things like clock tree (common clock framework) and pincontrol
which are needed by the LPSS peripheral drivers.
config X86_RDC321X
bool "RDC R-321x SoC"