arm64: sysreg: subsume GICv3 sysreg definitions
Unlike most sysreg defintiions, the GICv3 definitions don't have a SYS_ prefix, and they don't live in <asm/sysreg.h>. Additionally, some definitions are duplicated elsewhere (e.g. in the KVM save/restore code). For consistency, and to make it possible to share a common definition for these sysregs, this patch moves the definitions to <asm/sysreg.h>, adding a SYS_ prefix, and sorting the registers per their encoding. Existing users of the definitions are fixed up so that this change is not problematic. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Mark Rutland
parent
c7a3c61fc6
commit
0e9884fe63
@ -20,69 +20,14 @@
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#include <asm/sysreg.h>
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#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
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#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
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#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
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#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
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#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
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#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
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#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
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#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
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#define ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
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#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
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/*
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* System register definitions
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*/
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#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
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#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
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#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
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#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
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#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
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#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
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#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
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#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
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#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
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#define ICH_LR0_EL2 __LR0_EL2(0)
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#define ICH_LR1_EL2 __LR0_EL2(1)
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#define ICH_LR2_EL2 __LR0_EL2(2)
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#define ICH_LR3_EL2 __LR0_EL2(3)
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#define ICH_LR4_EL2 __LR0_EL2(4)
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#define ICH_LR5_EL2 __LR0_EL2(5)
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#define ICH_LR6_EL2 __LR0_EL2(6)
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#define ICH_LR7_EL2 __LR0_EL2(7)
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#define ICH_LR8_EL2 __LR8_EL2(0)
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#define ICH_LR9_EL2 __LR8_EL2(1)
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#define ICH_LR10_EL2 __LR8_EL2(2)
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#define ICH_LR11_EL2 __LR8_EL2(3)
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#define ICH_LR12_EL2 __LR8_EL2(4)
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#define ICH_LR13_EL2 __LR8_EL2(5)
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#define ICH_LR14_EL2 __LR8_EL2(6)
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#define ICH_LR15_EL2 __LR8_EL2(7)
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#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
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#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
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#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
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#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
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#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
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#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
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#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
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#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
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#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
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#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
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#ifndef __ASSEMBLY__
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#include <linux/stringify.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#define read_gicreg read_sysreg_s
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#define write_gicreg write_sysreg_s
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#define read_gicreg(r) read_sysreg_s(SYS_ ## r)
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#define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
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/*
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* Low-level accessors
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@ -93,13 +38,13 @@
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static inline void gic_write_eoir(u32 irq)
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{
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write_sysreg_s(irq, ICC_EOIR1_EL1);
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write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
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isb();
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}
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static inline void gic_write_dir(u32 irq)
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{
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write_sysreg_s(irq, ICC_DIR_EL1);
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write_sysreg_s(irq, SYS_ICC_DIR_EL1);
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isb();
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}
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@ -107,7 +52,7 @@ static inline u64 gic_read_iar_common(void)
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{
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u64 irqstat;
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irqstat = read_sysreg_s(ICC_IAR1_EL1);
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irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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dsb(sy);
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return irqstat;
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}
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@ -124,7 +69,7 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
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u64 irqstat;
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nops(8);
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irqstat = read_sysreg_s(ICC_IAR1_EL1);
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irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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nops(4);
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mb();
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@ -133,40 +78,40 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
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static inline void gic_write_pmr(u32 val)
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{
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write_sysreg_s(val, ICC_PMR_EL1);
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write_sysreg_s(val, SYS_ICC_PMR_EL1);
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}
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static inline void gic_write_ctlr(u32 val)
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{
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write_sysreg_s(val, ICC_CTLR_EL1);
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write_sysreg_s(val, SYS_ICC_CTLR_EL1);
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isb();
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}
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static inline void gic_write_grpen1(u32 val)
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{
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write_sysreg_s(val, ICC_GRPEN1_EL1);
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write_sysreg_s(val, SYS_ICC_GRPEN1_EL1);
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isb();
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}
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static inline void gic_write_sgi1r(u64 val)
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{
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write_sysreg_s(val, ICC_SGI1R_EL1);
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write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
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}
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static inline u32 gic_read_sre(void)
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{
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return read_sysreg_s(ICC_SRE_EL1);
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return read_sysreg_s(SYS_ICC_SRE_EL1);
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}
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static inline void gic_write_sre(u32 val)
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{
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write_sysreg_s(val, ICC_SRE_EL1);
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write_sysreg_s(val, SYS_ICC_SRE_EL1);
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isb();
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}
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static inline void gic_write_bpr1(u32 val)
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{
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asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
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write_sysreg_s(val, SYS_ICC_BPR1_EL1);
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}
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#define gic_read_typer(c) readq_relaxed(c)
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@ -149,9 +149,20 @@
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#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
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#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
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#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
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#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
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#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
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#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
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#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
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#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
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#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
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#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
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#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
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#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
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#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
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#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
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#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
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@ -179,6 +190,47 @@
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#define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
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#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
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#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
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#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
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#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
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#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
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#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
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#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
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#define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
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#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
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#define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
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#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
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#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
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#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
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#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
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#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
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#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
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#define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
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#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
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#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
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#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
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#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
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#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
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#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
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#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
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#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
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#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
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#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
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#define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
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#define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
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#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
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#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
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#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
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#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
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#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
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#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
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#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
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/* Common SCTLR_ELx flags. */
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#define SCTLR_ELx_EE (1 << 25)
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#define SCTLR_ELx_I (1 << 12)
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@ -594,14 +594,14 @@ set_hcr:
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cmp x0, #1
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b.ne 3f
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mrs_s x0, ICC_SRE_EL2
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mrs_s x0, SYS_ICC_SRE_EL2
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orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
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orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
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msr_s ICC_SRE_EL2, x0
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msr_s SYS_ICC_SRE_EL2, x0
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isb // Make sure SRE is now set
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mrs_s x0, ICC_SRE_EL2 // Read SRE back,
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mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
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tbz x0, #0, 3f // and check that it sticks
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msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
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msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
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3:
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#endif
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