forked from Minki/linux
usb: dwc3: add support for USB 2.0-only core configuration
Newer DWC3 controllers can be built for USB 2.0-only mode, where most of the USB 3.0 circuitry is left out. To support this mode, the driver must limit the speed programmed into the DCFG register to Hi-Speed or lower. Reads and writes to the PIPECTL register are left as-is, since they should be no-ops in USB 2.0-only mode. Calls to phy_init() etc. for the USB3 phy are also left as-is, since the no-op USB3 phy should be used for USB 2.0-only mode controllers. Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -386,6 +386,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
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}
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dwc->revision = reg;
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/* Handle USB2.0-only core configuration */
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if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
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DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
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if (dwc->maximum_speed == USB_SPEED_SUPER)
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dwc->maximum_speed = USB_SPEED_HIGH;
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}
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/* issue device SoftReset too */
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timeout = jiffies + msecs_to_jiffies(500);
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dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
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@ -191,6 +191,19 @@
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#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
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#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
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/* Global HWPARAMS3 Register */
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#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
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#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
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#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
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#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
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#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
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#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
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#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
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#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
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#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
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#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
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#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
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/* Global HWPARAMS4 Register */
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#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
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#define DWC3_MAX_HIBER_SCRATCHBUFS 15
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