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arm64: dts: renesas: r8a774c0: Add PCIe EP node

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Add PCIe EP node to R8A774C0 (RZ/G2E) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2020-08-14 18:30:37 +01:00
committed by Geert Uytterhoeven
parent d12d16205f
commit 0c77ecdcfc
1 changed files with 19 additions and 0 deletions
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19
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
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@@ -1698,6 +1698,25 @@
status = "disabled"; status = "disabled";
}; };
pciec0_ep: pcie-ep@fe000000 {
compatible = "renesas,r8a774c0-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0x0 0xfe000000 0 0x80000>,
<0x0 0xfe100000 0 0x100000>,
<0x0 0xfe200000 0 0x200000>,
<0x0 0x30000000 0 0x8000000>,
<0x0 0x38000000 0 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>;
clock-names = "pcie";
resets = <&cpg 319>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
status = "disabled";
};
vspb0: vsp@fe960000 { vspb0: vsp@fe960000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>; reg = <0 0xfe960000 0 0x8000>;