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drm/amd/display: Use SMU ClockTable Values for DML Calculations

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[Why]
DML Initialization was previously done on dcn21_resource initialization.
This meant that DML soc struct was populated with hardcoded values.

[How]
Move DML initialization to after updating bounding box, to use clock table
values from SMU.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sung Lee
2019-12-19 11:37:49 -05:00
committed by Alex Deucher
parent 51f2af1d83
commit 08f6c85921
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
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@@ -1349,6 +1349,10 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
} }
dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - 1]; dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - 1];
dcn2_1_soc.num_states = i; dcn2_1_soc.num_states = i;
// diags does not retrieve proper values from SMU, do not update DML instance for diags
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment))
dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
} }
/* Temporary Place holder until we can get them from fuse */ /* Temporary Place holder until we can get them from fuse */