forked from Minki/linux
MIPS: math-emu: Remove most ifdefery.
Most of these tests should be runtime tests. This also finally means that on a MIPS III systems MIPS IV opcodes are going to result in an exception as they're supposed to. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
9e8bad1f9c
commit
08a07904e1
@ -183,6 +183,17 @@
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/*
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* Shortcuts ...
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*/
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#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
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#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
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#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
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#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
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#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
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#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
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#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
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#define cpu_has_mips_4_5_r2 (cpu_has_mips_4_5 | cpu_has_mips_r2)
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#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
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#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
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#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
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@ -35,6 +35,7 @@
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*/
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#include <linux/sched.h>
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#include <linux/debugfs.h>
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#include <linux/kconfig.h>
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#include <linux/percpu-defs.h>
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#include <linux/perf_event.h>
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@ -50,22 +51,13 @@
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#include "ieee754.h"
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/* Strap kernel emulator for full MIPS IV emulation */
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#ifdef __mips
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#undef __mips
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#endif
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#define __mips 4
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/* Function which emulates a floating point instruction. */
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static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
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mips_instruction);
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#if __mips >= 4 && __mips != 32
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static int fpux_emu(struct pt_regs *,
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struct mips_fpu_struct *, mips_instruction, void *__user *);
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#endif
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/* Control registers */
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@ -95,7 +87,6 @@ static const unsigned char mips_rm[4] = {
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[IEEE754_RU] = FPU_CSR_RU,
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};
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#if __mips >= 4
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/* convert condition code register number to csr bit */
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static const unsigned int fpucondbit[8] = {
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FPU_CSR_COND0,
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@ -107,7 +98,6 @@ static const unsigned int fpucondbit[8] = {
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FPU_CSR_COND6,
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FPU_CSR_COND7
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};
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#endif
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/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
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static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
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@ -860,13 +850,13 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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*/
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static inline int cop1_64bit(struct pt_regs *xcp)
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{
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#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
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return 1;
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#elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
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return 0;
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#else
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if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
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return 1;
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else if (config_enabled(CONFIG_32BIT) &&
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!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
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return 0;
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return !test_thread_flag(TIF_32BIT_FPREGS);
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#endif
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}
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#define SIFROMREG(si, x) \
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@ -1070,8 +1060,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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case cop1_op:
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switch (MIPSInst_RS(ir)) {
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#if defined(__mips64)
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case dmfc_op:
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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return SIGILL;
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/* copregister fs -> gpr[rt] */
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if (MIPSInst_RT(ir) != 0) {
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DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
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@ -1080,10 +1072,12 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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break;
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case dmtc_op:
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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return SIGILL;
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/* copregister fs <- rt */
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DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
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break;
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#endif
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case mfhc_op:
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if (!cpu_has_mips_r2)
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@ -1173,16 +1167,18 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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}
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case bc_op:{
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unsigned int cbit;
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int likely = 0;
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if (delay_slot(xcp))
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return SIGILL;
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#if __mips >= 4
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cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
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#else
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cond = ctx->fcr31 & FPU_CSR_COND;
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#endif
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if (cpu_has_mips_4_5_r)
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cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
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else
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cbit = FPU_CSR_COND;
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cond = ctx->fcr31 & cbit;
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switch (MIPSInst_RT(ir) & 3) {
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case bcfl_op:
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likely = 1;
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@ -1235,23 +1231,32 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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switch (MIPSInst_OPCODE(ir)) {
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case lwc1_op:
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goto emul;
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case swc1_op:
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#if (__mips >= 2 || defined(__mips64))
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goto emul;
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case ldc1_op:
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case sdc1_op:
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#endif
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case cop1_op:
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#if __mips >= 4 && __mips != 32
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case cop1x_op:
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#endif
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/* its one of ours */
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if (cpu_has_mips_2_3_4_5 ||
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cpu_has_mips64)
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goto emul;
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return SIGILL;
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goto emul;
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#if __mips >= 4
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case cop1_op:
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goto emul;
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case cop1x_op:
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if (cpu_has_mips_4_5 || cpu_has_mips64)
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/* its one of ours */
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goto emul;
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return SIGILL;
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case spec_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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if (MIPSInst_FUNC(ir) == movc_op)
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goto emul;
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break;
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#endif
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}
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/*
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@ -1291,17 +1296,22 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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}
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break;
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#if __mips >= 4 && __mips != 32
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case cop1x_op:{
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int sig = fpux_emu(xcp, ctx, ir, fault_addr);
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int sig;
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if (!cpu_has_mips_4_5 && !cpu_has_mips64)
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return SIGILL;
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sig = fpux_emu(xcp, ctx, ir, fault_addr);
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if (sig)
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return sig;
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break;
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}
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#endif
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#if __mips >= 4
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case spec_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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if (MIPSInst_FUNC(ir) != movc_op)
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return SIGILL;
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cond = fpucondbit[MIPSInst_RT(ir) >> 2];
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@ -1309,8 +1319,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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xcp->regs[MIPSInst_RD(ir)] =
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xcp->regs[MIPSInst_RS(ir)];
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break;
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#endif
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default:
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sigill:
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return SIGILL;
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@ -1339,8 +1347,6 @@ static const unsigned char cmptab[8] = {
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};
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#if __mips >= 4 && __mips != 32
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/*
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* Additional MIPS4 instructions
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*/
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@ -1571,7 +1577,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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return 0;
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}
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#endif
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@ -1588,9 +1593,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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union ieee754dp d;
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union ieee754sp s;
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int w;
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#ifdef __mips64
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s64 l;
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#endif
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} rv; /* resulting value */
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MIPS_FPU_EMU_INC_STATS(cp1ops);
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@ -1617,21 +1620,34 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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goto scopbop;
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/* unary ops */
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#if __mips >= 2 || defined(__mips64)
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case fsqrt_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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handler.u = ieee754sp_sqrt;
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goto scopuop;
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#endif
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#if __mips >= 4 && __mips != 32
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/*
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* Note that on some MIPS IV implementations such as the
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* R5000 and R8000 the FSQRT and FRECIP instructions do not
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* achieve full IEEE-754 accuracy - however this emulator does.
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*/
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case frsqrt_op:
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if (!cpu_has_mips_4_5_r2)
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return SIGILL;
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handler.u = fpemu_sp_rsqrt;
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goto scopuop;
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case frecip_op:
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if (!cpu_has_mips_4_5_r2)
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return SIGILL;
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handler.u = fpemu_sp_recip;
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goto scopuop;
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#endif
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#if __mips >= 4
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case fmovc_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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cond = fpucondbit[MIPSInst_FT(ir) >> 2];
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if (((ctx->fcr31 & cond) != 0) !=
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((MIPSInst_FT(ir) & 1) != 0))
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@ -1639,16 +1655,21 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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SPFROMREG(rv.s, MIPSInst_FS(ir));
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break;
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case fmovz_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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if (xcp->regs[MIPSInst_FT(ir)] != 0)
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return 0;
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SPFROMREG(rv.s, MIPSInst_FS(ir));
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break;
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case fmovn_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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if (xcp->regs[MIPSInst_FT(ir)] == 0)
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return 0;
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SPFROMREG(rv.s, MIPSInst_FS(ir));
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break;
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#endif
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case fabs_op:
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handler.u = ieee754sp_abs;
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goto scopuop;
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@ -1712,7 +1733,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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goto copcsr;
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}
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#if __mips >= 2 || defined(__mips64)
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case fround_op:
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case ftrunc_op:
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case fceil_op:
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@ -1720,6 +1740,9 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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unsigned int oldrm = ieee754_csr.rm;
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union ieee754sp fs;
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if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
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return SIGILL;
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SPFROMREG(fs, MIPSInst_FS(ir));
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ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
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rv.w = ieee754sp_tint(fs);
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@ -1727,12 +1750,13 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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rfmt = w_fmt;
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goto copcsr;
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}
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#endif /* __mips >= 2 */
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#if defined(__mips64)
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case fcvtl_op:{
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union ieee754sp fs;
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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return SIGILL;
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SPFROMREG(fs, MIPSInst_FS(ir));
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rv.l = ieee754sp_tlong(fs);
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rfmt = l_fmt;
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@ -1746,6 +1770,9 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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unsigned int oldrm = ieee754_csr.rm;
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union ieee754sp fs;
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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return SIGILL;
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SPFROMREG(fs, MIPSInst_FS(ir));
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ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
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rv.l = ieee754sp_tlong(fs);
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@ -1753,7 +1780,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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rfmt = l_fmt;
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goto copcsr;
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}
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#endif /* defined(__mips64) */
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default:
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if (MIPSInst_FUNC(ir) >= fcmp_op) {
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@ -1802,21 +1828,33 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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goto dcopbop;
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/* unary ops */
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#if __mips >= 2 || defined(__mips64)
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case fsqrt_op:
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if (!cpu_has_mips_2_3_4_5_r)
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return SIGILL;
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handler.u = ieee754dp_sqrt;
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goto dcopuop;
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#endif
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#if __mips >= 4 && __mips != 32
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/*
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* Note that on some MIPS IV implementations such as the
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* R5000 and R8000 the FSQRT and FRECIP instructions do not
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* achieve full IEEE-754 accuracy - however this emulator does.
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*/
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case frsqrt_op:
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if (!cpu_has_mips_4_5_r2)
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return SIGILL;
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handler.u = fpemu_dp_rsqrt;
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goto dcopuop;
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case frecip_op:
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if (!cpu_has_mips_4_5_r2)
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return SIGILL;
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handler.u = fpemu_dp_recip;
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goto dcopuop;
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#endif
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#if __mips >= 4
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case fmovc_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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cond = fpucondbit[MIPSInst_FT(ir) >> 2];
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if (((ctx->fcr31 & cond) != 0) !=
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((MIPSInst_FT(ir) & 1) != 0))
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@ -1824,16 +1862,21 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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DPFROMREG(rv.d, MIPSInst_FS(ir));
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break;
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case fmovz_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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if (xcp->regs[MIPSInst_FT(ir)] != 0)
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return 0;
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DPFROMREG(rv.d, MIPSInst_FS(ir));
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break;
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case fmovn_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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if (xcp->regs[MIPSInst_FT(ir)] == 0)
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return 0;
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DPFROMREG(rv.d, MIPSInst_FS(ir));
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break;
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#endif
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case fabs_op:
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handler.u = ieee754dp_abs;
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goto dcopuop;
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@ -1886,7 +1929,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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goto copcsr;
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}
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#if __mips >= 2 || defined(__mips64)
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case fround_op:
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case ftrunc_op:
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case fceil_op:
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@ -1894,6 +1936,9 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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unsigned int oldrm = ieee754_csr.rm;
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union ieee754dp fs;
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if (!cpu_has_mips_2_3_4_5_r)
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return SIGILL;
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DPFROMREG(fs, MIPSInst_FS(ir));
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ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
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rv.w = ieee754dp_tint(fs);
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@ -1901,12 +1946,13 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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rfmt = w_fmt;
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goto copcsr;
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}
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#endif
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#if defined(__mips64)
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case fcvtl_op:{
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union ieee754dp fs;
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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return SIGILL;
|
||||
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.l = ieee754dp_tlong(fs);
|
||||
rfmt = l_fmt;
|
||||
@ -1920,6 +1966,9 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
unsigned int oldrm = ieee754_csr.rm;
|
||||
union ieee754dp fs;
|
||||
|
||||
if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
|
||||
return SIGILL;
|
||||
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
|
||||
rv.l = ieee754dp_tlong(fs);
|
||||
@ -1927,7 +1976,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
rfmt = l_fmt;
|
||||
goto copcsr;
|
||||
}
|
||||
#endif /* __mips >= 3 */
|
||||
|
||||
default:
|
||||
if (MIPSInst_FUNC(ir) >= fcmp_op) {
|
||||
@ -1978,9 +2026,12 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
break;
|
||||
}
|
||||
|
||||
#if defined(__mips64)
|
||||
case l_fmt:{
|
||||
u64 bits;
|
||||
|
||||
if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
|
||||
return SIGILL;
|
||||
|
||||
DIFROMREG(bits, MIPSInst_FS(ir));
|
||||
|
||||
switch (MIPSInst_FUNC(ir)) {
|
||||
@ -1999,7 +2050,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
}
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
default:
|
||||
return SIGILL;
|
||||
@ -2022,18 +2072,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
* Now we can safely write the result back to the register file.
|
||||
*/
|
||||
switch (rfmt) {
|
||||
case -1:{
|
||||
#if __mips >= 4
|
||||
cond = fpucondbit[MIPSInst_FD(ir) >> 2];
|
||||
#else
|
||||
cond = FPU_CSR_COND;
|
||||
#endif
|
||||
if (rv.w)
|
||||
ctx->fcr31 |= cond;
|
||||
unsigned int cbit;
|
||||
case -1:
|
||||
|
||||
if (cpu_has_mips_4_5_r)
|
||||
cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
|
||||
else
|
||||
ctx->fcr31 &= ~cond;
|
||||
cbit = FPU_CSR_COND;
|
||||
if (rv.w)
|
||||
ctx->fcr31 |= cbit;
|
||||
else
|
||||
ctx->fcr31 &= ~cbit;
|
||||
break;
|
||||
}
|
||||
|
||||
case d_fmt:
|
||||
DPTOREG(rv.d, MIPSInst_FD(ir));
|
||||
break;
|
||||
@ -2043,11 +2094,12 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
case w_fmt:
|
||||
SITOREG(rv.w, MIPSInst_FD(ir));
|
||||
break;
|
||||
#if defined(__mips64)
|
||||
case l_fmt:
|
||||
if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
|
||||
return SIGILL;
|
||||
|
||||
DITOREG(rv.l, MIPSInst_FD(ir));
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return SIGILL;
|
||||
}
|
||||
|
@ -45,15 +45,14 @@
|
||||
/* special constants
|
||||
*/
|
||||
|
||||
|
||||
#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__)
|
||||
#define SPSTR(s, b, m) {m, b, s}
|
||||
#define DPSTR(s, b, mh, ml) {ml, mh, b, s}
|
||||
#endif
|
||||
|
||||
#ifdef __MIPSEB__
|
||||
#define SPSTR(s, b, m) {s, b, m}
|
||||
#define DPSTR(s, b, mh, ml) {s, b, mh, ml}
|
||||
#elif defined(__MIPSEL__)
|
||||
#define SPSTR(s, b, m) {m, b, s}
|
||||
#define DPSTR(s, b, mh, ml) {ml, mh, b, s}
|
||||
#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
|
||||
#error "MIPS but neither __MIPSEB__ nor __MIPSEL__?"
|
||||
#endif
|
||||
|
||||
const struct ieee754dp_const __ieee754dp_spcvals[] = {
|
||||
|
Loading…
Reference in New Issue
Block a user